Sony ILX532A Datasheet
7500-pixel CCD Linear Sensor (B/W)
Description
The ILX532A is a reduction type CCD linear sensor
developed for high resolution copiers. This sensor
reads A3-size documents at a density of 600DPI, at
high speed.
Features
• Number of effective pixels: 7500 pixels
• Pixel size: 7µm × 7µm (7µm pitch)
• Clamp circuit are on-chip
• Signal output phase of two-output
simultaneous-output (alternate-output is available)
• Ultra high sensitivity/Ultra low lag
• Max Data Rate: 40MHz
• Single 12V power supply
• Input Clock Pulse: CMOS 5V drive
• Package: 28 pin Cer-DIP (400mil)
ILX532A
28 pin DIP (Cer-DIP)
Block Diagram
Absolute Maximum Ratings
• Supply voltage VDD 15 V
• Operating temperature –10 to +60 °C
• Storage temperature –30 to +80 °C
Pin Configuration (Top View)
ODD
GND
VGG
NC
NC
VDD
NC
NC
10
11
12
13
14
1
2
1
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
7500
16
15
EVEN
φCLP-
φRS-EVEN
φLH-EVEN
VDD
VOUT-EVEN
VDD
NC
NC
φ2-EVEN
GND
EVEN
φ1VDD
GND
NC
φCLP-
φRS-ODD
φLH-ODD
V
OUT-ODD
φ2-ODD
φ1-ODD
φROG
GND
VDD
EVEN
φ1-
φ2-EVEN
VDD
VDD
φLH-EVEN
φRS-EVEN
EVEN
φCLP-
19
D94
1718
D75
S7500
S7499
20
23
25
2627
28
CCD analog shift register
Output amplifier
24
VOUT-EVEN
S2
Read out gate
S1
D74
D26
D25
6
VGG
Read out gate
φROG pulse
generator
CCD analog shift register
Output amplifier
5
OUT-ODD
V
12
φROG
11
VDD
10
φ1-ODD
9
φ2-ODD
16
GND
φLH-ODD
2 34
φRS-ODD
ODD
1
φCLP-
GND
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E98344-PS
Pin Description
ILX532A
Pin
No.
10
11
12
13
14
Symbol Description
1
2
3
4
5
6
7
8
9
φCLP-ODD
φRS-ODD
φLH-ODD
GND
VOUT-ODD
VGG
NC
NC
φ2-ODD
φ1-ODD
VDD
φROG
NC
NC
Clock pulse input (odd pixel)
Clock pulse input (odd pixel)
Clock pulse input (odd pixel)
GND
Signal out (odd pixel)
Output circuit gate bias
NC
NC
Clock pulse input (odd pixel)
Clock pulse input (odd pixel)
12V power supply
Readout gate clock pulse input
NC
NC
Recommended Supply Voltage
Pin
No.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol Description
NC
GND
VDD
φ1-EVEN
GND
φ2-EVEN
NC
NC
VDD
VOUT-EVEN
VDD
φLH-EVEN
φRS-EVEN
φCLP-EVEN
NC
GND
12V power supply
Clock pulse input (even pixel)
GND
Clock pulse input (even pixel)
NC
NC
12V power supply
Signal out (even pixel)
12V power supply
Clock pulse input (even pixel)
Clock pulse input (even pixel)
Clock pulse input (even pixel)
Unit
V
VDD
Item
Min.
11.4
Typ.
12
Max.
12.6
Clock Characteristics
Item
Input capacity of φ1∗1, φ2
Input capacity of φLH
Input capacity of φRS
Input capacity of φCLP
∗1
∗1
∗1
∗1
Input capacity of φROG
∗1
It indicates that φ1-ODD, φ1-EVEN as φ1, φ2-ODD, φ2-EVEN as φ2, φLH-ODD, φLH-EVEN as φLH, φRS-ODD,
Symbol
Cφ1, Cφ2
CφLH
CφRS
CφCLP
CφROG
Min.
—
—
—
—
—
Typ.
500
10
10
10
10
φRS-EVEN as φRS, φCLP-ODD, φCLP-EVEN as φCLP.
Clock Frequency
Typ.
1
2
φ1, φ2, φLH, φRS, φCLP
Data rate
Symbol
fφ1, fφ2, fφLH, fφRS, fφCLP
fφR
Min.
—
—
Max.
—
—
—
—
—
Max.
20
40
Unit
pF
pF
pF
pF
pF
Unit
MHz
MHz
Input Clock Pulse Voltage Condition
φ1, φ2, φLH, φRS, φCLP, φROG pulse voltage
Low level
High level
– 2 –
Min.
—
4.75
Typ.
0
5.0
Max.
0.1
5.25
Unit
V
V
ILX532A
Electrooptical Characteristics (Note 1)
(Ta = 25°C, VDD = 12V, fφR = 2MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm))
Item
Sensitivity 1
Sensitivity 2
Sensitivity nonuniformity
Saturation output voltage
Saturation exposure
Register imbalance
Dark voltage average
Dark signal nonuniformity
Image lag
Supply current
Total transfer efficiency
Output impedance
Offset level
Notes)
1. In accordance with the given electrooptical characteristics, the even black level is defined as the average
value of D6, D8, to D24. The odd black level is defined as the average value of D5, D7, to D23.
2. For the sensitivity test light is applied with a uniform intensity of illumination.
3. W lamp (2854K)
4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
VOUT = 500mV (Typ.)
Symbol
R1
R2
PRNU
VSAT
SE
RI
VDRK
DSNU
IL
IVDD
TTE
Zo
VOS
Min.
8.2
—
—
1.8
0.13
—
—
—
—
—
92
—
—
Typ.
11
25.1
4
2.5
0.23
1
0.3
0.6
0.02
30
98
150
6.5
Max.
13.8
—
10
—
—
7
2.0
5.0
—
60
—
—
—
Unit
V/(lx · s)
V/(lx · s)
%
V
lx · s
%
mV
mV
%
mA
%
Ω
V
Remarks
Note 2
Note 3
Note 4
Note 5
Note 6
Note 7
Note 8
Note 9
Note 10
—
—
—
Note 11
PRNU = × 100 [%]
The maximum output of each odd and even pixels is set to VMAX, the minimum output to VMIN and the average
output to VAVE.
5. Use below the minimum value of the saturation output voltage.
6. Saturation exposure is defined as follows. SE =
7. RI is defined as indicated bellow. VOUT = 500mV (Typ.)
RI = × 100 [%]
Where average of odd pixels output is set to VODD-AVE, even pixels to VEVEN-AVE.
8. Optical signal accumulated time τ int stands at 10ms.
9. The difference between the maximum and average values of the dark output voltage is calculated for even
and odd respectively. The larger value is defined as the dark signal nonuniformity.
Optical signal accumulated time τ int stands at 10ms.
10. VOUT = 500mV (Typ.)
11. VOS is defined as indicated below.
VOUT
(VMAX – VMIN)/2
VAVE
VSAT
R1
| VODD-AVE – VEVEN-AVE |
VODD-AVE + VEVEN-AVE
()
2
VOS
GND
– 3 –
ILX532A
3797
D93
D83
D81
D79
D77
D75
S7499
S7497
S7495
S3
S1
D73
D71
D69
D94
D84
D82
D80
D78
D76
S7500
S7498
S7496
S4
S2
D74
D72
D70
1-line output period (7594 pixels)
3
2
1
5
0
5
0
5
0
5
φROG
ODD
φ1-
φ1-EVEN
φLH-ODD
φLH-EVEN
ODD
φ2-
φ2-EVEN
ODD
φRS-
Clock Timing Chart 1 (simultaneous output)
0
φRS-EVEN
5
ODD
φCLP-
– 4 –
0
φCLP-EVEN
D27
D25
D23
D5
D3
D1
OUT-ODD
V
D28
D26
D24
D6
D4
D2
Optical black (48 pixels)
Dummy signal (74 pixels)
Note) The transfer pulses (φ1, φ2, φLH) must have more than 3797 cycles.
VOUT-EVEN
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