Sony ILX531A Datasheet
5150-pixel CCD Linear Sensor (B/W)
Description
The ILX531A is a reduction type CCD linear sensor
developed for high resolution copiers. This sensor
reads A3-size documents at a density of 400 DPI,
and A4-size documents at a density of 600 DPI at
high speed.
Features
• Number of effective pixels: 5150 pixels
• Pixel size: 7µm × 7µm (7µm pitch)
• Clamp circuit are on-chip
• Signal output phase of two-output
simultaneous-output
(alternate-output is available)
• Ultra high sensitivity/Ultra low lag
• Maximum data rate: 40MHz
• Single 12V power supply
• Input clock pulse: CMOS 5V drive
• Package:
22 pin Plastic DIP (400mil)
Absolute Maximum Ratings
• Supply voltage VDD 15 V
• Operating temperature –10 to +60 °C
• Storage temperature –30 to +80 °C
Pin Configuration (Top View)
Block Diagram
– 1 –
E97X25B97-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ILX531A
22 pin DIP (Plastic)
5150
1
2
3
4
5
6
7
8
9
10
11
1
φCLP-
ODD
GND
V
OUT-ODD
VGG
GND
V
DD
φRS-ODD
φLH-ODD
φ2-ODD
φ1-ODD
φROG
12
13
14
15
16
17
18
19
20
21
22
V
DD
VOUT-EVEN
VDD
NC
GND
VDD
φCLP-EVEN
φRS-EVEN
φLH-EVEN
φ2-EVEN
φ1-EVEN
D25
D26
D74
S1
S2
S5149
S5150
D75
D94
φROG pulse
generator
Read out gate
CCD analog shift register
10
V
DD
φ1-ODD
9
φROG
11
φRS-ODD
2
φLH-
ODD
3
GND
4
φ2-
ODD
8
GND
14
V
DD
12
φ1-EVEN
13
φ2-
EVEN
15
V
DD
17
V
DD
19
φLH-
EVEN
20
φRS-
EVEN
21
Read out gate
CCD analog shift register
5
V
OUT-ODD
18
VOUT-EVEN
6
VGG
φCLP-ODD
1
Output
amplifier
φCLP-EVEN
22
Output
amplifier
– 2 –
ILX531A
Pin Description
Pin No. Symbol Description Pin No. Symbol Description
1
2
3
4
5
6
7
8
9
10
11
φCLP-ODD
φRS-ODD
φLH-ODD
GND
VOUT-ODD
VGG
GND
φ2-ODD
φ1-ODD
VDD
φROG
Clock pulse input (odd pixel)
Clock pulse input (odd pixel)
Clock pulse input (odd pixel)
GND
Signal out (odd pixel)
Output circuit gate bias
GND
Clock pulse input (odd pixel)
Clock pulse input (odd pixel)
12V power supply
Readout gate clock pulse input
12
13
14
15
16
17
18
19
20
21
22
VDD
φ1-EVEN
GND
φ2-EVEN
NC
VDD
VOUT-EVEN
VDD
φLH-EVEN
φRS-EVEN
φCLP-EVEN
12V power supply
Clock pulse input (even pixel)
GND
Clock pulse input (even pixel)
NC
12V power supply
Signal out (even pixel)
12V power supply
Clock pulse input (even pixel)
Clock pulse input (even pixel)
Clock pulse input (even pixel)
Recommended Supply Voltage
Item
VDD
Min.
11.4
Typ.
12
Max.
12.6
Unit
V
Clock Characteristics
Symbol
Cφ1, Cφ2
CφLH
CφRS
CφCLP
CφROG
Min.
—
—
—
—
—
Typ.
400
10
10
10
10
Max.
—
—
—
—
—
Unit
pF
pF
pF
pF
pF
Item
Input capacity of φ1∗1, φ2
∗1
Input capacity of φLH
∗1
Input capacity of φRS
∗1
Input capacity of φCLP
∗1
Input capacity of φROG
Input Clock Pulse Voltage Condition
High level
Low level
Min.
4.75
—
Typ.
5.0
0
Max.
5.25
0.1
Unit
V
V
Item
φ1, φ2, φLH, φRS, φCLP, φROG
pulse voltage
∗1
It indicates that φ1-ODD, φ1-EVEN as φ1, φ2-ODD, φ2-EVEN as φ2, φLH-ODD, φLH-EVEN as φLH, φRS-ODD,
φRS-EVEN as φRS, φCLP-ODD, φCLP-EVEN as φCLP.
Clock Frequency
Min.
—
—
Typ.
1
2
Max.
20
40
Unit
MHz
MHz
Item Symbol
φ1, φ2, φLH, φRS, φCLP
Data rate
fφ1, fφ2, fφLH, fφRS, fφCLP
fφR
– 3 –
ILX531A
Electrooptical Characteristics (Note 1)
(Ta = 25°C, VDD = 12V, fφR = 2MHz, Input clock = 5Vp-p,
Light source = 3200K, IR cut filter CM-500S (t = 1.0mm))
Item Symbol Min. Typ. Max. Unit Remarks
Sensitivity1
Sensitivity2
Sensitivity nonuniformity
Saturation output voltage
Saturation exposure
Register imbalance
Dark voltage average
Dark signal nonuniformity
Image lag
Supply current
Total transfer efficiency
Output impedance
Offset level
R1
R2
PRNU
VSAT
SE
RI
VDRK
DSNU
IL
IVDD
TTE
ZO
VOS
8.2
—
—
1.8
0.13
—
—
—
—
—
92
—
—
11
25.1
4
2.5
0.23
1
0.3
0.6
0.02
30
98
150
6.5
13.8
—
10
—
—
7
2.0
5.0
—
60
—
—
—
V/(lx · s)
V/(lx · s)
%
V
lx · s
%
mV
mV
%
mA
%
Ω
V
Note 2
Note 3
Note 4
Note 5
Note 6
Note 7
Note 8
Note 9
Note 10
—
—
—
Note 11
Notes
1) In accordance with the given electrooptical characteristics, the even black level is defined as the average
value of D6, D8, to D24. The odd black level is defined as the average value of D5, D7, to D23.
2) For the sensitivity test light is applied with a uniform intensity of illumination.
3) W lamp (2854K)
4) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
VOUT = 500mV (Typ.)
PRNU = × 100 [%]
Where the 5150 pixels are divided into blocks of even and odd pixels, respectively. The maximum output of
each block is set to VMAX, the minimum output to VMIN and the average output to VAVE.
5) Use below the minimum value of the saturation output voltage.
6) Saturation exposure is defined as follows. SE = VSAT/R1
7) RI is defined as indicated bellow. VOUT = 500mV (Typ.)
RI = × 100 [%]
Where average of odd pixels output is set to VODD-AVE, even pixels to VEVEN-AVE.
8) Optical signal accumulated time τ int stands at 10ms.
9) The difference between the maximum and average values of the dark output voltage is calculated for even
and odd respectively. The larger value is defined as the dark signal nonuniformity.
Optical signal accumulated time τ int stands at 10ms.
(VMAX – VMIN) /2
VAVE
| VODD-AVE – VEVEN-AVE |
VODD-AVE + VEVEN-AVE
(
2
)
– 4 –
ILX531A
10) VOUT = 500 mV (Typ.)
11) VOS is defined as indicated bellow.
A
VOS
VOUT
GND
A
– 5 –
ILX531A
5
0
5
0
5
0
5
0
5
0
1
2
3
2622
φROG
φ1-
ODD
φ1-EVEN
φLH-ODD
φLH-EVEN
φ2-ODD
φ2-EVEN
φRS-ODD
φRS-EVEN
φCLP-ODD
φCLP-EVEN
VOUT-EVEN
VOUT-ODD
D1
D3
D5
D23
D25
D27
D69
D71
D73
S1
S3
S5145
S5147
S5149
D75
D77
D79
D81
D83
D93
D2
D4
D6
D24
D26
D28
D70
D72
D74
S2
S4
S5146
S5148
S5150
D76
D78
D80
D82
D84
D94
Optical black (48 pixels)
Dummy signal (74 pixels)
1-line output period (5244 pixels)
Note) The transfer pulses (φ1, φ2, φLH) must have more than 2622 cycles.
Clock Timing Chart 1 (simultaneous output)
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