Sony ILX526A Datasheet
3000-pixel CCD Linear Image Sensor (B/W)
Description
The ILX526A is a rectangular reduction type CCD
linear image sensor designed for bar code POS
hand scanner and optical measuring equipment use.
A built-in timing generator and clock-drivers ensure
single 5V power supply for easy use.
Features
• Number of effective pixels: 3000 pixels
• Pixel size: 7µm × 200µm (7µm pitch)
• Single 5V power supply
• High sensitivity: 300V/(lx · s)
• Built-in timing generator and clock-drivers
• Built-in sample-and-hold circuit
• Electrical shutter function
• Clock frequency: 100kHz (Min), 1MHz (Max)
Absolute Maximum Ratings
• Supply voltage VDD 6V
•Operating temperature –10 to +60 °C
• Storage temperature –30 to +80 °C
Internal Structure
8
9
13
14
ILX526A
22 pin DIP (Cer-DIP)
Readout gate pulse
generator
Shutter pulse
generator
D65
D56
S3000
S2999
Clock pulse
generator
7
φSHUTφROGφCLKT1S/HSW
6
2
Pin Configuration (Top View)
DD VDD GND VDD GND
22
Clock-drivers
1
Vgg
φCLK
2
NC
3
NC
4
5
NC
6
φROG
φSHUT
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
GND
V
DD
T1
NC
7
8
9
10
11
1
3000
22
21
20
19
18
17
16
15
14
13
12
V
DD
GND
V
OUT
NC
NC
NC
NC
NC
V
DD
GND
S/HSW
21
1
Vgg GND V
S3
Readout gate
S2
S1
D55
CCD analog shift register
D54
D25
D24
Output Amplifier
S/H circuit
Clock-drivers
Readout gate
CCD analog shift register
20
OUT
V
10
12
– 1 –
E97803-PS
Pin Description
Pin No. Symbol Description
ILX526A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vgg
φCLK
NC
NC
NC
φROG
φSHUT
GND
VDD
T1
NC
S/HSW
GND
VDD
NC
NC
NC
Output circuit gate bias
Clock pulse input
NC
NC
NC
Readout gate pulse input
Electrical Shutter pulse input
GND
5V
TEST
NC
Switch (with S/H or without S/H)
GND
5V
NC
NC
NC
18
19
20
21
22
NC
NC
VOUT
GND
VDD
Mode Description
Mode in Use
With S/H
Without S/H
12 pin S/HSW
GND
VDD
Recommended Voltage
Item
VDD
Min.
4.5
Input Pin Capacity
Item
NC
NC
Signal output
GND
5V
Typ.
Max.
5.0
5.5
Symbol
Unit
V
Min.
Typ.
Max.
Unit
Input capacity of φCLK pin
Input capacity of φROG pin
Input capacity of φSHUT pin
CφCLK
CφROG
CφROG
—
—
—
– 2 –
10
10
10
—
—
—
pF
pF
pF
Electro-optical Characteristics (Note 1)
Ta = 25°C, VDD = 5V, Clock frequency: 500kHz, Light source = 3200K,
IR cut filter: CM-500S (t = 1.0mm), Without S/H mode
Item Symbol Min. Typ. Max. Unit Remarks
ILX526A
Sensitivity 1
Sensitivity 2
Sensitivity nonuniformity
Saturation output voltage
Dark voltage average
Dark signal nonuniformity
Image lag
Dynamic range
Saturation exposure
5V current consumption
Total transfer efficiency
Output impedance
Offset level
R1
R2
PRNU
VSAT
VDRK
DSNU
IL
DR
SE
IVDD
TTE
ZO
VOS
210
—
—
0.6
—
—
—
—
—
—
92.0
—
—
300
3700
5.0
0.8
2.5
5.0
5.0
320
0.003
7.0
97.0
250
2.5
390
—
10.0
—
6.0
12.0
—
—
—
17.0
—
—
—
V/(lx · s)
V/(lx · s)
%
V
mV
mV
%
—
lx · s
mA
%
Ω
V
Note 2
Note 3
Note 4
—
Note 5
Note 6
Note 7
Note 8
Note 9
—
—
—
Note 10
Note)
1. In accordance with the given electrooptical characteristics, the even black level is defined as the average
value of D24, D26 to D52. The odd black level is defined as the average value of D25 , D27 to D53.
2. For the sensitivity test light is applied with a uniform intensity of illumination.
3. Light source: LED λ = 660nm
4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
PRNU = × 100 [%]
(VMAX – VMIN)/2
VAVE
Where the 3000 pixels are divided into blocks of even and odd pixels, respectively, the maximum output of
each block is set to VMAX, the minimum output to VMIN and the average output to VAVE.
5. Integration time is 10ms.
6. The difference between the maximum and average values of the dark output voltage is calculated for even
and odd respectively. Integration time is 10ms.
7. Typical value is used for clock pulse and readout pulse. VOUT = 500mV.
8. DR =
VSAT
VDRK
When optical integration time is shorter, the dynamic range sets wider because dark voltage is in
proportion to optical integration time.
VSAT
9. SE =
R1
10. Vos is defined as indicated below.
VOUT
GND
D52 D53D51 D55 S1D54
VOS
– 3 –
D65
D64
D63
D62
D61
D60
D59
D58
D57
D56
S3000
S2999
S2998
S2997
(10 pixels)
Dummy signal
ILX526A
S4
S3
S2
S1
D55
D54
D53
D24
D23
D22
D21
D4
D3
2
1
0
–1
D2
D1
D0
Optical black
(3000 pixels)
elements signal
Effective picture
(30 pixels)
1-Line output period (3066 pixels)
Dummy signal (55 pixels)
0
5
φROG
Clock Timing Diagram (With S/H mode)
0
5
φSHUT
0
5
φCLK
OUT
V
3100 or more clock pulses are required.
– 4 –
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