Sony ICX418AKL User Manual

ICX418AKL

Diagonal 8mm (Type 1/2) CCD Image Sensor for NTSC Color Video Cameras

Description

The ICX418AKL is an interline CCD solid-state
image sensor suitable for NTSC color video cameras
with a diagonal 8mm (Type 1/2) system. Compared
with the current product ICX038DNA, basic
characteristics such as sensitivity, smear, dynamic
range and S/N are improved drastically.

This chip features a field period readout system and
an electronic shutter with variable charge-storage
time. This chip is compatible with the pins of the
ICX038DNA and has the same drive conditions.

Features

• High sensitivity (+6.0dB compared with the ICX038DNA)

• Low smear (–5.0dB compared with the ICX038DNA)

• High D range (+2.0dB compared with the ICX038DNA)

• High S/N

• High resolution and low dark current

• Excellent antiblooming characteristics

• Ye, Cy, Mg, and G complementary color mosaic filters on chip

• Continuous variable-speed shutter

• Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V)

• Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V)

• Horizontal register: 5V drive

20 pin DIP (Cer-DIP)

V

3

Pin 11

Optical black position

H

(T op View)

Pin 1

2

12

40

Device Structure

• Interline CCD image sensor

• Optical size: Diagonal 8mm (Type 1/2)

• Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels

• Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels

• Chip size: 7.40mm (H) × 5.95mm (V)

• Unit cell size: 8.4µm (H) × 9.8µm (V)

• Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels

Vertical (V) direction: Front 12 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 22

Vertical 1 (even fields only)

• Substrate material: Silicon

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E01503B41

ICX418AKL

USE RESTRICTION NOTICE (December 1, 2003 ver.)

This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD
products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify
this Notice which will be available to you in the latest specifications book for the Products. You should abide by
the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the
Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor. You
should consult a sales representative of the subsidiary or distributor of Sony on such a use restriction notice
when you consider using the Products.

Use Restrictions

• The Products are intended for incorporation into such general electronic equipment as office products,

communication products, measurement products, and home electronics products in accordance with the

terms and conditions set forth in this specifications book and otherwise notified by Sony from time to time.

• You should not use the Products for critical applications which may pose a life- or injury- threatening risk or

are highly likely to cause significant property damage in the event of failure of the Products. You should

consult your Sony sales representative beforehand when you consider using the Products for such critical

applications. In addition, you should not use the Products in weapon or military equipment.

• Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,

modification, use of the Products for the above-mentioned critical applications, weapon and military

equipment, or any deviation from the requirements set forth in this specifications book.

Design for Safety

• Sony is making continuous efforts to further improve the quality and reliability of the Products; however,

failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care to

ensure the safe design of your products such as component redundancy, anti-conflagration features, and

features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social

damage as a result of such failure.

Export Control

• If the Products are controlled items under the export control laws or regulations of various countries, approval

may be required for the export of the Products under the said laws or regulations. You should be responsible

for compliance with the said laws or regulations.

No License Implied

• The technical information shown in this specifications book is for your reference purposes only. The

availability of this specifications book shall not be construed as giving any indication that Sony and its

licensors will license any intellectual property rights in such information by any implication or otherwise. Sony

will not assume responsibility for any problems in connection with your use of such information or for any

infringement of third-party rights due to the same. It is therefore your sole legal and financial responsibility to

resolve any such problems and infringement.

Governing Law

• This Notice shall be governed by and construed in accordance with the laws of Japan, without reference to

principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating to this

Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the court of first

instance.

Other Applicable Terms and Conditions

• The terms and conditions in the Sony additional specifications, which will be made available to you when you

order the Products, shall also be applicable to your use of the Products as well as to this specifications book.

You should review those terms and conditions when you consider purchasing and/or using the Products.

– 2 –

Block Diagram and Pin Configuration

(T op Vie w)

ICX418AKL

VOUT

VDD

GND

VLVφ1

10 9 8 7 6 5 4 3 2 1

Cy

Mg

Cy

G

Cy

Vertical Register

Mg

11 12 13 14 15 16 17 18 19 20

NC

DSUB

V

NC

Ye

G

Ye

Mg

Ye

G

Horizontal Register

GND

GND

GND

Mg

Mg

RD

SUB

φ

Vφ2

Vφ3

Cy

Cy

G

Cy

RG

φ

Ye

Ye

Mg

Ye

G

G

NC

Note)

Hφ1Hφ2

Vφ4

Note) : Photo sensor

Pin Description

Pin No. Pin No.

10

Symbol Description

1

Vφ4

2

Vφ3

3

Vφ2

4

φSUB

5

GND

6

Vφ1

7

VL

8

GND

9

VDD
VOUT

Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate clock
GND
Vertical register transfer clock
Protective transistor bias
GND
Output circuit supply voltage
Signal output

11
12
13
14
15
16
17
18
19
20

Symbol Description
NC
VDSUB

Substrate bias circuit supply voltage
NC
GND
GND
RD

φRG

GND

GND

Reset drain bias

Reset gate clock
NC
Hφ1
Hφ2

Horizontal register transfer clock

Horizontal register transfer clock

– 3 –

Absolute Maximum Ratings

ICX418AKL

Item

Substrate clock φSUB – GND

VDD, VRD, VDSUB, VOUT – GND

Supply voltage

VDD, VRD, VDSUB, VOUT – φSUB
Vφ1, Vφ2, Vφ3, Vφ4 – GND

Clock input voltage

1, Vφ2, Vφ3, Vφ4 – φSUB

Vφ
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2 – Vφ4

φRG – GND
φRG – φSUB

VL – φSUB
Pins other than GND and φSUB – VL
Storage temperature
Operating temperature

∗1

+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Ratings Unit Remarks

–0.3 to +50

–0.3 to +18

–55 to +10
–15 to +20
to +10
to +15
to +17

–17 to +17

–10 to +15

–55 to +10
–65 to +0.3
–0.3 to +30

–30 to +80

–10 to +60

V
V
V
V
V
V
V
V
V
V
V

V
°C
°C

1

∗

– 4 –

Bias Conditions 1 [when used in substrate bias internal generation mode]

ICX418AKL

Item
Output circuit supply voltage
Reset drain voltage
Protective transistor bias
Substrate bias circuit supply voltage
Substrate clock

∗1

VL setting is the VVL voltage of the ver tical transfer clock waveform, or the same supply voltage as the VL

Symbol

VDD
VRD
VL
VDSUB

φSUB

Min.

14.55

14.55

14.55

15.0

15.0

1

∗

15.0

2

∗

15.45

15.45

15.45

Unit

V
V

V

RemarksTyp. Max.

VRD = VDD

power supply for the V dr iver should be used. (When CXD1267AN is used.)

∗2

Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.

Bias Conditions 2 [when used in substrate bias external adjustment mode]

Item
Output circuit supply voltage

Reset drain voltage
Protective transistor bias
Substrate bias circuit supply voltage
Substrate voltage adjustment range
Substrate voltage adjustment precision

Symbol

VDD
VRD
VL
VDSUB
VSUB
∆VSUB

Min.

14.55

14.55

6.0
–3

15.0

15.0

3

∗

4

∗

15.45

15.45

14.0
+3

Unit

V
V

V

%

RemarksTyp. Max.

VRD = VDD

5

∗

5

∗

∗3

VL setting is the VVL voltage of the ver tical transfer clock waveform, or the same supply voltage as the VL
power supply for the V dr iver should be used. (When CXD1267AN is used.)

∗4

Connect to GND or leave open.

∗5

The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a
special code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated
voltage. The adjustment precision is ±3%. However, this setting value has not significance when used in
substrate bias internal generation mode.

VSUB code — one character indication

Code and optimal setting correspond to each other as follows.

VSUB code
Optimal setting

6.0

f

E

6.5G7.0h7.5J8.0K8.5L9.0m9.5N10.0P10.5Q11.0

R

11.5

S

12.0

U

T

13.0V13.5W14.0

12.5

<Example> "L" → VSUB = 9.0V

DC Characteristics

Item

Output circuit supply current

Symbol

IDD

Min. Unit RemarksTyp. Max.

5.0

mA10.0

– 5 –

Clock V oltage Conditions

ICX418AKL

V
V
V

V

Vp-p

V
V
V
V
V
V
V

Vp-p

V
V

Vp-p

V

Vp-p

Waveform
diagram

1
2
2

2
2

2
2
2
2
2
2
2
3
3
4
4
4
5

Remarks

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)

High-level coupling
High-level coupling
Low-level coupling
Low-level coupling

Low-level coupling

Item

Readout clock voltage

Vertical transfer clock
voltage

Horizontal transfer
clock voltage

Reset gate clock
voltage

∗1

Substrate clock voltage

∗1

Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven

Symbol

VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,

VVL3, VVL4
VφV
| VVH1 – VVH2 |
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VRGL
VφRG
VRGLH – VRGLL
VφSUB

Min.

14.55
–0.05

–0.2
–9.6

8.3

–0.25
–0.25

4.75

–0.05

4.5

23.0

Typ.

15.0
0
0

–9.0

9.0

5.0
0

1

∗

5.0

24.0

Max. Unit

15.45

0.05

0.05
–8.5

9.65

0.1

0.1

0.1

0.5

0.5

0.5

0.5

5.25

0.05

5.5

0.8

25.0

with the following specifications.

Item

Reset gate clock
voltage

VRGL
VφRG

Symbol

Min.
–0.2

8.5

Typ.

0

9.0

– 6 –

Max. Unit

0.2

9.5

V

Vp-p

Waveform
diagram

4
4

Remarks

Clock Equivalent Circuit Constant

ICX418AKL

Item Min.

Capacitance between vertical transfer clock
and GND

Capacitance between vertical transfer clocks

Capacitance between horizontal transfer clock
and GND

Capacitance between horizontal transfer cloc ks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND

Vertical transfer clock series resistor

Vertical transfer clock ground resistor

Vφ

Vφ

1

Cφ

R

1

V12

2

R

2

Symbol
CφV1, CφV3
CφV2, CφV4
CφV12, CφV34
CφV23, CφV41
CφH1
CφH2
CφHH
CφRG
CφSUB
R1, R3
R2, R4
RGND

Typ.
2700
2700

820

330

100

91
47
11

680

91

100

68

Max.

Unit Remarks

pF
pF
pF
pF
pF
pF
pF
pF
pF

Ω
Ω
Ω

Vφ

Cφ

4

Hφ1 Hφ2

Cφ

V1

V41

Cφ

V4

R

4

R

Cφ

GND

V34

Cφ

Cφ

V2

Cφ

V23

V3

R

3

Vφ

3

CφH1

CφHH

CφH2

Horizontal transfer clock equivalent circuitVertical transfer clock equivalent circuit

– 7 –

Drive Clock Waveform Conditions

(1) Readout clock waveform

ICX418AKL

100%

90%

10%

0%

tr tf

twh

(2) Vertical transfer clock waveform

Vφ1 Vφ3

VVH1

VVHH

VVL1

VVH

VVHL

VVLH

VVHH

VVHL

VVL3

VVHL

φM

2

VVHH

φM

VVH3

V

VVHL

VT

VVHH

0V

VVH

VVLH

VVLL

VVL

Vφ2 Vφ4

VVH2

VVHH

VVHL

VVL

VVHH

VVLL

VVH

VVL2

VVHL

VVLH

VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)

– 8 –

VVL4

VVLL

VVH

VVLH

VVHL

VVL

VVHH

VVH4

VVLL

VVHH

VVHL

VVL

(3) Horizontal transfer clock waveform

tr twh tf

90%

10%

V

HL

Vφ

ICX418AKL

H

twl

(4) Reset gate clock waveform

RG waveform

VRGLH

RGLL

V

VRGLm

Hφ1 waveform

+2.5V

twl

Point A

twhtr tf

Vφ

RG

VRGH

VRGL + 0.5V
VRGL

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the period twh, then:

VφRG = VRGH – VRGL

Negative overshoot level during the falling edge of RG is VRGLm.

(5) Substrate clock waveform

SUB

V

100%

90%

10%

0%

VφSUB

tr tftwh

– 9 –

φM

φM

2

Clock Switching Characteristics

ICX418AKL

Item

Readout clock
Vertical transfer

clock

During
imaging

During
parallel-serial

Horizontal

transfer clock

conversion

Reset gate clock

Substrate clock

∗1

When vertical transfer clock driver CXD1267AN is used.

∗2

tf ≥ tr – 2ns.

Symbol

VT
Vφ1, Vφ2,

Vφ

3, Vφ4

Hφ

Hφ1
Hφ2

φRG

φSUB

Min.

2.3

11

1.5

twh

Typ.

2.5

20

5.38

13

1.8

Max.

twl tr tf

Min. Typ.

20

5.38

51

two

Symbol

Horizontal transfer clock

Min.

Hφ1, Hφ2

Typ. Max.

16 20

Max.

Min. Typ.

0.5

15

0.01

0.01
3

UnitnsRemarksItem

Max.

19

0.5

3

∗

Min. Typ.

0.5
15

15

0.01

0.01
3

Max.

250

19

0.5

Unit

µs

During readout

∗1

ns

∗2

ns

µs

ns

When draining

µs

charge

Remarks

∗3

The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.

– 10 –

ICX418AKL

Image Sensor Characteristics

Item

Sensitivity
Saturation signal
Smear

Video signal shading

Uniformity between
video signal channels

Dark signal
Dark signal shading
Flicker Y
Flicker R-Y
Flicker B-Y
Line crawl R
Line crawl G
Line crawl B
Line crawl W
Lag

Symbol
S

Ysat
Sm

SHy

∆Sr
∆Sb

Ydt
∆Ydt
Fy
Fcr
Fcb
Lcr
Lcg
Lcb
Lcw
Lag

Min.

1040
1000

Typ.

1300

–115

Max.

–105

20
25
10
10

2
1
2
5
5
3
3
3
3

0.5

Measurement

Unit

method
mV
mV

dB

%
%
%

%
mV
mV

%

%

%

%

%

%

%

%

1
2
3
4
4
5
5
6
7
8
8
8
9
9
9
9

10

(Ta = 25°C)

Remarks

Ta = 60°C

Zone 0 and I
Zone 0 to II'

Ta = 60°C
Ta = 60°C

Zone Definition of Video Signal Shading

14

H
8

768 (H)

V

10

V

10

14

H
8

Zone 0, I

Zone II, II'

Ignored region

Effective pixel region

12

10

Measurement System

[∗A]

CCD signal output

(3dB down 6.3MHz)

CCD C.D.S

AMP

494 (V)

LPF1

S/H

S/H

[∗Y]

Y signal output

LPF2

(3dB down 1MHz)

[∗C]

Chroma signal output

Note) Adjust the amplifier gain so that the gain between [∗A] and [∗Y], and between [∗A] and [∗C] equals 1.

– 11 –

ICX418AKL

Image Sensor Characteristics Measurement Method

Measurement conditions

1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the
value indicated on the device.)

2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output
or chroma signal output of the measurement system.

Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals

Cy Ye Cy Ye

A1

GMgGMg

B

Cy Ye Cy Ye

A2

Mg G Mg G

As shown in the left figure, fields are read out. The charge is
mixed by pairs such as A1 and A2 in the A field. (pairs such
as B in the B field)
As a result, the sequence of charges output as signals from
the horizontal shift register (Hreg) is, for line A1, (G + Cy),
(Mg + Ye), (G + Cy), and (Mg + Ye).

Hreg

Color Coding Diagram

These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:

Y = {(G + Cy) + (Mg + Ye)} × 1/2

= 1/2 {2B + 3G + 2R}

is used for the Y signal, and the approximation:

R – Y = {(Mg + Ye) – (G + Cy)}

= {2R – G}

is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are

(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).

The Y signal is formed from these signals as follows:

Y = {(G + Ye) + (Mg + Cy)} × 1/2

= 1/2 {2B + 3G + 2R}
This is balanced since it is formed in the same way as for line A1.
In a like manner, the chroma (color difference) signal is approximated as follows:

– (B – Y) = {(G + Ye) – (Mg + Cy)}

= – {2B – G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and – (B – Y)
in alternation. This is also true for the B field.

– 12 –

ICX418AKL

Definition of standard imaging conditions

1) Standard imaging condition I:

Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and
image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard
sensitivity testing luminous intensity.

2) Standard imaging condition II:

Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.

1. Sensitivity

Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following
formula.

S = Ys × [mV]

250

60

2. Saturation signal

Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of the Y signal output, 200mV, measure the minimum value of the Y signal.

3. Smear

Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure
the maximum value YSm [mV] of the Y signal output and substitute the value into the following formula.

Sm = 20 × log

YSm

200

1

×

500

1

×

[dB] (1/10V method conversion value)

10

4. Video signal shading

Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and
minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.

SHy = (Ymax – Ymin)/200 × 100 [%]

5. Uniformity between video signal channels

Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Cr min, Cbmin
[mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into the
following f ormula.

∆Sr = | (Crmax – Crmin)/200 | × 100 [%]
∆Sb = | (Cbmax – Cbmin)/200 | × 100 [%]

6. Dar k signal

Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.

– 13 –

ICX418AKL

7. Dar k signal shading

After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the dark
signal output and substitute the values into the following formula.

∆Ydt = Ydmax – Ydmin [mV]

8. Flicker

1) Fy
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the difference in the signal level between fields (∆Yf [mV]). Then
substitute the value into the following formula.

Fy = (∆Yf/200) × 100 [%]

2) Fcr, Fcb
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, inser t an R or B filter, and then measure both the difference in the signal level between
fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output (CAr, CAb).
Substitute the values into the following formula.

Fci = (∆Ci/CAi) × 100 [%] (i = r, b)

9. Line crawls

Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then inser t a white subject and R, G, and B filters and measure the difference
between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the
following f ormula.

Lci = (∆Yli/200) × 100 [%] (i = w, r, g, b)

10. Lag

Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following
formula.

Lag = (Ylag/200) × 100 [%]

FLD

V1

Strobe light

timing

Light

Output

Y signal output 200mV Ylag (lag)

– 14 –

Drive Circuit 1 (substrate bias internal generation mode)

15V

– 15 –

XSUB

XV2
XV1

XSG1

XV3

XSG2

XV4

Hφ

10

22/20V

1
2
3
4
5

CXD1267AN

6
7
8
9

20
19
18
17
16
15
14
13
12
11

22/16V

1/35V

100k

1 2 3 4 5 6

2

Vφ4Vφ3Vφ

SUB

φ

GND

7 8 9 10

L

1

V

Vφ

GND

DD

V

OUT

V

1

–9V

3.3/16V

1M

0.01

3.3/20V

ICX418

(BOTTOM VIEW)

2

20 19 18 17 16 15

1

RG

Hφ1Hφ

NC

RD

GND

φ

14 13 12 11

GND

NC

DSUB

V

NC

Hφ

RG

0.01

2

100

0.01

3.9k

[∗A]
CCD OUT

ICX418AKL

Drive Circuit 2 (substrate bias external adjustment mode)

– 16 –

15V

XSUB

XV2
XV1

XSG1

XV3

XSG2

XV4

10

22/20V

1
2
3
4
5

CXD1267AN

6
7
8
9

20
19
18
17
16
15
14
13
12
11

22/16V

1/35V

1/35V

1/35V

100k

1 2 3 4 5 6

Vφ4Vφ3Vφ

2

Hφ1Hφ

20 19 18 17 16 15

0.1

56k

27k

2

SUB

φ

0.1

GND

ICX418

(BOTTOM VIEW)

RG

NC

RD

φ

270k

7 8 9 10

L

1

V

Vφ

GND

GND

GND

NC

14 13 12 11

39k

DD

V

DSUB

V

OUT

V

NC

15k
47k

15k

0.1

3.3/20V

–9V

3.3/16V

1M

0.01

Hφ

Hφ

RG

1

0.01

2

100

ICX418AKL

[∗A]

0.01

3.9k

CCD OUT

Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics)

1.0
Cy

0.8
G

0.6

Ye

ICX418AKL

0.4

Relative Response

0.2

0

400 450 500

Sensor Readout Clock Timing Chart

V1

V2

Odd Field

V3

V4

Mg

550

Wave Length [nm]

2.5

33.5

1.6

600 650 700

2.5 2.5 2.5

Even Field

0.2

V1

V2

V3

V4

Unit: µs

– 17 –

Drive Timing Chart (Vertical Sync)

FLD

VD

BLK

HD

3

2

1

520

525

– 18 –

V1

V2

5

4

10

15

20

260

265

270

275

280

V3

V4

CCD
OUT

493
494

246

135

246

135

494
493

21436

5

5

21436

ICX418AKL

Drive Timing Chart (Horizontal Sync)

HD

BLK

H1

– 19 –

H2

760

RG

V1
V2

768

5

3

2

1

10

20

3

2

1

3

5

3

2

30

40

1

10

2

1

22

20

10

20

V3
V4

SUB

ICX418AKL

ICX418AKL

Notes on Handling

1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.

Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.

2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W

soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering

tool, use a thermal controller of the zero cross On/Off type and connect it to ground.

3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should

dirt stick to a glass surface, blow it off with an air blower. (For dir t stuck through static electricity ionized

air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d)Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for

electrostatic protection. Do not reuse the tape.

4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more

than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)

Upper ceramic

39N

29N

29N

0.9Nm

Lower ceramic

Compressive strength

Low melting
point glass

Shearing strength

Tensile strength

Torsional strength

b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the

package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation,
use either an elastic load, such as a spring plate, or an adhesive.

– 20 –

ICX418AKL

c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated

voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.

d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not to

perform the following actions as this may cause cracks.

• Applying repeated bending stress to the outer leads.

• Heating the outer leads for an extended period with a soldering iron.

• Rapidly cooling or heating the package.

• Applying any load or impact to a limited portion of the low melting point glass using tweezers or other

sharp tools.

• Prying at the upper or lower ceramic using the low melting point glass as a fulcrum.
Note that the same cautions also apply when removing soldered products from boards.

e)Acr ylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-

acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)

5) Others
a)Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high

luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.

b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or

usage in such conditions.

– 21 –

Package Outline Unit: mm

20pin DIP (600mil)

B

– 22 –

PACKAGE STRUCTURE

PACKAGE MATERIAL
LEAD TREA TMENT

Sony Corporation

LEAD MATERIAL
PACKAGE MASS

DRAWING NUMBER

0.7

~

~

3

11.55

7.55

3

0.55

0.4

0.51

0.4

Cer-DIP
TIN PLATING

42 ALLOY

2.6g
AS-B14-01(E)

20

9.0

V

H

1

18.0 ± 0.4

14.6

1.778

0.3

A

11

1.27

15.24

1. “A” is the center of the effective image area.

3.26 ± 0.3

2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.

3. The bottom “C” of the package is the height reference.

4. The center of the effective image area, relative to “B” and “B'” is
(H, V) = (9.0, 7.55) ± 0.15mm.

5. The rotation angle of the effective image area relative to H and V is ± 1˚.

6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm.

4.0 ± 0.3

7. The tilt of the effective image area relative to the bottom “C” is less than 60µm.

8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.

9. The notch and the hole on the bottom must not be used for reference of fixing.

15.1 ± 0.3

10

B'

3

0.70

~

0.46

0.8

M

0˚ to 9˚

C

1.4

0.25

(1.0)

11

(0.7R) φ1.4

10

(1.7)

20

(4.0)

1

ICX418AKL