Sony ICX224AQ Datasheet

Diagonal 8mm (T ype 1/2) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX224AQ is a diagonal 8mm (Type 1/2) interline CCD solid-state image sensor with a square pixel array and 2.02M effective pixels. Frame readout allows all pixels' signals to be output independently within approximately 1/7.5 second. Also, the adoption of high frame rate readout mode supports 30 frames per second which is four times the speed in frame readout mode. This chip features an electronic shutter with variable charge-storage time. Adoption of a design specially suited for frame readout ensures a saturation signal level equivalent to when using field readout. High resolution and high color reproductivity are achieved through the use of R, G, B primary color mosaic filters. Further, high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology.
This chip is suitable for applications such as electronic still cameras, PC input cameras, etc.
Features
Supports frame readout
High horizontal and vertical resolution
Supports high frame rate readout mode: 30 frames/s
Square pixel
Horizontal drive frequency: 18MHz
No voltage adjustments (reset gate and substrate bias are not adjusted.)
R, G, B primary color mosaic filters on chip
High color reproductivity, high sensitivity, low smear
Continuous variable-speed shutter
Low dark current, excellent anti-blooming characteristics
20-pin high-precision plastic package (top/bottom dual surface reference possible) Device Structure
Interline CCD image sensor
Image size: Diagonal 8mm (Type 1/2)
Total number of pixels: 1688 (H) × 1248 (V) approx. 2.11M pixels
Number of effective pixels: 1636 (H) × 1236 (V) approx. 2.02M pixels
Number of active pixels: 1620 (H) × 1220 (V) approx. 1.98M pixels
Chip size: 7.6mm (H) × 6.2mm (V)
Unit cell size: 3.9µm (H) × 3.9µm (V)
Optical black: Horizontal (H) direction: Front 4 pixels, rear 48 pixels
Vertical (V) direction: Front 10 pixels, rear 2 pixels
Number of dummy bits: Horizontal 28
Vertical 1 (even fields only)
Substrate material: Silicon
– 1 –
E98927B99
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ICX224AQ
20 pin DIP (Plastic)
Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor
A
A
A
Pin 1
V
4
48
2
10
Pin 11
H
Optical black position
(Top View)
AAA AAA AAA
– 2 –
ICX224AQ
Pin Description
Note) : Photo sensor
V
OUT
GND
NC
GND
Vφ
1B
Vφ
1A
Vφ
2
Vφ
3B
Vφ
3A
Vφ
4
V
DD
φRG
Hφ
2
Hφ
1
GND
φSUB
C
SUB
V
L
Hφ
1
Hφ
2
B G
B G
B G
Horizontal register
Vertical register
Note)
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
1
17
18
19
20
B G
B G
B G
G R
G R
G R
G R
G R
G R
Block Diagram and Pin Configuration
(Top View)
1
DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF.
Pin No. Symbol Description Pin No. Symbol Description
1 2 3 4 5 6 7 8 9
10
Vφ4 Vφ3A Vφ3B Vφ2 Vφ1A Vφ1B GND NC GND VOUT
Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND
GND Signal output
11 12 13 14 15 16 17 18 19 20
VDD φRG Hφ2 Hφ1 GND φSUB CSUB VL Hφ1 Hφ2
Supply voltage Reset gate clock Horizontal register transfer clock Horizontal register transfer clock GND Substrate clock Substrate bias
1
Protective transistor bias Horizontal register transfer clock Horizontal register transfer clock
– 3 –
ICX224AQ
Absolute Maximum Ratings
–40 to +12
–50 to +15 –50 to +0.3 –40 to +0.3
–25 to
–0.3 to +22
–10 to +18 –10 to +6.5 –0.3 to +28 –0.3 to +15
to +15
–6.5 to +6.5
–10 to +16
–30 to +80
–10 to +60
–10 to +75
V V V V V V V V V V V V
V °C °C °C
VDD, VOUT, φRG – φSUB Vφ1A, Vφ1B, Vφ3A, Vφ3B φSUB Vφ2, Vφ4, VL φSUB Hφ1, Hφ2, GND – φSUB CSUB φSUB VDD, VOUT, φRG, CSUB – GND Vφ1A, Vφ1B, Vφ2, Vφ3A, Vφ3B, Vφ4 – GND Hφ1, Hφ2 – GND Vφ1A, Vφ1B, Vφ3A, Vφ3B – VL Vφ2, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Hφ1 – Hφ2 Hφ1, Hφ2 – Vφ4
Item
Ratings
Unit
Remarks
2
+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. +16V (Max.) is guaranteed for turning on or off power supply.
2
Against φSUB
Against GND
Against VL
Between input clock pins
Storage temperature Guaranteed temperature of performance Operating temperature
– 4 –
ICX224AQ
Clock Voltage Conditions
Item
Readout clock voltage
VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2,
VVL3, VVL4 VφV VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL VφH VHL VCR VφRG VRGLH – VRGLL VRGL – VRGLm VφSUB
14.55 –0.05
–0.2 –8.0
6.8 –0.25 –0.25
4.75
–0.05
0.5
3.0
21.5
15.0 0 0
–7.5
7.5
5.0 0
1.65
3.3
22.5
15.45
0.05
0.05 –7.0
8.05
0.1
0.1
1.4
1.3
1.4
0.8
5.25
0.05
5.25
0.4
0.5
23.5
V V V
V V
V V V V V V V V V V V V V
1 2 2
2 2
2 2 2 2 2 2 3 3 3 4 4 4 5
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)
High-level coupling High-level coupling Low-level coupling Low-level coupling
Cross-point voltage
Low-level coupling Low-level coupling
Horizontal transfer clock voltage
Reset gate clock voltage
Substrate clock voltage
Vertical transfer clock voltage
Symbol Min. Typ.
Max.
Unit
Remarks
Bias Conditions
Item Supply voltage Protective transistor bias Substrate clock Reset gate clock
VDD VL
φSUB φRG
14.55
15.0
122
15.45
V
Symbol Min. Typ. Max. Unit Remarks
DC Characteristics
Item
Supply current
IDD
4.0
7.0
10.0
mA
Symbol Min. Typ. Max. Unit Remarks
1
VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power supply for the V driver should be used.
2
Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD.
Waveform diagram
– 5 –
ICX224AQ
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer clock and GND
CφV1A, CφV3A CφV1B, CφV3B CφV2, CφV4 CφV1A2, CφV3A4 CφV1B2, CφV3B4 CφV23A, CφV41A CφV23B, CφV41B CφV1A3A CφV1B3B C
φ
V1A3B, C
φ
V1B3A
CφV24 C
φ
V1A1B, C
φ
V3A3B
CφH1 CφH2
CφHH
CφRG
CφSUB R1A, R3A
R1B, R3B R2, R4 RGND RφH
390 1800 1800
220
470
120
330
120
120
270
330
180
120
120
30
8
820
75 100 120
30
5
pF pF pF pF pF pF pF pF pF pF pF pF pF pF
pF
pF
pF
Ω Ω Ω Ω Ω
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor Horizontal transfer clock series resistor
Symbol Min. Typ. Max. Unit Remarks
RGND
CφV1B3B
R1B
CφV41B
Vφ1B
CφV4
CφV41A
CφV1B
CφV1B3A
CφV1A1B
CφV1A
CφV1B2
R1A
Vφ1A
CφV1A2
Vφ2
R2
CφV24
CφV1A3A
CφV23A
CφV23B
R3A
Vφ3A
CφV2 CφV3A
CφV3A3B
CφV1A3B
CφV3B
R3B
Vφ3B
CφV3A4
CφV3B4
Vφ4
R4
Vertical transfer clock equivalent circuit
Hφ1
RφH
CφH1 CφH2
RφH
CφHH
Hφ2
RφH
Hφ1 Hφ2
RφH
Horizontal transfer clock equivalent circuit
– 6 –
ICX224AQ
Drive Clock Waveform Conditions (1) Readout clock waveform
(2) Vertical transfer clock waveform
II
100%
90%
10%
0%
tr twh tf
φM
0V
φM
2
Vφ1A, Vφ1B Vφ3A, Vφ3B
Vφ2 Vφ4
VVHH
VVH
VVHL
VVHH
VVHL
VVH1
VVL1
VVLH
VVLL
VVL
VVHH
VVH3
VVHL
VVH
VVHH
VVHL
VVL3
VVL
VVLL
VVLH
VVHH VVHH
VVH
VVHL
VVHL
VVH2
VVLH
VVL2
VVLL
VVL
VVHH VVHH
VVHL
VVH4
VVHL
VVH
VVL
VVLH
VVLL
VVL4
VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)
II
VVT
– 7 –
ICX224AQ
twh
tf
tr
90%
10%
V
HL
twl
Hφ1
two
Hφ2
VRGL
VRGLL
VRGLH
twl
V
RGH
RG waveform
VRGLm
tr twh tf
V
CR
(3) Horizontal transfer clock waveform
(4) Reset gate clock waveform
VφH
VφH
2
Point A
VφRG
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
VSUB
90%
100%
10%
0%
tr twh tf
φM
φM
2
(A bias generated within the CCD)
VφSUB
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
– 8 –
ICX224AQ
Clock Switching Characteristics (Horizontal drive frequency: 18MHz)
Item
Readout clock
Vertical transfer clock
Reset gate clock
Substrate clock
VT Vφ1A, Vφ1B,
Vφ2, Vφ3A, Vφ3B, Vφ4
Hφ1 Hφ2 Hφ1 Hφ2
φRG
φSUB
1.36
14 14
7
1.7
1.56
19.5
19.5
5.56
10
3.6
14 14
19.5
19.5
5.56 37
0.5
8.5
8.5
0.01
0.01 4
14 14
0.5
15
0.5
8.5
8.5
0.01
0.01 5
250
14 14
0.5
µs
ns
ns
µs
ns
µs
During readout
When using CXD1267AN
tf tr – 2ns
During drain charge
Symbol
twh
Min. Typ.
Max.
Horizontal transfer clock
Hφ1, Hφ2 12 19.5 ns
Item
Symbol
two
Unit
Remarks
Min. Typ.
Max.
Min. Typ.
Max.
Min. Typ.
Max.
Min. Typ.
Max.
twl tr tf
Unit Remarks
Horizontal
transfer clock
During imaging
During parallel-serial conversion
1.0
0.8
0.6
0.4
0.2
0
400 450 500 550 600 650 700
Wave Length [nm]
Relative Response
B
R
G
Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)
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