Sony ICX206AKB Datasheet

Description

The ICX206AKB is an interline CCD solid-state image sensor suitable for NTSC color video cameras. Compared with the current product ICX086AKB, sensitivity and saturation signal are improved drastically through the adoption of Super HAD CCD technology. Ye, Cy, Mg, and G complementary color mosaic filters are used.

This chip features a field period readout system and an electronic shutter with variable charge-storage time.

Also, this outline is miniaturized by using original package.

Features

• Maximum package dimensions: φ8mm

• High sensitivity (+4dB compared with ICX086AKB)

• High saturation signal

(+2.2dB compared with ICX086AKB)

• Horizontal register: 3.3 to 5.0V drive

• Reset gate: 3.3 to 5.0V drive

• No voltage adjustment

(Reset gate and substrate bias are not adjusted.)

• Low smear and low dark current

• Excellent antiblooming characteristics

• Continuous variable-speed shutter

• Recommended range of exit pupil distance: –20 to –100mm

• Ye, Cy, Mg, and G complementary color mosaic filters on chip

Device Structure

• Interline CCD image sensor

• Image size: Diagonal 4.5mm (Type 1/4)

• Number of effective pixels: 510 (H) × 492 (V) approx. 250K pixels

• Total number of pixels: 537 (H) × 505 (V) approx. 270K pixels

• Chip size: 4.47mm (H) × 3.80mm (V)

• Unit cell size: 7.15µm (H) × 5.55µm (V)

• Optical black: Horizontal (H) direction: Front 2 pixels, rear 25 pixels

Vertical (V) direction: Front 12 pixels, rear 1 pixel

• Number of dummy bits: Horizontal 16

Vertical 1 (even fields only)

• Substrate material: Silicon

– 1 –

ICX206AKB

E97Z29B99

Diagonal 4.5mm (Type 1/4) CCD Image Sensor for NTSC Color Video Cameras

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Optical black position

(Top View)

13 pin PCA (Ceramic)

A

Pin 1

V

2

25

1

12

Pin 8

H

∗

Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing

newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.

AAA AAA AAA

– 2 –

ICX206AKB

Block Diagram and Pin Configuration (Top View)

Absolute Maximum Ratings

∗1

+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Against φSUB

Against GND

Against VL

Between input clock pins

Storage temperature Operating temperature

–40 to +8

–50 to +15 –50 to +0.3 –40 to +0.3 –0.3 to +18

–10 to +18

–10 to +6 –0.3 to +28 –0.3 to +15

to +15

–5 to +5 –13 to +13 –30 to +80 –10 to +60

V V V V V V V V V V V

V °C °C

VDD, VOUT, RG – φSUB Vφ1, Vφ3 – φSUB Vφ2, Vφ4, VL – φSUB Hφ1, Hφ2, GND – φSUB VDD, VOUT, RG – GND Vφ1, Vφ2, Vφ3, Vφ4 – GND Hφ1, Hφ2 – GND Vφ1, Vφ3 – VL Vφ2, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Hφ1 – Hφ2 Hφ1, Hφ2 – Vφ4

Item Ratings Unit Remarks

∗1

Pin No.

1 2 3 4 5 6 7

Vφ4 Vφ3 Vφ2 Vφ1 NC GND VOUT

Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock

GND Signal output

8

9 10 11 12 13

VDD φSUB VL RG Hφ1 Hφ2

Supply voltage Substrate clock Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock

Symbol Description Pin No. Symbol Description

Pin Description

5

6

7

Note)

Note) : Photo sensor

V

OUT

GND

Vφ

1

Vφ

2

Vφ

3

Vφ

4

V

DD

φSUB

V

L

RG

Hφ

1

Hφ

2

Horizontal Register

2

3

4

NC

Cy

G

Cy

Mg

Ye

Mg

Ye

G

Cy

G

Cy

Mg

Ye

Mg

Ye

G

8

1

Vertical Register

9

10

11

13

12

2

3

4

5

6

7

8

9

10

11

12

13

1

Hφ1

RG

V

L

φSUB

V

DD

GND

NC

Hφ

2

Vφ4

Vφ1

Vφ2

Vφ3

VOUT

– 3 –

ICX206AKB

Clock Voltage Conditions

Item

Readout clock voltage

VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2,

VVL3, VVL4 VφV VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL VφH VHL

VφRG VRGLH – VRGLL

VRGL – VRGLm VφSUB

14.55 –0.05

–0.2 –8.0

6.3 –0.25 –0.25

3.0 –0.05

3.0

21.0

15.0 0 0

–7.0

7.0

3.3 0

3.3

22.0

15.45

0.05

0.05 –6.5

8.05

0.1

0.3

5.25

0.05

5.5

0.4

0.5

23.5

V V V

V V

V V V V V V V V

V V

1 2 2

2 2

2 2 2 2 2 2 3 3

4 4

4 5

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)

High-level coupling High-level coupling Low-level coupling Low-level coupling

Input through 0.1µF capacitance

Low-level coupling Low-level coupling

Horizontal transfer clock voltage

Reset gate clock voltage

Substrate clock voltage

Vertical transfer clock voltage

Symbol Min.

Typ. Max.

Unit

Waveform

diagram

Remarks

Bias Conditions

Item Supply voltage Protective transistor bias Substrate clock Reset gate clock

VDD VL

φSUB φRG

14.55 15.0

∗1 ∗2 ∗2

15.45 V

Symbol Min. Typ. Max. Unit Remarks

DC Characteristics

Item Supply current IDD 3 5 mA

Symbol Min. Typ. Max. Unit Remarks

∗1

VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used.

∗2

Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD.

– 4 –

ICX206AKB

Item

Capacitance between vertical transfer clock and GND

CφV1, CφV3 CφV2, CφV4 CφV12, CφV34 CφV23, CφV41 CφV13 CφV24

CφH1, CφH2

CφHH

CφRG

CφSUB R1, R2, R3, R4

RGND RφH RφRG

390 220 330 270

82 75

33

5

100 100

15 15 39

pF pF pF pF pF pF

pF

Ω Ω Ω Ω

Capacitance between vertical transfer clocks

Capacitance between horizontal transfer clock and GND

Capacitance between horizontal transfer clocks

Capacitance between reset gate clock and GND

Capacitance between substrate clock and GND

Vertical transfer clock series resistor Vertical transfer clock ground resistor Horizontal transfer clock series resistor Reset gate clock series resistor

Symbol Min. Typ. Max. Unit Remarks

RφH

Hφ2

Hφ1

CφH1 CφH2

CφHH

Vφ1

CφV12

Vφ2

Vφ4

Vφ3

CφV34

CφV23CφV41

CφV13

CφV24

CφV1 CφV2

CφV4 CφV3

RGND

R4

R1

R3

R2

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

RφRG

RGφ

Cφ

RG

Reset gate clock equivalent circuit

Clock Equivalent Circuit Constant

– 5 –

ICX206AKB

Drive Clock Waveform Conditions (1) Readout clock waveform

(2) Vertical transfer clock waveform

II II

100%

90%

10%

0%

VVT

tr twh tf

φM

0V

φM

2

Vφ1 Vφ3

Vφ2 Vφ4

VVHH

VVH

VVHL

VVHH

VVHL

VVH1

VVL1

VVLH

VVLL

VVL

VVHH

VVH3

VVHL

VVH

VVHH

VVHL

VVL3

VVL

VVLL

VVLH

VVHH VVHH

VVH

VVHL

VVH2

VVLH

VVL2

VVLL

VVL

VVHH VVHH

VVHL

VVH4

VVHL

VVH

VVL

VVLH

VVLL

VVL4

VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)

– 6 –

ICX206AKB

tr twh tf

90%

10%

twl

Vφ

H

VHL

Point A

twl

Vφ

RG

VRGH

VRGL

VRGLH

RG waveform

VRGLL

Hφ1 waveform

twhtr tf

10%

VRGLm

90%

100%

10%

0%

(A bias generated within the CCD)

V

SUB

tr twh tf

φM

2

VφSUB

(3) Horizontal transfer clock waveform

(4) Reset gate clock waveform

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the interval twh, then:

VφRG = VRGH – VRGL

Negative overshoot level during the falling edge of RG is VRGLm.

(5) Substrate clock waveform