Sony ICX099AL Datasheet

Description

The ICX099AL is a 1/2-inch optical interline CCD
solid-state image sensor with a square pixel array
and 800K effective pixels. Progressive scan allows all
pixels' signals to be output independently within
approximately 1/15 second. Also, the adoption of
high-speed mode supports 30 frames per second.
This chip features an electronic shutter with variable
charge-storage time which makes it possible to
realize high resolution, full-frame still image without a
mechanical shutter. Further, high sensitivity and low
dark current are achieved through the adoption of
HAD (Hole-Accumulation Diode) sensors.

This chip is suitable for applications such as high
resolution cameras for FA, etc.

Features

• Progressive scan allows individual readout of the

image signals from all pixels.

• High horizontal and vertical resolution still image

without a mechanical shutter.

• Supports 30 frames per second mode

• Square pixel

• Horizontal drive frequency: 14.31818MHz

• No voltage adjustments (reset gate and substrate

bias are not adjusted.)

• High resolution, high sensitivity, low dark current

• Continuous variable-speed shutter

• Low smear

• Excellent antiblooming characteristics

Device Structure

• Interline CCD image sensor

• Optical size: 1/2-inch format

• Number of effective pixels: 1034 (H) × 779 (V) approx. 800K pixels

• Total number of pixels: 1077 (H) × 788 (V) approx. 850K pixels

• Chip size: 7.60mm (H) × 6.20mm (V)

• Unit cell size: 6.25µm (H) × 6.25µm (V)

• Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels

Vertical (V) direction: Front 7 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 29

Vertical 1

• Substrate material: Silicon

– 1 –

ICX099AL

E97747-PS

1/2-inch Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

A

A

A

Pin 1

V

3

40

2

7

Pin 11

H

Optical black position

(Top View)

20 pin DIP (Cer-DIP)

For the availability of this product, please contact the sales office.

AAA
AAA
AAA

VDD, VOUT, φRG – φSUB
Vφ2A, Vφ2B – φSUB
Vφ1, Vφ3, VL – φSUB
Hφ1, Hφ2, GND – φSUB
CSUB – φSUB
VDD, VOUT, φRG, CSUB – GND
Vφ1, Vφ2A, Vφ2B, Vφ3 – GND
Hφ1, Hφ2 – GND
Vφ2A, Vφ2B – VL
Vφ1, Vφ3, Hφ1, Hφ2, GND – VL
Voltage difference between vertical clock input pins
Hφ1 – Hφ2
Hφ1, Hφ2 – Vφ3

– 2 –

ICX099AL

Pin No. Symbol Description Pin No. Symbol Description

1
2
3
4
5
6
7
8
9

10

Vφ1
Vφ2A
NC
Vφ2B
NC
Vφ3
GND
GND
NC
VOUT

Vertical register transfer clock
Vertical register transfer clock

Vertical register transfer clock

Vertical register transfer clock
GND
GND

Signal output

11
12
13
14
15
16
17
18
19
20

VDD
GND
φSUB
CSUB
NC
NC
VL
φRG
Hφ1
Hφ2

Supply voltage
GND
Substrate clock
Substrate bias

∗1

Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock

Pin Description

Block Diagram and Pin Configuration

(Top View)

∗1

DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance

of 0.1µF.

Against φSUB

Against GND

Against VL

Between input
clock pins

Storage temperature
Operating temperature

Absolute Maximum Ratings

–40 to +10

–50 to +15
–50 to +0.3
–40 to +0.3

–25 to

–0.3 to +18

–10 to +18

–10 to +5
–0.3 to +28
–0.3 to +15

to +15

–5 to +5
–13 to +13
–30 to +80
–10 to +60

V
V
V
V
V
V
V
V
V
V
V
V

V
°C
°C

Item Ratings Unit

Remarks

∗2

+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

∗2

Note)

Note)

: Photo sensor

1

2

3

4

5

6

7

8

9

10

V

OUT

NC

GND

GND

Vφ

3

NC

Vφ

2B

NC

Vφ

2A

Vφ

1

Horizontal register

11

12

13

14 15

16

17

18

19

V

DD

GND

φSUB

C

SUB

NC

NC

V

L

φRG

Hφ

1

Hφ

2

20

Vertical register

– 3 –

ICX099AL

Clock Voltage Conditions

Item

Readout clock voltage

VVT
VVH02A
VVH1, VVH2A,

VVH2B, VVH3
VVL1, VVL2A,

VVL2B, VVL3
Vφ1, Vφ2A,

Vφ2B, Vφ3
| VVL1– VVL3 |
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VφRG
V

RGLH –

V

RGLL

VRGL– V

RGLm

VφSUB

14.55
–0.05

–0.2

–5.8

5.2

4.75

–0.05

3.0

19.75

15.0
0

0

–5.5

5.5

5.0
0

3.3

20.5

15.45

0.05

0.05

–5.2

5.8

0.1

0.3

1.0

0.5

0.5

5.25

0.05

5.5

0.4

0.5

21.25

V
V

V

V

V
V

V
V
V
V
V
V
V
V
V
V

1
2

2

2

2
2

2
2
2
2
3
3
4
4
4
5

VVH = VVH02A

VVL = (VVL1+VVL3)/2

High-level coupling
High-level coupling
Low-level coupling
Low-level coupling

Low-level coupling
Low-level coupling

Horizontal transfer
clock voltage

Reset gate clock
voltage

Substrate clock voltage

Vertical transfer clock
voltage

Symbol Min. Typ. Max. Unit

Waveform
diagram

Remarks

Bias Conditions

Item
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock

VDD
VL

φSUB
φRG

14.55

15.0

∗1
∗2
∗2

15.45 V

Symbol Min. Typ. Max. Unit Remarks

DC Characteristics

Item

Supply current

IDD 6.0 mA

Symbol Min. Typ. Max. Unit

Remarks

∗1

VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.

∗2

Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.

– 4 –

ICX099AL

Clock Equivalent Circuit Constant

Item

Capacitance between vertical transfer
clock and GND

CφV1
CφV2A, CφV2B
CφV3
CφV12A, CφV2B1
CφV2A3, CφV32B
CφV13

CφH1, CφH2

CφHH

CφRG

CφSUB
R1, R2A, R2B, R3

RGND
RφH
RH2

2200
1800
6800
1200
1000
1500

56

120

10

400

30
30
20
20

pF
pF
pF
pF
pF
pF

pF

pF

pF

pF

Ω
Ω
Ω

kΩ

Capacitance between vertical transfer
clocks

Capacitance between horizontal
transfer clock and GND

Capacitance between horizontal transfer
clocks

Capacitance between reset gate clock
and GND

Capacitance between substrate clock and
GND

Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Horizontal transfer clock ground resistor

Symbol Min. Typ. Max. Unit Remarks

RφH RφH

Hφ2

Hφ1

CφH1

CφH2

CφHH

Vφ1

CφV12A

Vφ2A

Vφ2B

Vφ3

CφV32B

CφV2A3CφV2B1

CφV13

CφV1 CφV2A

CφV2B CφV3

RGND

R2B

R1

R3

R2A

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

RH2

– 5 –

ICX099AL

Drive Clock Waveform Conditions

(1) Readout clock waveform

(2) Vertical transfer clock waveform

II II

100%

90%

10%

0%

VVT

tr twh tf

φM

0V

φM

2

Vφ1

Vφ3

Vφ2A, Vφ2B

VVH1

VVHH VVH

VVHL

VVLH

VVL1

VVL01

VVL

VVLL

VVH3

VVHH VVH

VVHL

VVLH

VVL03

VVL

VVLL

VφV1 = VVH1 – VVL01
VφV2A = VVH02A – VVL2A
VφV2B = VVH02B – VVL2B
VφV3 = VVH3 – VVL03

VVH = VVH02A
VVL = (VVL01 + VVL03) /2
VVL3 = VVL03

VVLH

VVL2A, VVL2B

VVLL

VVL

VVH

VVHH

VVH02A, VVH02B

VVH2A, VVH2B

VVHL

VT

Note) Readout clock is used by composing vertical transfer clocks Vφ2A and Vφ2B.

– 6 –

ICX099AL

twh tftr

90%

10%

V

HL

twl

Hφ1

two

Hφ2

VRGL

VRGLL

VRGLH

twl

V

RGH

RG waveform

VRGLm

tr twh tf

V

CR

Point A

(3) Horizontal transfer clock waveform

Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.

(4) Reset gate clock waveform

VφH

VφRG

VφH

2

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the interval twh, then:

VφRG = VRGH – VRGL

Negative overshoot level during the falling edge of RG is VRGLm.

(5) Substrate clock waveform

90%

100%

10%

0%

V

SUB

tr twh tf

φM

φM

2

VφSUB

(A bias generated within the CCD)

– 7 –

ICX099AL

Readout clock
Vertical transfer

clock

During
imaging

During
parallel-serial

conversion

Reset gate clock

Substrate clock

VT
Vφ1,Vφ2A,

Vφ2B, Vφ3
Hφ1
Hφ2
Hφ1
Hφ2

φRG

φSUB

2.3

19
21

11

1.5

2.5

24
26

13

1.8

211926

24

51

0.5

10
10

0.01

0.01
3

15
15

0.5

15

0.5

10
10

0.01

0.01
3

350

15
15

0.5

µs

ns

ns

µs

ns

µs

During
readout

∗1

∗2

During
drain
charge

Horizontal

transfer clock

Item Symbol

twh twl tr tf

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Unit Remarks

Horizontal transfer clock Hφ1, Hφ2

16 20

ns

Item

Symbol

two

Min. Typ.

Max.

Unit

Remarks

∗1

When vertical transfer clock driver CXD1267AN × 2 are used.

∗2

tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be
at least VφH/2 [V].

Clock Switching Characteristics

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

400 500 600 700 800 900 1000

Wave Length [nm]

Relative Response

Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)