Sony ICX098AL Datasheet

Diagonal 4.5mm (Type 1/4) Progressive Scan CCD Image Sensor with Square Pixel for B/W Cameras
Description
The ICX098AL is a diagonal 4.5mm (Type 1/4) interline CCD solid-state image sensor with a square pixel array which supports VGA format. Progressive scan allows all pixels signals to be output independently within approximately 1/30 second. Also, the adoption of monitoring mode supports 60 frame/s. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still image without a mechanical shutter. Further, high sensitivity and low dark current are achieved through the adoption of HAD (Hole­Accumulation Diode) sensors.
This chip is suitable for applications such as second­dimensional bar-code reader, PC input cameras, etc.
Features
Progressive scan allows individual readout of the
image signals from all pixels.
High horizontal and vertical resolution (both approx.
480TV-lines) still image without a mechanical shutter.
Supports monitoring mode
Square pixel
Supports VGA format
Horizontal drive frequency: 12.27MHz
No voltage adjustments (reset gate and substrate
bias are not adjusted.)
High resolution, high sensitivity, low dark current
Continuous variable-speed shutter
Low smear
Excellent antiblooming characteristics
Horizontal register: 3.3V drive
14-pin high precision plastic package (enables dual-surface standard)
Device Structure
Interline CCD image sensor
Image size: Diagonal 4.5mm (Type 1/4)
Number of effective pixels: 659 (H) × 494 (V) approx. 330K pixels
Total number of pixels: 692 (H) × 504 (V) approx. 350K pixels
Chip size: 4.60mm (H) × 3.97mm (V)
Unit cell size: 5.6µm (H) × 5.6µm (V)
Optical black: Horizontal (H) direction: Front 2 pixels, rear 31 pixels
Vertical (V) direction: Front 8 pixels, rear 2 pixels
Number of dummy bits: Horizontal 16
Vertical 5
Substrate material: Silicon
– 1 –
E98302A99
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ICX098AL
14 pin DIP (Plastic)
A
A
A
Pin 1
V
2
31
2
8
Pin 8
H
Optical black position
(Top View)
AAA AAA AAA
– 2 –
ICX098AL
VDD, VOUT, φRG – φSUB Vφ2A, Vφ2B φSUB Vφ1, Vφ3, VL φSUB Hφ1, Hφ2, GND – φSUB CSUB φSUB VDD, VOUT, φRG, CSUB – GND Vφ1, Vφ2A, Vφ2B, Vφ3 – GND Hφ1, Hφ2 – GND Vφ2A, Vφ2B – VL Vφ1, Vφ3, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Hφ1 – Hφ2 Hφ1, Hφ2 – Vφ3
Pin No. Symbol Description Pin No. Symbol Description
1 2 3 4 5 6 7
Vφ1 Vφ3 Vφ2A Vφ2B VL GND VOUT
Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Protective transistor bias GND Signal output
8
9 10 11 12 13 14
VDD GND φSUB CSUB φRG Hφ1 Hφ2
Supply voltage GND Substrate clock Substrate bias
1
Reset gate clock Horizontal register transfer clock Horizontal register transfer clock
Pin Description
Vertical register
Horizontal register
V
OUT
GND
V
L
Vφ
2B
Vφ
2A
Vφ
3
Vφ
1
V
DD
GND
φSUB
C
SUB
φRG
Hφ
1
Hφ
2
Note)
Note)
: Photo sensor
9
10
11
12
13
14
8
1
2
3
4
5
6
7
Block Diagram and Pin Configuration
(Top View)
1
DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
Against φSUB
Against GND
Against VL
Between input clock pins
Storage temperature Operating temperature
Absolute Maximum Ratings
–40 to +10
–50 to +15 –50 to +0.3 –40 to +0.3
–25 to
–0.3 to +18
–10 to +18
–10 to +5 –0.3 to +28 –0.3 to +15
to +15
–5 to +5 –13 to +13 –30 to +80 –10 to +60
V V V V V V V V V V V V
V °C °C
Item Ratings Unit
Remarks
2
+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
2
– 3 –
ICX098AL
Clock Voltage Conditions
Item
Readout clock voltage
VVT VVH02A VVH1, VVH2A,
VVH2B, VVH3 VVL1, VVL2A,
VVL2B, VVL3 Vφ1, Vφ2A,
Vφ2B, Vφ3 | VVL1– VVL3 | VVHH VVHL VVLH VVLL VφH VHL VφRG V
RGLH
V
RGLL
VRGL– V
RGLm
VφSUB
14.55 –0.05
–0.2
–5.8
5.2
3.0
–0.05
3.0
19.75
15.0 0
0
–5.5
5.5
3.3 0
3.3
20.5
15.45
0.05
0.05
–5.2
5.8
0.1
0.3
1.0
0.5
0.5
5.25
0.05
5.5
0.4
0.5
21.25
V V
V
V
V V
V V V V V V V V V V
1 2
2
2
2 2
2 2 2 2 3 3 4 4 4 5
VVH = VVH02A
VVL = (VVL1 + VVL3)/2
High-level coupling High-level coupling Low-level coupling Low-level coupling
Low-level coupling Low-level coupling
Horizontal transfer clock voltage
Reset gate clock voltage
Substrate clock voltage
Vertical transfer clock voltage
Symbol Min. Typ. Max. Unit
Waveform diagram
Remarks
Bias Conditions
Item Supply voltage Protective transistor bias Substrate clock Reset gate clock
VDD VL
φSUB φRG
14.55
15.0
122
15.45 V
Symbol Min. Typ. Max. Unit Remarks
DC Characteristics
Item
Supply current
IDD 6.0 mA
Symbol Min. Typ. Max. Unit
Remarks
1
VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used.
2
Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD.
– 4 –
ICX098AL
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer clock and GND
CφV1 CφV2A, CφV2B CφV3 CφV12A, CφV2B1 CφV2A3, CφV32B CφV13
CφH1, CφH2
CφHH
CφRG
CφSUB R1
R2A, R2B R3 RGND RφH RH2 RφRG
1200
470
2200
470 390
10 22
68
3
220
20 43 36 43 12 30 62
pF pF pF pF pF pF
pF
pF
pF
pF
Ω Ω Ω Ω Ω
k
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor Horizontal transfer clock series resistor Horizontal transfer clock ground resistor Reset gate clock series resistor
Symbol Min. Typ. Max. Unit Remarks
RφH RφH
Hφ2Hφ1
CφH1 CφH2
CφHH
Vφ1
CφV12A
Vφ2A
Vφ2B Vφ3
CφV32B
CφV2A3CφV2B1
CφV13
CφV1 CφV2A
CφV2B CφV3
RGND
R2B
R1
R3
R2A
Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit
RH2
RφRG
RGφ
Cφ
RG
Reset gate clock equivalent circuit
– 5 –
ICX098AL
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
II II
100%
90%
10%
0%
VVT
tr twh tf
φM
0V
φM
2
Vφ1
Vφ3
Vφ2A, Vφ2B
VVH1
VVHH VVH
VVHL
VVLH
VVL1
VVL01
VVL
VVLL
VVH3
VVHH VVH
VVHL
VVLH
VVL03
VVL
VVLL
VφV1 = VVH1 – VVL01 VφV2A = VVH02A – VVL2A VφV2B = VVH02B – VVL2B VφV3 = VVH3 – VVL03
VVH = VVH02A VVL = (VVL01 + VVL03) /2 VVL3 = VVL03
VVLH
VVL2A, VVL2B
VVLL
VVL
VVH
VVHH
VVH02A, VVH02B
VVH2A, VVH2B
VVHL
VT
Note) Readout clock is used by composing vertical transfer clocks Vφ2A and Vφ2B.
– 6 –
ICX098AL
twh tftr
90%
10%
V
HL
twl
Hφ1
two
Hφ2
VRGL
VRGLL
VRGLH
twl
V
RGH
RG waveform
VRGLm
tr twh tf
V
CR
Point A
(3) Horizontal transfer clock waveform
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
VφH
VφRG
VφH
2
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
90%
100%
10%
0%
V
SUB
tr twh tf
φM
φM
2
VφSUB
(A bias generated within the CCD)
– 7 –
ICX098AL
Readout clock Vertical transfer
clock
During imaging
During parallel-serial
conversion
Reset gate clock
Substrate clock
VT Vφ1,Vφ2A,
Vφ2B, Vφ3 Hφ1 Hφ2 Hφ1 Hφ2
φRG
φSUB
2.3
25.5 28
11
1.5
2.5
30.5 33
12
1.8
28
25.53330.5
63.5
0.5
9 9
0.01
0.01 3
16.5 14
0.5
15
0.5
9 9
0.01
0.01 3
350
16.5 14
0.5
µs
ns
ns
µs
ns
µs
During readout
1
2
During drain charge
Horizontal
transfer clock
Item Symbol
twh twl tr tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit Remarks
Horizontal transfer clock Hφ1, Hφ2
21.5 25.5
ns
Item
Symbol
two
Min. Typ.
Max.
Unit
Remarks
1
When vertical transfer clock driver CXD1267AN is used.
2
tf tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be
at least VφH/2 [V].
Clock Switching Characteristics
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
400 500 600 700 800 900 1000
Wave Length [nm]
Relative Response
Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)
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