Sony ICX097AKE Datasheet

Description

The ICX097AKE is an interline CCD solid-state
image sensor suitable for PAL small color cameras.
Ye, Cy, Mg, and G complementary color mosaic
filters are used. At the same time, high sensitivity
and low dark current are achieved through the
adoption of Super HAD CCD technology.

This chip features a field period readout system
and an electronic shutter with variable charge­storage time.

The package is a small 12-pin SON(LCC).

Features

• High sensitivity and low dark current

• Horizontal register: 3.3 to 5.0V drive

• No voltage adjustment

(Reset gate and substrate bias are not adjusted.)

• Low smear

• Excellent antiblooming characteristics

• Continuous variable-speed shutter

• Recommended range of exit pupil distance: –10mm to –∞

• Ye, Cy, Mg, and G complementary color mosaic filters on chip

• 12-pin ceramic SON(LCC) package

Device Structure

• Interline CCD image sensor

• Image size: Diagonal 3mm (Type 1/6)

• Number of effective pixels: 500 (H) × 582 (V) approx. 290K pixels

• Total number of pixels: 537 (H) × 597 (V) approx. 320K pixels

• Chip size: 3.30mm (H) × 2.95mm (V)

• Unit cell size: 4.90µm (H) × 3.15µm (V)

• Optical black: Horizontal (H) direction: Front 7 pixels, rear 30 pixels

Vertical (V) direction: Front 14 pixels, rear 1 pixel

• Number of dummy bits: Horizontal 16

Vertical 1 (even fields only)

• Substrate material: Silicon

∗

Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly
developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.

– 1 –

ICX097AKE

E97728A99

Diagonal 3mm (Type 1/6) CCD Image Sensor for PAL Color Cameras

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

12 pin SON (Ceramic)

A

A

A

Pin 1

V

7

30

1

14

Pin 7

H

Optical black position

(Top View)

AAA
AAA
AAA

– 2 –

ICX097AKE

Block Diagram and Pin Configuration

(Top View)

Note)

Note) : Photo sensor

V

OUT

GND

Vφ

1

Vφ

2

Vφ

3

Vφ

4

V

DD

φSUB

V

L

RG

Hφ

1

Hφ

2

Horizontal register

Cy

Cy

G

Cy

Mg

Ye

Ye

Mg

Ye

G

Cy

Cy

G

Cy

Mg

Ye

Ye

Mg

Ye

G

1

5

2

3

4

6

9

11

12

8

10

7

Vertical register

Mg

G

Mg

G

Pin No.

1
2
3
4
5
6

Vφ4
Vφ3
Vφ2
Vφ1
GND
VOUT

Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output

7
8

9
10
11
12

VDD
φSUB
VL
RG
Hφ1
Hφ2

Supply voltage
Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock

Symbol Description Pin No. Description

Pin Description

Absolute Maximum Ratings

∗1

+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Symbol

Against φSUB

Against GND

Against VL

Between input clock
pins

Storage temperature
Operating temperature

–40 to +8
–40 to +10
–50 to +15

–50 to +0.3
–40 to +0.3
–0.3 to +18

–10 to +18
–10 to +15

–0.3 to +26
–0.3 to +16

to +15
–14 to +14
–14 to +14

–30 to +80
–10 to +60

V
V
V
V
V
V
V
V
V
V
V
V
V

°C
°C

VDD – φSUB
VOUT, RG – φSUB
Vφ1, Vφ3 – φSUB
Vφ2, Vφ4, VL– φSUB
Hφ1, Hφ2, GND – φSUB
VDD, VOUT, RG – GND
Vφ1, Vφ2, Vφ3, Vφ4 – GND
Hφ1, Hφ2 – GND
Vφ1, Vφ3 – VL
Vφ2, Vφ4, Hφ1, Hφ2, GND – VL
Voltage difference between vertical clock input pins
Hφ1 – Hφ2
Hφ1, Hφ2 – Vφ4

Item Ratings Unit Remarks

∗1

– 3 –

ICX097AKE

Clock Voltage Conditions

Item

Readout clock voltage

VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,

VVL3, VVL4
VφV
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL

VφRG
VRGLH – VRGLL
VRGH
VφSUB

14.55
–0.05

–0.2
–8.0

6.8
–0.25
–0.25

3.0
–0.05

4.5

VDD +

0.3

21.5

15.0
0
0

–7.5

7.5

5.0
0

5.0

VDD +

0.6

22.5

15.45

0.05

0.05
–7.0

8.05

0.1

0.1

0.3

0.3

0.3

0.3

5.25

0.05

5.5

0.8

VDD +

0.9

23.5

V
V
V

V
V

V
V
V
V
V
V
V
V

V
V
V
V

1
2
2

2
2

2
2
2
2
2
2
3
3

4
4
4
5

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2
VφV

= VVHn – VVLn (n = 1 to 4)

High-level coupling
High-level coupling
Low-level coupling
Low-level coupling

Input through 0.01µF
capacitance

Low-level coupling

Horizontal transfer
clock voltage

Reset gate clock
voltage

Substrate clock voltage

Vertical transfer clock
voltage

Symbol Min.

Typ. Max.

Unit

Waveform

diagram

Remarks

Bias Conditions

Item
Supply voltage
Protective transistor bias
Substrate clock

VDD
VL
φSUB

14.55

15.0

∗1
∗2

15.45 V

Symbol Min. Typ. Max. Unit Remarks

DC Characteristics

Item
Supply current IDD 4 6 mA

Symbol Min. Typ. Max. Unit Remarks

∗1

VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.

∗2

Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.

– 4 –

ICX097AKE

Clock Equivalent Circuit Constant

Item

Capacitance between vertical transfer
clock and GND

CφV1, CφV3
CφV2, CφV4
CφV12, CφV34
CφV23, CφV41
CφV13, CφV24

CφH1, CφH2

CφHH

CφRG

CφSUB
R1, R2, R3, R4

RGND
RφH
RφRG

270
220
180
150

62
20

30

3

150

82
15
20
39

pF
pF
pF
pF
pF

pF

pF

pF

pF

Ω
Ω
Ω
Ω

Capacitance between vertical transfer
clocks

Capacitance between horizontal
transfer clock and GND

Capacitance between horizontal
transfer clocks

Capacitance between reset gate clock
and GND

Capacitance between substrate clock
and GND

Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor

Symbol Min. Typ. Max. Unit Remarks

RφH

RφH

Hφ2

Hφ1

CφH1 CφH2

CφHH

Vφ1

CφV12

Vφ2

Vφ4 Vφ3

CφV34

CφV23CφV41

CφV13

CφV24

CφV1

CφV2

CφV4 CφV3

RGND

R4

R1

R3

R2

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

RφRG

RGφ

Cφ

RG

Reset gate clock equivalent circuit

– 5 –

ICX097AKE

Drive Clock Waveform Conditions
(1) Readout clock waveform

(2) Vertical transfer clock waveform

II II

100%

90%

10%

0%

VVT

tr twh tf

φM

0V

φM

2

Vφ1 Vφ3

Vφ2 Vφ4

VVHH

VVH

VVHL

VVHH

VVHL

VVH1

VVL1

VVLH

VVLL

VVL

VVHH

VVH3

VVHL

VVH

VVHH

VVHL

VVL3

VVL

VVLL

VVLH

VVHH VVHH

VVH

VVHL

VVHL

VVH2

VVLH

VVL2

VVLL

VVL

VVHH VVHH

VVHL

VVH4

VVHL

VVH

VVL

VVLH

VVLL

VVL4

VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)

– 6 –

ICX097AKE

tr twh tf

90%

10%

twl

Vφ

H

VHL

(3) Horizontal transfer clock waveform

twl

Vφ

RG

VRGH

VRGL + 0.5V
V

RGL

VRGLH

VRGLL

twhtr tf

10%

Point A

RG waveform

Hφ

1 waveform

(4) Reset gate clock waveform

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the interval twh, then:

VφRG = VRGH – VRGL

(5) Substrate clock waveform

90%

100%

10%

0%

V

SUB

tr twh tf

φM

φM

2

VφSUB

(A bias generated within the CCD)