Sony ICX089AK Datasheet

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ICX089AK

E97710A99

Diagonal 4.5mm (Type 1/4) CCD Image Sensor for PAL Color Video Cameras

Description

The ICX089AK is an interline CCD solid-state image sensor suitable for PAL color digital video cameras. This chip supports DV standard SD mode, and can drive at 13.5MHz.

High sensitivity, wide dynamic range and low dark current are achieved through the adoption of Super HAD CCD technology. In addition, high resolution is achieved through the adoption of Ye, Cy, Mg and G complementary color mosaic filters.

This chip features a field period readout system and an electronic shutter with variable charge-storage time.

The package is a 14-pin DIP (Plastic), and both top and bottom surface reference can be assured at the same time.

Features

• Supports DV standard SD mode (13.5MHz)

• High resolution, high sensitivity and wide dynamic range

• Low dark current and low smear

• Excellent antiblooming characteristics

• Supply voltage: 12V

• Horizontal register drive amplitude: 2.7 to 3.6V

• No voltage adjustment (Reset gate and substrate bias are not adjusted.)

• Continuous variable-speed shutter

• Recommended range of exit pupil distance: –20 to –100mm

• Ye, Cy, Mg and G complementary color mosaic filters on chip

• 14-pin high precision plastic package (both top and bottom surface reference possible)

Device Structure

• Interline CCD image sensor

• Image size: Diagonal 4.5mm (Type 1/4)

• Total number of pixels: 766 (H) × 596 (V) approx. 460K pixels

• Total number of effective pixels: 724 (H) × 582 (V) approx. 420K pixels

• Chip size: 4.60mm (H) × 3.97mm (V)

• Unit cell size: 5.15µm (H) × 4.70µm (V)

• Optical black: Horizontal (H) direction: Front 2 pixels, rear 40 pixels

Vertical (V) direction: Front 12 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 20

Vertical 1 (even fields only)

• Substrate material: Silicon

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

14 pin DIP (Plastic)

Pin 1

Pin 8

Optical black position

(Top View)

∗

Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.

AAA AAA AAA

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ICX089AK

Against φSUB

Against GND

Against VL

Between input clock pins

Storage temperature Operating temperature

Block Diagram and Pin Configuration

(Top View)

Note) : Photo sensor

OUT

GND

Vφ

GND

φSUB

SUB

φRG

Hφ

Horizontal Register

Vertical Register

Mg Ye G

Mg Ye

G Cy Mg

Note)

Pin No.

1 2 3 4 5 6 7

Vφ4 Vφ3 Vφ2 Vφ1 VL GND VOUT

Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Protective transistor bias GND Signal output

9 10 11 12 13 14

VDD GND φSUB CSUB φRG Hφ1 Hφ2

Supply voltage GND Substrate clock Substrate bias

∗1

Reset gate clock Horizontal register transfer clock Horizontal register transfer clock

Symbol Description

Pin Description

Absolute Maximum Ratings

–40 to +8

–50 to +15 –50 to +0.3 –40 to +0.3

–25 to

–0.3 to +18

–10 to +18

–10 to +5 –0.3 to +28 –0.3 to +15

to +15

–5 to +5 –13 to +13 –30 to +80 –10 to +60

V V V V V V V V V V V V

V °C °C

VDD, VOUT, φRG – φSUB Vφ1, Vφ3 – φSUB Vφ2, Vφ4, VL – φSUB Hφ1, Hφ2, GND – φSUB CSUB – φSUB VDD, VOUT, φRG, CSUB – GND Vφ1, Vφ2, Vφ3, Vφ4 – GND Hφ1, Hφ2 – GND Vφ1, Vφ3 – VL Vφ2, Vφ4, Hφ1, Hφ2, GND – VL Voltage difference between vertical clock input pins Hφ1 – Hφ2 Hφ1, Hφ2 – Vφ4

Item Ratings Unit Remarks

∗2

+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

∗1

DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of 0.1µF.

∗2

Pin No. Symbol Description

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ICX089AK

Clock Voltage Conditions

Item

Readout clock voltage

VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2,

VVL3, VVL4 VφV VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL VφH VHL VφRG VRGLH – VRGLL VRGL – VRGLm VφSUB

11.64 –0.05

–0.2

–6.85

5.95 –0.25 –0.25

2.7

–0.05

2.7

17.3

12.0 0 0

–6.5

6.5

3.3 0

3.3

18.5

12.36

0.05

–6.15

6.9

0.1

0.3

3.6

0.05

3.6

0.4

0.5

19.3

V V V

V V

V V V V V V V V V V V V

1 2 2

2 2

2 2 2 2 2 2 3 3 4 4 4 5

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)

High-level coupling High-level coupling Low-level coupling Low-level coupling

Low-level coupling Low-level coupling

Horizontal transfer clock voltage

Reset gate clock voltage

Substrate clock voltage

Vertical transfer clock voltage

Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

Bias Conditions

Item Supply voltage Protective transistor bias Substrate clock Reset gate clock

VDD VL

φSUB φRG

11.64

12.0

∗1 ∗2 ∗2

12.36

Symbol Min. Typ. Max. Unit Remarks

DC Characteristics

Item Supply current IDD 5.0 mA

Symbol Min. Typ. Max. Unit Remarks

∗1

VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used.

∗2

Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated within the CCD.

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ICX089AK

Clock Equivalent Circuit Constant

Item

Capacitance between vertical transfer clock and GND

CφV1, CφV3 CφV2, CφV4 CφV12, CφV34 CφV23, CφV41 CφV13 CφV24 CφH1, CφH2 CφHH CφRG CφSUB R1, R2, R3, R4 RGND RφH RH2

680 470 330 270

82 75 47 47

180

82 15 12 30

pF pF pF pF pF pF pF pF pF pF

Ω Ω Ω

kΩ

Capacitance between vertical transfer clocks

Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor Horizontal transfer clock series resistor Horizontal transfer clock ground resistor

Symbol Min. Typ. Max. Unit Remarks

RφH RφH

Hφ2Hφ1

CφH1 CφH2

CφHH

Vφ1

CφV12

Vφ2

Vφ4 Vφ3

CφV34

CφV23CφV41

CφV13

CφV24

CφV1 CφV2

CφV4 CφV3

RGND

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

RH2

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ICX089AK

Drive Clock Waveform Conditions (1) Readout clock waveform

(2) Vertical transfer clock waveform

II II

100%

90%

10%

VVT

tr twh tf

φM

Vφ1 Vφ3

Vφ2 Vφ4

VVHH

VVH

VVHL

VVHH

VVHL

VVH1

VVL1

VVLH

VVLL

VVL

VVHH

VVH3

VVHL

VVH

VVHH

VVHL

VVL3

VVL

VVLL

VVLH

VVHH VVHH

VVH

VVHL

VVH2

VVLH

VVL2

VVLL

VVL

VVHH VVHH

VVHL

VVH4

VVHL

VVH

VVL

VVLH

VVLL

VVL4

VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4)

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ICX089AK

twh tftr

90%

10%

twl

Hφ1

two

Hφ2

VRGL

VRGLL

VRGLH

twl

RGH

RG waveform

VRGLm

tr twh tf

Point A

(3) Horizontal transfer clock waveform

Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR. The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.

(4) Reset gate clock waveform

VφH

VφRG

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL.

VRGL = (VRGLH + VRGLL) /2

Assuming VRGH is the minimum value during the interval twh, then:

VφRG = VRGH – VRGL.

Negative overshoot level during the falling edge of RG is VRGLm.

(5) Substrate clock waveform

90%

100%

10%

SUB

tr twh tf

φM

(A bias generated within the CCD)

VφSUB

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