Sony ICX085AK Datasheet

– 1 –

ICX085AK

E96414D99

Diagonal 11mm (Type 2/3) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras

Description

The ICX085AK is a diagonal 11mm (Type 2/3)
interline CCD solid-state image sensor with a square
pixel array. Progressive scan allows all pixels
signals to be output independently within
approximately 1/12 second. This chip features an
electronic shutter with variable charge-storage time
which makes it possible to realize full-frame still
image without a mechanical shutter. High resolution
and high color reproductivity are achieved through
the use of R, G, B primary color mosaic filters.
Further, high sensitivity and low dark current are
achieved through the adoption of HAD (Hole­Accumulation Diode) sensors.

This chip is suitable for image input applications
such as still cameras which require high resolution.

Features

• Progressive scan allows individual readout of the

image signals from all pixels.

• High vertical resolution (1024TV-lines) still image

without a mechanical shutter.

• Square pixel unit cell

• Aspect ratio 5:4

• Horizontal drive frequency: 20.25MHz

• Reset gate bias is not adjusted.

• Substrate voltage: 5.5 to 12.5V

• R, G, B primary color mosaic filters on chip

• Continuous variable-speed shutter

• High resolution, high color reproductivity, high sensitivity, low dark current

• Low smear

• Excellent antiblooming characteristics

• Horizontal register: 5V drive

Device Structure

• Interline CCD image sensor

• Image size: Diagonal 11mm (Type 2/3)

• Number of effective pixels: 1300 (H) × 1030 (V) approx. 1.3M pixels

• Total number of pixels: 1360 (H) × 1034 (V) approx. 1.4M pixels

• Chip size: 10.0mm (H) × 8.7mm (V)

• Unit cell size: 6.7µm (H) × 6.7µm (V)

• Optical black: Horizontal (H) direction: Front 4 pixels, rear 56 pixels

Vertical (V) direction: Front 3 pixels, rear 1 pixel

• Number of dummy bits: Horizontal 24

Vertical 1

• Substrate material: Silicon

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

A

A

A

Pin 1

V

4

56

1

3

Pin 11

H

Optical black position

(Top View)

20 pin DIP (Ceramic)

∗

Wfine CCD is a registered trademark of Sony Corporation.

Represents a CCD adopting progressive scan, primary color filter and square pixel.

AAA
AAA
AAA

– 2 –

ICX085AK

Pin No. Symbol Description Pin No. Symbol Description

1
2
3
4
5
6
7
8
9

10

Vφ3
Vφ2
Vφ1
VL
GND
GND
NC
CGG
GND
VOUT

Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Protective transistor bias
GND
GND

Output amplifier gate

∗1

GND
Signal output

11
12
13
14
15
16
17
18
19
20

VRD
VDD
GND
SUB
NC
NC
RG
GND
Hφ1
Hφ2

Reset drain power supply
Supply voltage
GND
Substrate (overflow drain)

Reset gate clock
GND
Horizontal register transfer clock
Horizontal register transfer clock

Pin Description

1

2

3

4

5

6

7

8

9

10

11

12

13

14 15

16

Note)

Note) : Photo sensor

V

OUT

GND

NC

GND

GND

Vφ

1

Vφ

2

Vφ

3

V

DD

V

RD

GND

SUB

NC

RG

Hφ

1

Hφ

2

Horizontal register

17

18

19

20

V

L

C

GG

GND

NC

Vertical register

G
R
G
R
G
R

B
G
B
G
B
G

G
R
G
R
G
R

B
G
B
G
B
G

Block Diagram and Pin Configuration

(Top View)

∗1

DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of
1µF or more.

Substrate voltage SUB–GND

VDD, VOUT, VRD, CGG–GND

Supply voltage

VDD, VOUT, VRD, CGG–SUB
Vφ1, Vφ2, Vφ3–GND

Vφ1, Vφ2, Vφ3–SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2–Vφ3
Hφ1, Hφ2–GND
Hφ1, Hφ2–SUB
VL–SUB
Vφ2, Vφ3–VL
RG–GND
Vφ1, Hφ1, Hφ2, GND–VL
Storage temperature
Operating temperature

– 3 –

ICX085AK

Item

–0.3 to +55
–0.3 to +18

–55 to +9

–15 to +16

to +10
to +15

to +16
–16 to +16
–10 to +15
–55 to +10

–65 to +0.3
–0.3 to +27.5
–0.3 to +20.5
–0.3 to +17.5

–30 to +80
–10 to +60

V
V
V
V
V
V
V
V
V
V
V
V
V

V
°C
°C

∗1

Ratings Unit Remarks

Absolute Maximum Ratings

∗1

+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Vertical clock input
voltage

∗1

Indications of substrate voltage (VSUB) setting value
The setting value of the substrate voltage is indicated on the back of image sensor by a special code.
Adjust the substrate voltage (VSUB) to the indicated voltage.

VSUB code – two characters indication

↑ ↑

Integer portion Decimal portion

Integer portion of code and optimal setting correspond to each other as follows.

<Example> “G5”→ VSUB = 10.5V

∗2

VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL
power supply for the V driver should be used.

– 4 –

ICX085AK

Item

VDD
VSUB
VL

14.55

5.5

15.45

12.5

15.0

∗2

V
V

∗1

Symbol Min. Typ. Max. Unit Remarks

Bias Conditions

DC Characteristics

Supply voltage
Substrate voltage adjustment range
Protective transistor bias

Supply current IDD 6 8 mA

Item

Readout clock voltage

VVT
VVH02
VVH1,VVH2,VVH3
VVL1,VVL2,VVL3
Vφ1, Vφ2, Vφ3
| VVL1–VVL3 |
VVHH
VVHL
VVLH
VVLL

VφH
VHL
VφRG
V

RGLH–VRGLL

VRGH

VφSUB

14.55
–0.05

–0.2
–8.0

6.8

4.75

–0.05

4.5

VDD

+0.4

21.5

15.0
0
0

–7.5

7.5

5.0
0

5.0

VDD

+0.6

22.5

15.45

0.05

0.05
–7.0

8.05

0.1

0.5

0.5

0.5

0.5

5.25

0.05

5.5

0.8

VDD

+0.8

23.5

V
V
V
V
V
V
V
V
V
V
V
V
V
V

V
V

1
2
2
2
2
2
2
2
2
2
3
3
4
4

4
5

VVH = VVH02

VVL = (VVL1 + VVL3)/2

High-level coupling
High-level coupling
Low-level coupling
Low-level coupling

Input through 0.01µF capacitance
Low-level coupling

Horizontal transfer
clock voltage

Reset gate clock
voltage

Substrate clock voltage

Vertical transfer clock
voltage

Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

Clock Voltage Conditions

Item Symbol Min. Typ. Max. Unit Remarks

Integer portion of code
Optimal setting

A5C

6

d
7

E8f9G10h11J

12

– 5 –

ICX085AK

Clock Equivalent Circuit Constant

Item

Capacitance between vertical transfer
clock and GND

CφV1
CφV2, CφV3
CφV12
CφV23
CφV31
CφH1
CφH2

CφHH

CφRG

CφSUB
R1, R2, R3

RGND
RφH1, RφH2
RφRG

5000

10000

1200

100

3300

82
68

22

6

800

30
30
10
20

pF
pF
pF
pF
pF
pF
pF

pF

pF

pF

Ω
Ω
Ω
Ω

Capacitance between vertical transfer
clocks

Capacitance between horizontal
transfer clock and GND

Capacitance between horizontal
transfer clocks

Capacitance between reset gate clock
and GND

Capacitance between substrate clock
and GND

Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor

Symbol Min. Typ. Max. Unit Remarks

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

RφRG

RGφ

Cφ

RG

Reset gate clock equivalent circuit

RφH1 RφH2

Hφ2

CφH1 CφH2

CφHH

Vφ1

CφV12

Vφ2

Vφ3

CφV2

RGND

R3

R1

R2

CφV1

Cφv31

Cφv23

Hφ1

CφV3

– 6 –

ICX085AK

Drive Clock Waveform Conditions

(1) Readout clock waveform

(2) Vertical transfer clock waveform

II II

100%

90%

10%

0%

VVT

tr twh tf

φM

0V

φM

2

Vφ1

Vφ3

Vφ2

VVH1

VVHH VVH

VVHL

VVLH

VVL1

VVL01

VVL

VVLL

VVH3

VVHH VVH

VVHL

VVLH

VVL03

VVL

VVLL

VφV1 = VVH1 – VVL01
VφV2 = VVH02 – VVL2
VφV3 = VVH3 – VVL03

VVH = VVH02
VVL = (VVL01 + VVL03) /2

VVLH

VVL2

VVLL

VVL

VVH

VVHH

VVH02

VVH2

VVHL

VT