Sony ICX084AK Datasheet

Description

The ICX084AK is a diagonal 6mm (Type 1/3)
interline CCD solid-state image sensor with a square
pixel array which supports VGA format. Progressive
scan allows all pixels signals to be output
independently within approximately 1/30 second.
This chip features an electronic shutter with variable
charge-storage time which makes it possible to
realize full-frame still image without a mechanical
shutter. High resolution and high color reproductivity
are achieved through the use of R, G, B primary
color mosaic filters. Further, high sensitivity and low
dark current are achieved through the adoption of
HAD (Hole-Accumulation Diode) sensors.

This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.

Features

• Progressive scan allows individual readout of the

image signals from all pixels.

• High vertical resolution (480TV-lines) still image

without a mechanical shutter.

• Square pixel unit cell

• Supports VGA format

• Horizontal drive frequency: 12.27MHz

• No voltage adjustments

(reset gate and substrate bias are not adjusted.)

• R, G, B primary color mosaic filters on chip

• High resolution, high color reproductivity, high

sensitivity, low dark current

• Continuous variable-speed shutter

1/30 (typ.) to 1/10000s

• Low smear

• Excellent antiblooming characteristics

• Horizontal register: 5V drive

• 16-pin high precision plastic package (enables dual-

surface standard)

Device Structure

• Interline CCD image sensor

• Image size: Diagonal 6mm (Type 1/3)

• Number of effective pixels: 659 (H) × 494 (V) approx. 330K pixels

• Total number of pixels: 692 (H) × 504 (V) approx. 350K pixels

• Chip size: 5.84mm (H) × 4.94mm (V)

• Unit cell size: 7.4µm (H) × 7.4µm (V)

• Optical black: Horizontal (H) direction: Front 2 pixels, rear 31 pixels

Vertical (V) direction: Front 8 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 16

Vertical 5

• Substrate material: Silicon

– 1 –

ICX084AK

E95101E99

Diagonal 6mm (Type 1/3) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

16 pin DIP (Plastic)

A

A

A

Pin 1

V

2

31

2

8

Pin 9

H

Optical black position

(Top View)

∗

Wfine CCD is a registered trademark of Sony Corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.

AAA
AAA
AAA

– 2 –

ICX084AK

Pin No. Symbol Description Pin No. Symbol Description

1
2
3

4
5
6
7
8

Vφ3
Vφ2
Vφ1

NC
GND
CGG
GND
VOUT

Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock

GND
Output amplifier gate

∗1

GND
Signal output

9
10
11

12
13
14
15
16

VDD
SUBCIR
GND

φSUB
VL
RG
Hφ1
Hφ2

Supply voltage
Supply voltage for the substrate

voltage generation
GND

Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock

Pin Description

1

2

3

4

5

6

7

8

Note)

Note) : Photo sensor

V

OUT

GND

C

GG

GND

NC

Vφ

1

Vφ

2

Vφ

3

V

DD

SUBCIR

GND

φSUB

V

L

RG

Hφ

1

Hφ

2

Horizontal register

G B G B
R G R G
G B G B
R G R G
G B G B
R G R G

Vertical register

10

11

12

13

14 15

16

9

Block Diagram and Pin Configuration

(Top View)

Item

–0.3 to +36
–0.3 to +18

–22 to +9

–15 to +16

to +10
to +15

to +16
–16 to +16
–10 to +15
–55 to +10

–65 to +0.3
–0.3 to +27.5
–0.3 to +20.5
–0.3 to +17.5

–30 to +80
–10 to +60

V
V
V
V
V
V
V
V
V
V
V
V
V

V
°C
°C

∗2

Ratings Unit Remarks

Absolute Maximum Ratings

∗2

+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Substrate clock φSUB – GND

VDD, VOUT, CGG, SUBCIR – GND

Supply voltage

VDD, VOUT, CGG, SUBCIR – φSUB
Vφ1, Vφ2, Vφ3 – GND

Clock input voltage

Vφ1, Vφ2, Vφ3 – φSUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2 – Vφ3
Hφ1, Hφ2 – GND
Hφ1, Hφ2 – φSUB
VL – φSUB
Vφ2, Vφ3 – VL
RG– GND
Vφ1, Hφ1, Hφ2, GND– VL
Storage temperature
Operating temperature

∗1

DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of
1000pF or more.

– 3 –

ICX084AK

Item

VDD
VL
φSUB

14.55 15.4515.0

∗1
∗2

V

Symbol Min. Typ. Max. Unit Remarks

Bias Conditions

DC Characteristics

Supply voltage
Protective transistor bias
Substrate clock

Item

Supply current IDD 6 8 mA

Symbol Min. Typ. Max.

Unit

Remarks

Item

Readout clock voltage

VVT
VVH02
VVH1, VVH2, VVH3
VVL1, VVL2, VVL3
Vφ1, Vφ2, Vφ3
I VVL1 – VVL3 I
VVHH
VVHL
VVLH
VVLL
VφH
VHL

VφRG
VRGLH – VRGLL
VRGH
VφSUB

14.55
–0.05

–0.2
–8.0

6.8

4.75

–0.05

4.5

VDD

+0.4

21.5

15.0
0
0

–7.5

7.5

5.0
0

5.0

VDD

+0.6

22.5

15.45

0.05

0.05
–7.0

8.05

0.1

1.0

2.3

1.0

1.0

5.25

0.05

5.5

0.8

VDD

+0.8

23.5

V
V
V
V
V
V
V
V
V
V
V
V

V
V

V
V

1
2
2
2
2
2
2
2
2
2
3
3

4

4
4

5

VVH = VVH02

VVL = (VVL1 + VVL3)/2

High-level coupling
High-level coupling
Low-level coupling
Low-level coupling

Input through 0.01µF
capacitance

Low-level coupling

Horizontal transfer
clock voltage

Reset gate clock
voltage

Substrate clock voltage

Vertical transfer clock
voltage

Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

Clock Voltage Conditions

∗1

VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.

∗2

Set SUBCIR pin to open when applying a DC bias to the substrate clock pin.

– 4 –

ICX084AK

Clock Equivalent Circuit Constant

Item

Capacitance between vertical transfer
clock and GND

CφV1
CφV2
CφV3
CφV12
CφV23
CφV31

CφH1, CφH2

CφHH

CφRG

CφSUB
R1, R2

R3
RGND
RφH1, RφH2
RφRG

560

470
1500
1500
1500
1000

43

39

5

570

20
56
43
10
39

pF
pF
pF
pF
pF
pF

pF

pF

pF

pF

Ω
Ω
Ω
Ω
Ω

Capacitance between vertical transfer
clocks

Capacitance between horizontal transfer
clock and GND

Vertical transfer clock series resistor

Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor

Symbol Min. Typ. Max. Unit

Remarks

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

RφRG

RGφ

Cφ

RG

Reset gate clock equivalent circuit

RφH1 RφH2

Hφ2

CφH1 CφH2

CφHH

Vφ1

CφV12

Vφ2

Vφ3

CφV2

RGND

R3

R1

R2

CφV1

Cφv31

Cφv23

Hφ1

CφV3

Capacitance between horizontal transfer
clocks

Capacitance between reset gate clock
and GND

Capacitance between substrate clock
and GND

– 5 –

ICX084AK

Drive Clock Waveform Conditions

(1) Readout clock waveform

(2) Vertical transfer clock waveform

II II

100%

90%

10%

0%

VVT

tr twh tf

φM

0V

φM

2

Vφ1

Vφ3

Vφ2

VVH1

VVHH VVH

VVHL

VVLH

VVL1

VVL01

VVL

VVLL

VVH3

VVHH

VVH

VVHL

VVLH

VVL03

VVL

VVLL

VφV1 = VVH1 – VVL01
VφV2 = VVH02 – VVL2
VφV3 = VVH3 – VVL03

VVH = VVH02
VVL = (VVL01 + VVL03)/2
VVL3 = VVL03

VVLH

VVL2

VVLL

VVL

VVH

VVHH

VVH02

VVH2

VVHL

VT

Note) Readout clock is used by composing vertical transfer clocks Vφ2 and Vφ3.

– 6 –

ICX084AK

(3) Horizontal transfer clock waveform

tr twh tf

90%

10%

twl

Vφ

H

VHL

Hφ1, Hφ2

(4) Reset gate clock waveform

Point A

twl

Vφ

RG

VRGH

VRGL + 0.5V
V

RGL

VRGLH

RG waveform

VRGLL

Hφ1 waveform

twhtr tf

φ

RG

2.5V

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the interval twh, then:

VφRG = VRGH – VRGL

(5) Substrate clock waveform

90%

100%

10%

0%

V

SUB

tr twh tf

φM

φM

2

φSUB

VφSUB

(A bias generated within the CCD)