Sony ICX082AL Datasheet

Description

The ICX082AL is an interline CCD solid-state
image sensor suitable for EIA black-and-white video
cameras with a diagonal 11mm (Type 2/3) system.

High sensitivity and low dark current are achieved
through the adoption of HAD (Hole-Accumulation
Diode) sensors.

This chip features a field period readout system
and an electronic shutter with variable charge­storage time.

Features

• High sensitivity (+6dB compared with the ICX022BL)

• Low smear (–20dB compared with the ICX022BL)

• High resolution, Low dark current

• Excellent antiblooming characteristics

• Continuous variable-speed shutter

Device Structure

• Interline CCD image sensor

• Image size: Diagonal 11mm (Type 2/3)

• Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels

• Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels

• Chip size: 10.25mm (H) × 8.5mm (V)

• Unit cell size: 11.6µm (H) × 13.5µm (V)

• Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels

Vertical (V) direction: Front 12 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 22

Vertical 1 (even fields only)

• Substrate material: Silicon

– 1 –

ICX082AL

E95935C99

Diagonal 1 1mm (Type 2/3) CCD Image Sensor for EIA Black-and-White Video Cameras

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

20 pin DIP (Ceramic)

A

A

Pin 1

V

3

40

2

12

Pin 11

H

Optical black position

(Top View)

AAAA
AAAA

– 2 –

ICX082AL

Pin No.

Symbol Description

Description

Pin No.

Symbol

Pin Description

Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate (overflow drain)
GND
Vertical register transfer clock
Protective transistor bias

GND
Output amplifier drain power

1
2
3
4
5
6
7
8
9

10

Vφ4
Vφ3
Vφ2
SUB
GND
Vφ1
VL
NC
GND
VDD

11
12
13
14
15
16
17
18
19
20

VOUT
VGG
VSS
GND
RD
RG
VL
Hφ1
Hφ2
HIS

Signal output
Output amplifier gate bias
Output amplifier source
GND
Reset drain
Reset gate clock
Protective transistor bias
Horizontal register transfer clock
Horizontal register transfer clock

Horizontal register input source bias

Block Diagram and Pin Configuration

(Top View)

1

2

3

4

5

6

9

7

10
11
12
13
14

Note)

GND

V

DD

SUB

RG Hφ1

15

16

17

18

19

20

HIS

V

OUT

Vφ4

Vφ3

Vφ2

Vφ1

VL

GND

VGG

VSS

GND

RD Hφ2VL

Vertical Register

Horizontal Register

Note) : Photo sensor

Output Unit

– 3 –

ICX082AL

Item

–0.3 to +55
–0.3 to +20

–55 to +10
–15 to +20

to +10
to +15

to +17
–17 to +17
–10 to +15
–55 to +10

–65 to +0.3
–0.3 to +30
–0.3 to +24
–0.3 to +20

–30 to +80
–10 to +60

V
V
V
V
V
V
V
V
V
V
V
V
V

V
°C
°C

∗1

Ratings Unit Remarks

Absolute Maximum Ratings

∗1

+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Substrate voltage SUB – GND

HIS, VDD, RD, VOUT, VSS – GND
HIS, VDD, RD, VOUT, VSS – SUB
Vertical clock input pins – GND

Vertical clock input pins – SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2 – Vφ4
Hφ1, Hφ2, RG, VGG – GND
Hφ1, Hφ2, RG, VGG – SUB
VL – SUB
Vφ1, Vφ3, HIS, VDD, RD, VOUT – VL
RG – VL
Vφ2, Vφ4, VGG, VSS, Hφ1, Hφ2 – VL
Storage temperature
Operating temperature

Item

VDD
VRD
VGG

VSS
VSUB

∆VSUB
VRGL
∆VRGL
VL
VHIS

Grounded with

750Ω resistor

V
V
V

V

%

V

%

V
V

VRD = VDD

±5%

∗2

∗2

∗3

VHIS = VDD

Symbol Min.

Unit

Remarks

Bias Conditions

Output amplifier drain voltage
Reset drain voltage
Output amplifier gate voltage

Output amplifier source
Substrate voltage adjustment range

Substrate voltage adjustment precision
Reset gate clock voltage adjustment range
Reset gate clock voltage adjustment precision
Protective transistor bias
Horizontal register input source bias

14.7

14.7

3.8

Typ.

Max.

15.0

15.0

4.2

15.3

15.3

4.6

9

–3

0

–3

–11

14.7

–10.5

15.0

19
+3

3.0
+3

–10

15.3

Supply voltage

Vertical clock input voltage

– 4 –

ICX082AL

∗2

Indications of substrate voltage (VSUB) and reset gate clock voltage (VRGL) setting value
The setting value of the substrate voltage and reset gate clock voltage are indicated on the back of the
image sensor by a special code. Adjust the substrate voltage (VSUB) and reset gate clock voltage (VRGL) to
the indicated voltage. The adjustment precision is ±3%.

VSUB code — one character indication
VRGL code — one character indication ↑ ↑

VRGL code VSUB code

"Code" and optimal setting correspond to each other as follows.

DC Characteristics

<Example> "5K" → VRGL = 2.0V

VSUB = 12.0V

∗3

This must no exceed the VVL voltage of the vertical clock waveform.

∗4

1) Current to each pin when 20V is applied to VDD, RD, VOUT, VSS, HIS and SUB pins, while pins that are
not tested are grounded.

2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are
not tested are grounded. However, 20V is applied to SUB pin.

3) Current to each pin when 15V is applied sequentially to Hφ1, Hφ2, RG and VGG pins, while pins that are
not tested are grounded. However, 15V is applied to SUB pin.

4) Current to VL pin when 30V is applied to Vφ1, Vφ3, HIS, VDD, RD and VOUT pins or when, 24V is applied
to RG pin or when, 20V is applied to Vφ2, Vφ4, VGG, VSS, Hφ1 and Hφ2 pins, while VL pin is grounded.
However, GND and SUB pins are left open.

∗5

Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.

Item
Output amplifier drain current
Input current
Input current

IDD
IIN1
IIN2

6

1

10

mA

µA
µA

∗4
∗5

Symbol Min.

Typ. Max.

Unit

Remarks

VRGL code
Optimal setting 0 0.5 1.0 1.5 2.0

2.5

3.0

1 2

3 4 5 6

7

VSUB code
Optimal setting

9.0 9.5

10.0

10.511.0

11.5

12.0

D E

f G h J

K

L m

N P Q R

S T U

V W X Y

Z

12.5

13.013.5

14.0

14.5

15.0

15.5

16.0

16.5

17.0

17.5

18.0

18.5

19.0

– 5 –

ICX082AL

Item

VVT
VVH1, VVH2,

VVH3, VVH4
VVL1, VVL2,

VVL3, VVL4
VφV
| VVH1– VVH2 |
VVH3– VVH
VVH4– VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VφRG
VRGL
VφSUB

14.5
–0.6

8.9

–0.5
–0.5

6.0

–3.5

6.0
0

27.0

15.0

–9.6

15.5
0

0.2
0
0

0.8

1.0

0.8

0.8

8.0

–3.0

13.0

3.0

32.0

V
V

V
V

V
V
V
V
V
V
V
V
V
V
V
V

1
2

2
2

2
2
2
2
2
2
2
3
3
3
3
4

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2
V

φ

V = VVHn – VVLn (n = 1 to 4)

High-level coupling
High-level coupling
Low-level coupling
Low-level coupling

∗1

Readout clock voltage

Vertical transfer clock
voltage

Horizontal transfer
clock voltage

Reset gate clock
voltage

Substrate clock voltage

Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

Clock Voltage Conditions

∗1

The reset gate clock voltage need not be adjusted when the reset gate clock is driven when the
specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of
the image sensor has not significance.

Reset gate clock
voltage

Item

Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

VRGL
VφRG

–0.2

8.5

0

9.0

0.2

9.5

V
V

3
3