Description
The ICX068AKB is an interline CCD solid-state
image sensor suitable for NTSC color video cameras.
High resolution is achieved through the use of Ye, Cy,
Mg, and G complementary color mosaic filters. At the
same time, high sensitivity and low dark current are
achieved through the adoption of HAD (HoleAccumulation Diode) sensors.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time.
Also, this outline is miniaturized by using original
package.
Features
• Maximum package dimensions: φ8mm
• High resolution, high sensitivity and low dark current
• Horizontal register: 3.6 to 5.0V drive
• No voltage adjustment
(Reset gate and substrate bias are not adjusted.)
• Low smear
• Excellent antiblooming characteristics
• Continuous variable-speed shutter
• Ye, Cy, Mg, and G complementary color mosaic filters on chip
Device Structure
• Image size: Diagonal 4.5mm (Type 1/4)
• Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels
• Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels
• Interline CCD image sensor
• Chip size: 4.47mm (H) × 3.80mm (V)
• Unit cell size: 4.75µm (H) × 5.55µm (V)
• Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction: Front 12 pixels, rear 2 pixels
• Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
• Substrate material: Silicon
– 1 –
ICX068AKB
E94727D99
Diagonal 4.5mm (Type 1/4) CCD Image Sensor for NTSC Color Video Cameras
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
13 pin PCA (Ceramic)
Pin 1
V
3
40
2
12
Pin 8
H
Optical black position
(Top View)
AAA
AAA
AAA
– 2 –
ICX068AKB
Substrate clock φSUB–GND
Supply voltage
Clock input voltage
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2 – Vφ4
Hφ1, Hφ2 – GND
Hφ1, Hφ2 – φSUB
VL – φSUB
Vφ1, Vφ3, VDD, VOUT – VL
RG – GND
Vφ2, Vφ4, Hφ1, Hφ2, GND – VL
Storage temperature
Operating temperature
Block Diagram and Pin Configuration
(Top View)
5
6
7
Note)
Note) : Photo sensor
V
OUT
GND
Vφ1
Vφ2
Vφ3
Vφ4
V
DD
φSUB
V
L
RG
Hφ1
Hφ2
Horizontal Register
Vertical Register
2
3
4
NC
Cy
Cy
Mg
G
Cy
Mg
Ye
Ye
G
Mg
Ye
G
Cy
Cy
Mg
G
Cy
Mg
Ye
Ye
G
Mg
Ye
G
8
9
10
11
13
12
1
Pin No.
1
2
3
4
5
6
7
Vφ4
Vφ3
Vφ2
Vφ1
NC
GND
VOUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output
8
9
10
11
12
13
VDD
φSUB
VL
RG
Hφ1
Hφ2
Supply voltage
Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Symbol Description Pin No. Description
Pin Description
Absolute Maximum Ratings
–0.3 to +40
–0.3 to +18
–30 to +9
–15 to +16
to +10
to +15
to +16
–16 to +16
–10 to +15
–55 to +10
–65 to +0.3
–0.3 to +27.5
–0.3 to +20.5
–0.3 to +17.5
–30 to +80
–10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗1
VDD, VOUT – GND
VDD, VOUT – φSUB
Vφ1, Vφ2, Vφ3, Vφ4 – GND
Vφ1, Vφ2, Vφ3, Vφ4 – φSUB
Item Ratings Unit Remarks
∗1
+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
Symbol
2
3
4
5
6
7
8
9
10
11
12
13
1
Hφ1
RG
V
L
φSUB
V
DD
GND
NC
Hφ
2
Vφ4
Vφ1
Vφ2
Vφ3
VOUT
– 3 –
ICX068AKB
Clock Voltage Conditions
Item
Readout clock voltage
VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
VφV
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VφRG
VRGLH – VRGLL
VRGH
VφSUB
14.55
–0.05
–0.2
–8.0
6.8
–0.25
–0.25
3.3
–0.05
4.5
VDD +
0.3
21.5
15.0
0
0
–7.5
7.5
5.0
0
5.0
VDD +
0.6
22.5
15.45
0.05
0.05
–7.0
8.05
0.1
0.1
0.3
0.3
0.3
0.3
5.25
0.05
5.5
0.8
VDD +
0.9
23.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.01µF
capacitance
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical transfer clock
voltage
Symbol Min.
Typ. Max.
Unit
Waveform
diagram
Remarks
Bias Conditions
Item
Supply voltage
Protective transistor bias
Substrate clock
VDD
VL
φSUB
14.55
15.0
∗1
∗2
15.45 V
Symbol Min. Typ. Max. Unit Remarks
DC Characteristics
Item
Supply current IDD 6 8 mA
Symbol Min. Typ. Max. Unit Remarks
∗1
VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗2
Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
– 4 –
ICX068AKB
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer
clock and GND
CφV1, CφV3
CφV2, CφV4
CφV12, CφV34
CφV23, CφV41
CφV13
CφV24
CφH1, CφH2
CφHH
CφRG
CφSUB
R1, R2, R3, R4
RGND
RφH
RφRG
680
470
220
180
82
75
33
27
5
170
82
15
39
39
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Ω
Capacitance between vertical transfer
clocks
Capacitance between horizontal
transfer clock and GND
Capacitance between horizontal
transfer clocks
Capacitance between reset gate clock
and GND
Capacitance between substrate clock
and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor
Symbol Min. Typ. Max. Unit Remarks
RφH RφH
Hφ2
Hφ1
CφH1
CφH2
CφHH
Vφ1
CφV12
Vφ2
Vφ4 Vφ3
CφV34
CφV23
CφV41
CφV13
CφV24
CφV1
CφV2
CφV4 CφV3
RGND
R4
R1
R3
R2
Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit
RφRG
RGφ
Cφ
RG
Reset gate clock equivalent circuit
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
II II
100%
90%
10%
0%
VVT
tr twh tf
φM
0V
φM
2
Vφ1 Vφ3
Vφ2 Vφ4
VVHH
VVH
VVHL
VVHH
VVHL
VVH1
VVL1
VVLH
VVLL
VVL
VVHH
VVH3
VVHL
VVH
VVHH
VVHL
VVL3
VVL
VVLL
VVLH
VVHH VVHH
VVH
VVHL
VVHL
VVH2
VVLH
VVL2
VVLL
VVL
VVHH VVHH
VVHL
VVH4
VVHL
VVH
VVL
VVLH
VVLL
VVL4
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
tr twh tf
90%
10%
twl
Vφ
H
VHL
(3) Horizontal transfer clock waveform
Point A
twl
Vφ
RG
VRGH
VRGL + 0.5V
V
RGL
VRGLH
RG waveform
V
RGLL
Hφ1 waveform
twhtr tf
2.5V
(4) Reset gate clock waveform
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
(5) Substrate clock waveform
90%
100%
10%
0%
V
SUB
tr twh tf
φM
φM
2
VφSUB
(A bias generated within the CCD)