Sony ICX062AL Datasheet

Description

The ICX062AL is an interline CCD solid-state
image sensor suitable for EIA black-and-white video
cameras with a diagonal 11mm (Type 2/3)
system.

High sensitivity is achieved by adopting HAD (Hole­Accumulation Diode) sensors. The chip features a
field period readout system and an electronic shutter
with variable charge-storage time.

Features

• High resolution

• Low smear

• High sensitivity, low dark current

• Excellent antiblooming characteristics

• Continuous variable-speed shutter

Device Structure

• Image size: Diagonal 11mm (Type 2/3)

• Number of effective pixels: 980 (H) × 494 (V), approx. 480K pixels

• Total number of pixels: 1038 (H) × 504 (V), approx. 520K pixels

• Interline CCD image sensor

• Chip size: 10.75mm (H) × 8.7mm (V)

• Unit cell size: 9.3µm (H) × 13.6µm (V)

• Optical black: Horizontal (H) direction; front 3 pixels, rear 55 pixels

Vertical (V) direction; front 8 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 25

Vertical 1 (even fields only)

• Substrate material: Silicon

– 1 –

ICX062AL

E95632D99

Diagonal 11mm (Type 2/3) CCD Image Sensor for EIA B/W Video Camera

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

A

A

A

Pin 1

V

3

55

2

8

Pin 11

H

Optical black position

(Top View)

20 pin DIP (Ceramic)

AAA
AAA
AAA

– 2 –

ICX062AL

Pin No. Symbol Description Pin No. Symbol Description

1
2
3
4
5
6
7
8
9

10

Vφ4
Vφ3
Vφ2
SUB
GND
Vφ1
VL
NC
NC
VDD

Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Substrate (overflow drain)
GND
Vertical register transfer clock
Protective transistor bias

Output amplifier drain power

11
12
13
14
15
16
17
18
19
20

VOUT
VGG
VSS
GND
RD
RG
VL
Hφ1
Hφ2
HIS

Signal output
Output amplifier gate bias
Output amplifier source
GND
Reset drain
Reset gate clock
Protective transistor bias
Horizontal register transfer clock
Horizontal register transfer clock
Horizontal register input source bias

Pin Description

2

3
4

5

6

7

10

11
12
13
14

15

16

17

18

19

20

1

VL

VDD

VOUT

VGG

VSS

GND

Output Unit

RD RG VL Hφ1 Hφ2 HIS

Vertical Register

Vφ1

GND

SUB

Vφ

2

Vφ3

Vφ4

Horizontal Register

(Note)

(Note) : Photo sensor

Block Diagram and Pin Configuration (Top View)

– 3 –

ICX062AL

Item

–0.3 to +55
–0.3 to +20

–55 to +10
–15 to +20
–65 to +10

to +15

to +17
–17 to +17
–10 to +15
–55 to +10

–65 to +0.3
–0.3 to +30

–30 to +80
–10 to +60

V
V
V
V
V
V
V
V
V
V
V

V

°C
°C

∗1

Ratings Unit Remarks

Absolute Maximum Ratings

∗1

+27V (max.) when clock width < 10µs and the clock duty factor < 0.1%.

Substrate voltage SUB – GND

Supply voltage

Vertical, horizontal
clock input voltage

Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2 – Vφ4
RG, VGG – GND
RG, VGG – SUB
VL – SUB
Vφ1, Vφ2, Vφ3, Vφ4, Hφ1, Hφ2, HIS, VDD, RD, VOUT,

VSS, RG, VGG – VL
Storage temperature
Operating temperature

HIS, VDD, RD, VOUT, VSS – GND
HIS, VDD, RD, VOUT, VSS – SUB
Vφ1, Vφ2, Vφ3, Vφ4, Hφ1, Hφ2 – GND
Vφ1, Vφ2, Vφ3, Vφ4, Hφ1, Hφ2 – SUB

Item

VDD
VRD
VGG

VSS
VSUB

∆VSUB
VRGL
∆VRGL
VL
VHIS

14.7

14.7

1.6

9

–3

0

–3

–13

14.7

15.0

15.0

2.0

15.0

15.3

15.3

2.6

19
+3

3.0
+3

–10

15.3

V
V
V

V

%

V

%

V
V

VRD = VDD

±5%

∗1

∗1

∗2

VHIS = VDD

Symbol Min. Typ. Max. Unit Remarks

Bias Conditions

Grounded with

390Ω resistor

Output amplifier drain voltage
Reset drain voltage
Output amplifier gate voltage

Output amplifier source
Substrate voltage adjustment range

Substrate voltage adjustment accuracy
Reset gate clock voltage adjustment range
Reset gate clock voltage adjustment accuracy
Protective transistor bias
Horizontal register input source bias

– 4 –

ICX062AL

∗1

Indications of substrate voltage (VSUB) and reset gate clock voltage (VRGL) setting value
The setting value of the substrate voltage and reset gate clock voltage are indicated on the back of the
image sensor by a special code. Adjust the substrate voltage (VSUB) and reset gate clock voltage (VRGL) to
the indicated voltage. The adjustment accuracy is ±3%.

VSUB code – one character indication
VRGL code – one character indication ↑ ↑

VRGL code VSUB code

"Code" and optimal setting correspond to each other as follows.

DC Characteristics

1

VRGL code
Optimal setting

0 0.5 1.0 1.5 2.0 2.5 3.0

2 3 4 5 6 7

VSUB code
Optimal setting

9.0 9.5

10.0

10.5 11.011.512.012.5 13.013.5 14.014.515.015.5 16.016.5 17.0 17.518.0

18.5

D E f G h J K L m N P Q R S T U V W X

Y

19.0

Z

<Example> "5K"→ VRGL = 2.0V

VSUB = 12.0V

∗2

This must no exceed the VVL voltage of the vertical clock waveform.

∗3

1) Current to each pin when 20V is applied to VDD, RD, VOUT, Vss, HIS, and SUB pins, while pins that are
not tested are grounded.

2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3, Vφ4, Hφ1, and Hφ2 pins, while pins
that are not tested are grounded. However, 20V is applied to SUB pin.

3) Current to each pin when 15V is applied sequentially to RG and VGG pins, while pins that are not tested
are grounded. However, 15V is applied to SUB pin.

4) Current to VL pin when 30V is applied to all pins except the pin being tested and when VL pin is
grounded. However, GND and SUB pins are left open.

∗4

Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.

Item

Output amplifier drain current
Input current
Input current

IDD
IIN1
IIN2

5

1

10

mA

µA
µA

∗3
∗4

Symbol Min. Typ. Max. Unit Remarks

– 5 –

ICX062AL

Item

Readout clock voltage

VVT
VVH1, VVH2,

VVH3, VVH4
VVL1, VVL2,

VVL3, VVL4
VφV
I VVH1 – VVH2I
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VφRG
V

RGL

VφSUB

14.5
–0.6

8.9

–0.5
–0.5

6.0

–4.0

6.0
0

27.0

15.0

–9.6

15.5
0

0.2
0
0

0.8

1.0

0.8

0.8

8.0

–3.5

13.0

3.0

32.0

V
V

V
V

V
V
V
V
V
V
V
V
V
V
V
V

1
2

2
2

2
2
2
2
2
2
2
3
3
3
3
4

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2
VφV= VVHn – VVLn (n = 1 to 4)

High-level coupling
High-level coupling
Low-level coupling
Low-level coupling

∗1

∗2

Horizontal transfer
clock voltage

Reset gate clock
voltage

Substrate clock voltage

Vertical transfer
clock voltage

Symbol

Min. Typ. Max. Unit

Waveform

diagram

Remarks

∗1

The reset gate clock voltage need not be adjusted when the reset gate clock is driven when the
specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of
the image sensor has not significance.

Item

Reset gate clock
voltage

Symbol

VRGL
VφRG

–0.2

8.5

0

9.0

0.2

9.5

V
V

3
3

Min.

Typ. Max.

Unit

Waveform

diagram

Remarks

Clock Voltage Conditions

∗2

The electronic shutter speed must be between 1/60 and 1/2000s.