Sony ICX059AK Datasheet

ICX059AK

A

A

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1/3-inch CCD Image Sensor for PAL Color Camera

Description

The ICX059AK is an interline CCD solid-state image
sensor suitable for PAL color video cameras. High
resolution is achieved through the use of Ye, Cy, Mg,
and G complementary color mosaic filters. At the
same time, high sensitivity and low dark current are
achieved through the adoption of HAD (Hole­Accumulation Diode) sensors.

This chip features a field period readout system and
an electronic shutter with variable charge-storage time.

Features

• High resolution, high sensitivity and low dark current

• Continuous variable-speed shutter

1/50s (Typ.), 1/120s to 1/10000s

• Low smear

• Excellent antiblooming characteristics

• Ye, Cy, Mg, and G complementary color mosaic filters on chip

• Horizontal register: 5V drive

• Reset gate: 5V drive

16 pin DIP (Plastic)

V

3

Pin 9

Pin 1

AAA
AAA

H

2

12

40

Device Structure

• Optical size: 1/3-inch format

• Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels

• Number of total pixels: 795 (H) × 596 (V) approx. 470K pixels

• Interline CCD image sensor

• Chip size: 6.00mm (H) × 4.96mm (V)

• Unit cell size: 6.50µm (H) × 6.25µm (V)

• Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels

Vertical (V) direction: Front 12 pixels, rear 2 pixels

• Number of dummy bits: Horizontal 22

Vertical 1 (even field only)

• Substrate material: Silicon

Optical black position

(Top View)

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E91Y29B5Y-PS

Block Diagram and Pin Configuration

(Top View)

OUT

V

8

ICX059AK

2

5

GND

1

Vφ

Vφ

4

3

SS

GG

V

V

6

7

4

3

Vφ

Vφ

1

2

Pin Description

Pin No.

1
2
3
4
5
6
7

Symbol

Vφ4
Vφ3
Vφ2
Vφ1
GND
VGG
VSS

9

10

DD

V

GND

Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Output amplifier gate bias
Output amplifier source

Cy

Ye

Cy

Mg
Cy

GMgGMg

Cy

Vertical register

Mg G Mg G

Horizontal register

12

11

L

V

SUB

Mg G

G

Cy Ye

Ye

Ye Cy Ye

13

14 15

1

RG

LHφ

Pin No.

9
10
11
12
13
14
15

Symbol

VDD
GND
SUB
VL
RG
LHφ1
Hφ1

Ye

Note)

Note) :Photo sensor

16

2

1

Hφ

Hφ

Description
Output amplifier drain supply
GND
Substrate (Overflow drain)
Protective transistor bias
Reset gate clock
Horizontal register final stage transfer clock
Horizontal register transfer clock

8

VOUT

Signal output

Absolute Maximum Ratings

Item Ratings Unit Remarks

Substrate voltage SUB – GND

VDD, VOUT, VSS – GND

Supply voltage

VDD, VOUT, VSS – SUB
Vφ1, Vφ2, Vφ3, Vφ4 – GND

Vertical clock input voltage

Vφ1, Vφ2, Vφ3, Vφ4 – SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2 – Vφ4
Hφ1, Hφ2, LHφ1, RG, VGG – GND
Hφ1, Hφ2, LHφ1, RG, VGG – SUB
VL – SUB
Vφ1, Vφ2, Vφ3, Vφ4, VDD, VOUT – VL
RG – VL

16

Hφ2

Horizontal register transfer clock

–0.3 to +55
–0.3 to +18

–55 to +10
–15 to +20

to +10
to +15

to +17
–17 to +17
–10 to +15
–55 to +10

–65 to +0.3
–0.3 to +30
–0.3 to +24

V
V
V
V
V
V
V
V
V
V
V
V
V

∗1

VGG, VSS, Hφ1, Hφ2, LHφ1 – VL
Storage temperature
Operating temperature

∗1

+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

– 2 –

–0.3 to +20

–30 to +80
–10 to +60

V
°C
°C

Bias Conditions

ICX059AK

Item
Output amplifier drain voltage
Output amplifier gate voltage

Output amplifier source
Substrate voltage adjustment range

Fluctuation range after substrate voltage adjustment
Reset gate clock voltage adjustment range
Fluctuation range after reset gate clock voltage

adjustment
Protective transistor bias

DC Characteristics

Item
Output amplifier drain current
Input current
Input current

Symbol Min. Typ. Max. Unit Remarks

IDD
IIN1
IIN2

Symbol Min. Typ. Max. Unit Remarks

%

%

V
V

±5%

∗1

V

∗1 ∗6

V

VDD
VGG

VSS
VSUB

∆VSUB
VRGL

∆VRGL
VL

5

14.55

3.8
Grounded with

820Ω resistor

9.0

–3

1.0

–3

1

10

15.0

4.2

∗2

mA

µA
µA

15.45

4.65

18.5
+3

4.0
+3

∗3
∗4

∗1

Indications of substrate voltage (VSUB) · reset gate clock voltage (VRGL) setting value.
The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image
sensor by a special code. Adjust substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the
indicated voltage. Fluctuation range after adjustment is ±3%.

VSUB code one character indication
VRGL code one character indication ↑↑

VRGL code VSUB code

Code and optimal setting correspond to each other as follows.

VRGL code
Optimal setting

VSUB code
Optimal setting

1

3

2

45

1.0 1.5 2.0 2.5 3.0 3.5 4.0

EfG

9.0 9.5

hJKL

10.0 10.5 11.0 11.5 12.012.5 13.0 13.5 14.0 14.5 15.0 15.516.0 16.5 17.0 17.5 18.0 18.5

6

7

m

NP

Q

R

S

UVWX

T

<Example> “5L” → VRGL = 3.0V

VSUB = 12.0V

∗2

VL setting is the VVL voltage of the vertical transfer clock waveform.

∗3

1) Current to each pin when 18V is applied to VDD, VOUT, Vss and SUB pins, while pins that are not tested
are grounded.

2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are
not tested are grounded. However, 20V is applied to SUB pin.

3) Current to each pin when 15V is applied sequentially to RG, LHφ1, Hφ1, Hφ2 and VGG pins, while pins
that are not tested are grounded. However, 15V is applied to SUB pin.

4) Current to VL pin when 30V is applied to Vφ1, Vφ2, Vφ3, Vφ4, VDD and VOUT pins or when, 24V is applied
to RG pin or when, 20V is applied to VGG, Vss, Hφ1, Hφ2 and LHφ1 pins, while VL pin is grounded.
However, GND and SUB pins are left open.

∗4

Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.

– 3 –

Y

Z

Clock Voltage Conditions

ICX059AK

Item

Readout clock voltage

Vertical transfer clock
voltage

Horizontal transfer
clock voltage

Reset gate clock
voltage

Symbol Min.

VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,

VVL3, VVL4
VφV
I VVH1 – VVH2 I
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH,VφLH
VHL,VLHL
VφRG
VRGLH – VRGLL

14.55
–0.05

–0.2
–9.0

7.8

–0.25
–0.25

4.75

–0.05

4.5

Typ. Max.

15.0

–8.5

0
0

8.5

15.45

0.05

0.05
–8.0

9.05

0.1

0.1

0.1

0.5

0.5

0.5

0.5

5.0

5.0

5.25

0

0.05

5.5

0.8

Unit

V
V
V

V
V

V
V
V
V
V
V
V
V
V
V
V

Waveform

diagram

1
2
2

2
2

2
2
2
2
2
2
2
3
3
4
4

Remarks

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)

High-level coupling
High-level coupling
Low-level coupling
Low-level coupling

∗5
∗5
∗6

Low-level coupling

Substrate clock voltage

∗5

The horizontal final stage transfer clock input pin LHφ1 is connected to the horizontal transfer clock input

VφSUB

22.5

23.5

24.5

V

5

pin Hφ1.

∗6

The reset gate clock voltage need not be adjusted when reset gate clock is driven when the specifications
are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image
sensor has not significance.

Item

Reset gate clock
voltage

Symbol

VRGL
VφRG

Min.
–0.2

8.5

Typ.

0

9.0

Max.

0.2

9.5

Unit

V
V

Waveform

diagram

4
4

Remarks

– 4 –

Clock Equivalent Circuit Constant

ICX059AK

Item

Capacitance between vertical transfer
clock and GND

Capacitance between vertical transfer
clocks

Capacitance between horizontal
transfer clock and GND

Capacitance between horizontal
transfer clocks

Capacitance between horizontal final
stage transfer clock and GND

Capacitance between reset gate clock
and GND

Capacitance between substrate clock
and GND

Vertical transfer clock series resistor

Symbol Min. Typ. Max. Unit Remarks
CφV1, CφV3
CφV2, CφV4
CφV12, CφV34
CφV23, CφV41
CφV13
CφV24

CφH1, CφH2

CφHH

CφLH

CφRG

CφSUB
R1, R2, R3, R4

1000

560
470
390
180
100

47

51

8

8

270

80

pF
pF
pF
pF
pF
pF

pF

pF

pF

pF

pF

Ω

Vertical transfer clock ground resistor
Horizontal transfer clock series resistor

Vφ1

R1

CφV41

CφV24

R4

Vφ4 Vφ3

CφV12

CφV1 CφV2

RGND

CφV4 CφV3

CφV34

R2

CφV23

CφV13

R3

Vφ2

RGND
RφH

Hφ1

15
15

RφH RφH

CφHH

CφH1

CφH2

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

Ω
Ω

Hφ2

– 5 –

Drive Clock Waveform Conditions

(1) Readout clock waveform

100%

90%

ICX059AK

II II

φM

VVT

10%

0%

tr twh tf

(2) Vertical transfer clock waveform

Vφ1 Vφ3

VVH1

VVL

VVHH

VVLL

VVL1

VVH

VVHL

VVLH

VVHH

VVHL

VVL3

VVHL

φM

2

VVHH

VVH3

VVL

VVHL

VVHH

0V

VVH

VVLH

VVLL

Vφ2 Vφ4

VVH2

VVHH VVHH

VVHL

VVL

VVLL

VVH

VVL2

VVHL

VVLH

VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)

– 6 –

VVL4

VVLL

VVH

VVLH

VVHL

VVHH VVHH

VVHL

VVH4

VVL