Sony ICX055BL Datasheet

– 1 –

ICX055BL

E98225A99

Diagonal 6mm (Type 1/3) CCD Image Sensor for CCIR B/W Video Cameras

Description

The ICX055BL is an interline CCD solid-state image
sensor suitable for CCIR B/W video cameras.
Compared with the current product ICX055AL,
sensitivity is improved drastically through the adoption
of Super HAD CCD technology.

This chip features a field period readout system,
and an electronic shutter with variable charge-storage
time.

Features

• High sensitivity (+4dB at F8, +2dB at F1.2 compared with ICX055AL)

• High saturation signal (+1dB compared with ICX055AL)

• Low smear and low dark current

• Excellent antiblooming characteristics

• Continuous variable-speed shutter

• Horizontal register: 5V drive

• Reset gate: 5V drive

Device Structure

• Interline CCD image sensor

• Image size: Diagonal 6mm(Type 1/3)

• Number of effective pixels: 500 (H) × 582 (V) approx. 290K pixels

• Number of total pixels: 537 (H) × 597 (V) approx. 320K pixels

• Chip size: 6.00mm (H) × 4.96mm (V)

• Unit cell size: 9.8µm (H) × 6.3µm (V)

• Optical black: Horizontal (H) direction: Front 7 pixels, Rear 30 pixels

Vertical (V) direction: Front 14 pixels, Rear 1 pixel

• Number of dummy bits: Horizontal 16

Vertical 1 (even field only)

• Substrate material: Silicon

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

16 pin DIP (Plastic)

A

A

A

Pin 1

V

7

30

1

14

Pin 9

H

Optical black position

(Top View)

∗

Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly
developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.

AAA
AAA
AAA

– 2 –

ICX055BL

1

2

3

4

5

6

7

8

9

10

11

12

13

14 15

16

Note

Note) : Photo sensor

V

OUT

V

SS

V

GG

GND

Vφ

1

Vφ

2

Vφ

3

Vφ

4

V

DD

GND

SUB

V

L

RG

NC

Hφ

1

Hφ

2

Horizontal register

Vertical register

Substrate voltage SUB – GND

VDD, VOUT, VSS – GND

Supply voltage

VDD, VOUT, VSS – SUB
Vφ1, Vφ2, Vφ3, Vφ4 – GND

Vertical clock input voltage

Vφ1, Vφ2, Vφ3, Vφ4 – SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2 – Vφ4
Hφ1, Hφ2, RG, VGG – GND
Hφ1, Hφ2, RG, VGG – SUB
VL – SUB
Vφ1, Vφ2, Vφ3, Vφ4, VDD, VOUT – VL
RG – VL
VGG, Vss, Hφ1, Hφ2 – VL
Storage temperature
Operating temperature

Pin No. Symbol Description Pin No. Symbol Description

1
2
3
4
5
6
7
8

Vφ4
Vφ3
Vφ2
Vφ1
GND
VGG
VSS
VOUT

Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Output amplifier gate bias
Output amplifier source
Signal output

9
10
11
12
13
14
15
16

VDD
GND
SUB
VL
RG
NC
Hφ1
Hφ2

Output amplifier drain supply
GND
Substrate (Overflow drain)
Protective transistor bias
Reset gate clock

Horizontal register transfer clock
Horizontal register transfer clock

Pin Description

Item

–0.3 to +55
–0.3 to +18

–55 to +10
–15 to +20

to +10
to +15

to +17
–17 to +17
–10 to +15
–55 to +10

–65 to +0.3
–0.3 to +30
–0.3 to +24
–0.3 to +20

–30 to +80
–10 to +60

V
V
V
V
V
V
V
V
V
V
V
V
V

V
°C
°C

∗1

Ratings Unit Remarks

Absolute Maximum Ratings

*1+27V (Max.) when clock width<10µs, clock duty factor<0.1%.

Block Diagram and Pin Configuration

(Top View)

– 3 –

ICX055BL

Item

VDD
VGG

VSS

VSUB
∆VSUB
VRGL
∆VRGL
VL

14.55

1.75

9.0
–3

1.0
–3

15.0

2.0

∗2

15.45

2.25

18.5
+3

4.0
+3

V
V

V

%

V

%

±5%

∗1

∗1

Symbol Min. Typ. Max. Unit Remarks

Bias Conditions

DC Characteristics

Grounded with

680Ω resistor

Item

Output amplifier drain current
Input current
Input current

IDD
IIN1
IIN2

3

1

10

mA

µA
µA

∗3
∗4

Symbol Min. Typ. Max. Unit Remarks

Output amplifier drain voltage
Output amplifier gate voltage

Output amplifier source

Substrate voltage adjustment range
Fluctuation range after substrate voltage adjustment
Reset gate clock voltage adjustment range
Fluctuation range after reset gate clock voltage adjustment
Protective transistor bias

∗1

Indications of substrate voltage (VSUB) · reset gate clock voltage (VRGL) setting value.
The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image
sensor by a special code. Adjust substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the
indicated voltage. Fluctuation range after adjustment is ±3%.

VSUB code one character indication
VRGL code one character indication ↑ ↑

VRGL code VSUB code

Code and optimal setting correspond to each other as follows.

1

VRGL code
Optimal setting 1.0 1.5 2.0 2.5 3.0 3.5 4.0

2

3

4 5

6

7

VSUB code
Optimal setting

9.0 9.5

10.0 10.5 11.011.5 12.0 12.5 13.0 13.514.014.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0

E f G

h J K L

m

N P

Q

R

S

T

U V W X

Y

Z

<Example> “5L” → VRGL = 3.0V

VSUB = 12.0V

∗2

VL setting is the VVL voltage of the vertical transfer clock waveform.

∗3

1) Current to each pin when 18V is applied to VDD, VOUT, Vss and SUB pins, while pins that are not tested
are grounded.

2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are
not tested are grounded. However, 20V is applied to SUB pin.

3) Current to each pin when 15V is applied sequentially to RG, Hφ1, Hφ2 and VGG pins, while pins that are
not tested are grounded. However, 15V is applied to SUB pin.

4) Current to VL pin when 30V is applied to Vφ1, Vφ2, Vφ3, Vφ4, VDD and VOUT pins or when, 24V is applied
to RG pin or when, 20V is applied to VGG, Vss, Hφ1 and Hφ2 pins, while VL pin is grounded. However,
GND and SUB pins are left open.

∗4

Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.

18.5

– 4 –

ICX055BL

Item

Readout clock voltage

VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,

VVL3, VVL4
VφV
|VVH1 – VVH2|
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VφRG
V

RGLH –

V

RGLL

VφSUB

14.55
–0.05

–0.2
–9.0

7.8

–0.25
–0.25

4.75

–0.05

4.5

22.5

15.0
0
0

–8.5

8.5

5.0
0

5.0

23.5

15.45

0.05

0.05
–8.0

9.05

0.1

0.1

0.1

0.5

0.5

0.5

0.5

5.25

0.05

5.5

0.8

24.5

V
V
V

V
V

V
V
V
V
V
V
V
V
V
V
V
V

1
2
2

2
2

2
2
2
2
2
2
2
3
3
4
4
5

VVH = (VVH1 + VVH2) /2

VVL = (VVL3 + VVL4) /2
VφV = VVHn – VVLn (n = 1 to 4)

High-level coupling
High-level coupling
Low-level coupling
Low-level coupling

∗1

Low-level coupling

Horizontal transfer
clock voltage

Reset gate clock
voltage

Substrate clock voltage

Vertical transfer clock
voltage

Symbol Min. Typ. Max. Unit

Waveform

diagram

Remarks

Clock Voltage Conditions

Item

Reset gate clock
voltage

Symbol
VRGL

VφRG

–0.2

8.5

0

9.0

0.2

9.5

V
V

4
4

Min. Typ. Max. Unit

Waveform

diagram

Remarks

∗1

The reset gate clock voltage need not be adjusted when reset gate clock is driven when the specifications
are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image
sensor has not significance.

– 5 –

ICX055BL

Clock Equivalent Circuit Constant

Item

Capacitance between vertical transfer
clock and GND

CφV1, CφV3
CφV2, CφV4
CφV12, CφV34
CφV23, CφV41
CφV13
CφV24

CφH1, CφH2

CφHH

CφRG

CφSUB
R1, R3

R2, R4
RGND
RφH
RφRG

1500

820
470
230
150
230

47

47

5

320

51

100

15
10
40

pF
pF
pF
pF
pF
pF

pF

pF

pF

pF

Ω
Ω
Ω
Ω
Ω

Capacitance between vertical transfer
clocks

Vertical transfer clock series resistor

Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor

Symbol Min. Typ. Max. Unit Remarks

RφH RφH

Hφ2Hφ1

CφH1 CφH2

CφHH

Vφ1

CφV12

Vφ2

Vφ4 Vφ3

CφV34

CφV23

CφV41

CφV13

CφV24

CφV1 CφV2

CφV4 CφV3

RGND

R4

R1

R3

R2

Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

RφRG

RGφ

Cφ

RG

Reset gate clock equivalent circuit

Capacitance between horizontal
transfer clock and GND

Capacitance between horizontal
transfer clocks

Capacitance between reset gate clock
and GND

Capacitance between substrate clock
and GND

– 6 –

ICX055BL

VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)

Vφ1 Vφ3

Vφ2 Vφ4

VVHH

VVH

VVHL

VVHH

VVHL

VVH1

VVL1

VVLH

VVLL

VVL

VVHH

VVH3

VVHL

VVH

VVHH

VVHL

VVL3

VVL

VVLL

VVLH

VVHH VVHH

VVH

VVHL

VVHL

VVH2

VVLH

VVL2

VVLL

VVL

VVHH VVHH

VVHL

VVH4

VVHL

VVH

VVL

VVLH

VVLL

VVL4

Drive Clock Waveform Conditions

(1) Readout clock waveform

(2) Vertical transfer clock waveform

II II

100%

90%

10%

0%

VVT

tr twh tf

φM

0V

φM

2