Sony HSR-1 Service manual

DIGITAL SUR VEILLANCE RECORDER

HSR-1/1P HSR-2/2P

INPUT BOARD

HSRA-11

SERVICE MANUAL

Volume 2 1st Edition (Revised 1)

HSR-1/1P HSR-2/2P (J, UC, CE) J, E 9-955-170-22

Printed in Japan

Sony Corporation 2000. 6 16

! W ARNING

This manual is intended for qualified service personnel only. To reduce the risk of electric shock, fire or injury, do not perform any servicing other than that contained in the operating instructions unless you are qualified to do so. Refer all servicing to qualified service personnel.

! W ARNUNG

Die Anleitung ist nur für qualifiziertes Fachpersonal bestimmt. Alle Wartungsarbeiten dürfen nur von qualifiziertem Fachpersonal ausgeführt werden. Um die Gefahr eines elektrischen Schlages, Feuergefahr und Verletzungen zu vermeiden, sind bei Wartungsarbeiten strikt die Angaben in der Anleitung zu befolgen. Andere als die angegeben Wartungsarbeiten dürfen nur von Personen ausgeführt werden, die eine spezielle Befähigung dazu besitzen.

! A VERTISSEMENT

Ce manual est destiné uniquement aux personnes compétentes en charge de l’entretien. Afin de réduire les risques de décharge électrique, d’incendie ou de blessure n’effectuer que les réparations indiquées dans le mode d’emploi à moins d’être qualifié pour en effectuer d’autres. Pour toute réparation faire appel à une personne compétente uniquement.

HSR-1/1P HSR-2/2P

MANUAL STRUCTURE

This manual is the Service Manual Vol. 2 of the digital surveillance recorder HSR-1/ 1P/2/2P and the option board Input Board HSRA-11. This manual contains the semiconductor pin assignments, parts lists, block diagrams, board layouts and schematic diagrams.

In addition to this Service Manual Vol. 2, the following manuals are provided.

..

. Operating Instructions

..

HSR-1/1P/2/2P (Supplied with equipment)

Parts number : 3-204-007-1X (English, for UC,CE)

3-204-007-2X (French, for UC,CE) 3-204-007-3X (German, for CE)

HSRA-11 (Supplied with Model HSRA-11)

Part number : 3-865-701-0X

: EXTERNAL LC RESONATOR : 13.5 MHz OSCILLATOR : REFERENCE FRAME PULSE FOR THE INDI MODE : REFERENCE FRAME PULSE FOR THE LINE & CAMERA MODE : FRAME PULSE FOR THE AFC : FRAME LOCKED 13.5 MHz CLOCK : FRAME LOCKED 13.5 MHz DIRECT OR 1/2 SELECT : PILOT REFERENCE : PILOT REFERENCE FEEDBACK : DATA TRANSFER CLOCK : CHIP SELECT : SERIAL DATA : POWER SAVE : RESET : HORIZONTAL LOCKED CLOCK (13.5 kHz) : DATA TRANSFER CLOCK : CHIP SELECT : SERIAL DATA : TRCK BUFFER FOR THE TCK5 & 6 : TRCK BUFFER FOR THE TCK1 - 4 : EXTERNAL LC RESONATOR : EXTARNAL LC RESONATOR DIRECT OR 1/2 SELECT : EXTERNAL PLL REFERENCE FOR THE TRCK PLL : TRCK PILOT FEEDBACK : TR CLOCK : VERTICAL PULSE FOR THE AFC : 13.5MHz EXTERNAL CRYSTAL OSCILLATOR

: STATUS (L = LINE, H = CAM) : DRUM REFERENCE PROTECTION : EXTERNAL LC RESONATOR : STATUS (L = INT, H = EXT) : FRAME PULSE FOR THE BLK-C DATA IN PB MODE : FRAME PULSE FOR THE BLK-Y DATA IN PB MODE : FRAME PULSE FOR THE RECORDING AUDIO : FRAME PULSE FOR THE MECHANICAL & SPEED CONTROLLERS : FRAME PULSE FOR THE DESHUFFLE MEMORY : FRAME PULSE FOR THE BLK-MEMORY : EXTERNAL CRYSTAL OSCILLTOR BUFFERED OUTPUT : CHARGE PUMP OUTPUT FOR THE IDCK PLL : IDCK PLL OSCILLATOR : PILOT REFERENCE SIGNAL FOR THE IDCK PLL : PILOT FEEDBACK SIGNAL : SERIAL DATA FOR THE MODE CONTROLLER : STATUS (L = NTSC, H = PAL) : JSG HORIZONTAL PULSE IN PLAYBACK MODE : JSG ODD/EVEN IN PLAYBACK MODE : SERIAL DATA FOR THE SPEED CONTROLLER : TRCK CLOCK BUFFERS : EXTERNAL LC RESONATOR FOR THE TRCK PLL : TRCK PLL OSCILLATOR : CHARGE PUMP FOR THE TRCK PLL : PILOT FEEDBACK SIGNAL FOR THE TRCK PLL : EXTERNAL PLL REFERENCE SIGNAL FOR THE TRCK PLL : REFERENCE PULSE FOR THE FRAME PLL : TRACK PULSE FOR THE MECHANICAL & SPEED CONTROLLERS : TRACK PULSE FOR THE DESHUFFLE MEMORY : FRAME PLL FEEDBACK PULSE (FOR OPERATION CHECK) : STATUS : STATUS : STATUS : 13.5 MHz EXTERNAL CRYSTAL OSCILLATOR

V

DD

TPVO

GND

TPVI

SPCK

DPRO

RST

FOE

FLBY

FLBC

FLTV

TRCK

DD

V

GND

IPRO

GND

IPRI

GND

DD

GND

V

101112131415161718192021222324

IPVI

IPVO

IOSS

IDCK

TCK1

IOSX

TCK2

GND

EX-LC2

FLTA

FLTT

TRKT

GND

GNDNCNCNCNC

IPCO

EX-LC1

TCK3

TCK4

GND

V

DD

GND

IC

DD

50

V

FLTD

49

TRKD

48

FLTE

47 46

TCK5

45

TCK6

44 43

SP-SD OUT

42

SP-SD IN

41

SP-CK

40

SP-CS

39

P-SAVE

38 37

DD

V

36

TOSS

35

TPCO

34 33

TOSI

32

TOSO

31 30

TOSX

29

TCKI

28

TCKE

27 26

25

PIN NO.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

I/O SIGNAL

— —

I I I

L 525MODE/SIN

I

AADD1/SOT

O O O O O

I

O

I I I I I

I — —

I

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

— —

I/O I/O

I

L CDMARQ

O

TESTMODE

I O

I — —

GND GND SCK AMC SMC

DD

AA

DD

AA

L CS0 L CS1

TDI TDO TCK TMS

L TRST BUNRI

TEST

NTEST1

GND

CC

V

NTEST2

L SYSRST

L CIARST

H BACKUP

CDATA15 CDATA14 CDATA13 CDATA12 CDATA11 CDATA10

CDATA9 CDATA8 CDATA7 CDATA6 CDATA5 CDATA4 CDATA3 CDATA2

CC

V GND

CDATA1 CDATA0 CPUCLK

L CWR L CRD L CCS1 L CCS0 CADD3 CADD2 CADD1 CADD0

L CPUDMA

CDMACK

L SINDIOE

STRCK

GND GND

I/O SIGNAL

NO.

61

—

62

I

63

I

64

O

65

I

66

I

67

I

68

0

I/O

69

2

I/O

70

I/O

71

I/O

72

I/O

73

—

74

—

75

I/O

76

I/O

77

I/O

78

I/O

79

I/O

80

—

81

—

82

I/O

83

I/O

84

I/O

85

I/O

86

I/O

87

I/O

88

—

89

I

90

O

91

O

92

O

93

O

94

O

95

O

96

O

97

O

98

O

99

O

100

—

101

—

102

O

103

O

104

O

105

O

106

O

107

—

108

O

109

O

110

O

111

O

112

—

113

—

114

O

115

O

116

O

117

O

118

O

119

O

120

—

V

CC

SFTLTT STRKT

SFLTE

SIENPA

SIOEC

SIENPV SIDATA15 SIDATA14 SIDATA13 SIDATA12 SIDATA11

GND

CC

V

SIDATA10

SIDATA9 SIDATA8 SIDATA7 SIDATA6

GND

CC

V SIDATA5 SIDATA4 SIDATA3 SIDATA2 SIDATA1 SIDATA0

GND

BK CLK L PMCS7 L PMCS6 L PMCS5 L PMCS4 L PMCS3 L PMCS2 L PMCS1 L PMCS0 PMADD4 PMADD3

CC

V

GND PMADD5 PMADD2 PMADD6 PMADD1 PMADD7

GND PMADD0 PMADD8

PMADD10

PMADD9

GND

CC

V PMADD12 PMADD11 PMADD13

L PMRAS L DMCKE L PMCAS

CC

V

PIN NO.

121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180

I/O SIGNAL

—

GND

—

GND

O

L DMDQM

O

L PMWE

—

GND

I/O

PMDATA8

I/O

PMDATA7

I/O

PMDATA9

I/O

PMDATA6

I/O

PMDATA10

—

GND

CC

—

V

PMDATA5

I/O

PMDATA11

I/O

PMDATA4

I/O

PMDATA12

I/O

PMDATA3

I/O

PMDATA13

I/O

GND

—

CC

V

—

PMDATA2

I/O

PMDATA14

I/O

PMDATA1

I/O

PMDATA15

I/O

PMDATA0

I/O

GND

—

DMCLK

O

L SMCS1

O

L SMCS0

O

SMADD4

O

SMADD3

O

SMADD5

O

SMADD2

O

SMADD6

O

SMADD1

O

SMADD7

O

SMADD0

O

SMADD8

O

SMADD10

O

CC

V

—

GND

—

SMADD9

O

SMADD12

O

SMADD11

O

SMADD13

O

L SMRAS

O

L SMCAS

O

L SMWE

O

GND

—

SMDATA8

I/O

SMDATA7

I/O

SMDATA9

I/O

SMDATA6

I/O

SMDATA10

I/O

SMDATA5

I/O

SMDATA11

I/O

SMDATA4

I/O

SMDATA12

I/O

GND

—

GND

—

PIN NO.

181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240

I/O SIGNAL

—

V

CC

I/O

SMDATA3

I/O

SMDATA13

I/O

SMDATA2

I/O

SMDATA14

I/O

SMDATA1

I/O

SMDATA15

I/O

SMDATA0

I

FRREF

O

LINK IOEC

I

PTRCK

I

PFLTT

I

PTRKT

O

PIENPA

O

SAV IOEC

O

PIENPV

I/O

PIDATA15

I/O

PIDATA14

I/O

PIDATA13

—

GND

—

CC

V

I/O

PIDATA12

I/O

PIDATA11

I/O

PIDATA10

I/O

PIDATA9

I/O

PIDATA8

I/O

PIDATA7

I/O

PIDATA6

I/O

PIDATA5

—

GND

I/O

PIDATA4

I/O

PIDATA3

I/O

PIDATA2

I/O

PIDATA1

I/O

PIDATA0

I/O

ADATA15

I/O

ADATA14

I/O

ADATA13

I/O

ADATA12

CC

—

V

—

GND

I/O

ADATA11

I/O

ADATA10

I/O

ADATA9

I/O

ADATA8

I/O

ADATA7

I/O

ADATA6

I/O

ADATA5

I/O

ADATA4

I/O

ADATA3

I/O

ADATA2

I/O

ADATA1

I/O

ADATA0

O

L HDDWR

O

L HDDRD

I

DMARQ

O

L DIOW

O

L DIOR

O

L DMACK

CC

—

V

7-5

IC

CXD3101R (SONY)

SIGNAL PROCESSOR

—TOP VIEW—

105

DD

110

115

120

125

130

135

140

144

PIN NO.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

V

GND

V

DD

GND

I/O SIGNAL —

O

O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O — —

I I/O I/O I/O I/O I/O

I

I —

I

O

I

DD

V

1

V

DD

REC CINV JSYC

JC0 JC1 JC2 JC3

GND

JC4 JC5 JC6 JC7

JSYY

JY0 JY1 JY2

DD

V

GND

SPCK

JY3 JY4 JY5 JY6

JY7 FLBKC FLBKY

JOOE

JFOE

GND BC1 TCK TD1

TENA1

TD0 VST

GND

5

PIN NO.

100

GND

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

10

I/O SIGNAL

I

BTRST I I I

O

I I I

—

O

I I

— — — — — — —

I

— —

I I I

—

I

I/O I/O

— I/O I/O I/O I/O I/O I/O

95

15

BTCK BTMS

BTDI

BTDO

XCS XSCK SPSO

GND

SPSI XRST

XPS

NC NC NC NC

NC V GND

TRCK

NC

NC TSI2 TSI1 TSI0 V

FLTV BKD7 BKD6

GND

BKD5 BKD4 BKD3 BKD2 BKD1 BKD0

90

58

80

75

GND

DD

V

GND

DD

V

GND

V

DD

NC NC

GND

V

DD

NC NC NC NC NC

GND

DD

GND

V

20

25

30 GND

35

I/O SIGNAL

NO.

73

—

74

I/O

75

I/O

76

I/O

77

I/O

78

I/O

79

I/O

80

I/O

81

—

82

I/O

83

I/O

84

O

85

O

86

O

87

O

88

O

89

O

90

DD

—

91

—

92

O

93

O

94

O

95

O

96

O

97

O

98

O

99

O

100

I/O

101

I/O

102

—

103

O

104

O

105

O

106

O

107

O

108

O

DD

V

BUP B2D10 B2D11 B2D12 B2D13 B2D14 B2D15

GND B2D16 B2D17

WCK2

B2WS B2WA0 B2WA1 B2WA2 B2WA3

DD

V

GND

B2WFS

B2RFS B2RA3 B2RA2 B2RA1 B2RA0

B2RS

RCK2

B2D07 B2D06

GND B2D05 B2D04 B2D03 B2D02 B2D01 B2D00

NO. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

I/O SIGNAL —

V

DD

I/O

B1D10

I/O

B1D11

I/O

B1D12

I/O

B1D13

I/O

B1D14

I/O

B1D15

I/O

B1D16

—

GND

I/O

B1D17

O

WCK1

O

B1WS

O

B1WA0

O

B1WA1

O

B1WA2

O

B1WA3

O

B1WFS

—

DD

V

—

GND

O

B1RFS

O

B1RA3

O

B1RA2

O

B1RA1

O

B1RA0

O

B1RS

O

RCK1

I/O

B1D07

I/O

B1D06

I/O

B1D05

—

GND

I/O

B1D04

I/O

B1D03

I/O

B1D02

I/O

B1D01

I/O

B1D00

I

SD

INPUT

BC1 BTCK BTD1 BTMS

70

BTRST FLBKC FLBKY FLTV

65

JFOE JOOE SD

60

SPCK SPSO TCK TD1

55

TENA1 TRCK TSI0 - TSI2

50

VST XCS XPS XRST

45

XSCK

OUTPUT

40

BTD0 BIRA0 - BIRA3/B2RA0 - B2RA3 B1RFS/B2RFS B1RS/B2RS B1WA0 - B1WA3/B2WA0 - B2WA3 B1WFS/B2WFS B1WS/B2WS CINV RCK1/RCK2 REC SPSI TD0 WCK1/WCK2

INPUT/OUTPUT

B1D00 - B1D07/B2D00 - B2D07 B1D10 - B1D17/B2D10 - B2D17 BKD0 - BKD7 BUP JC0 - JC7 JY0 - JY7 JSYC JSYY

; CROSS CHECK BIT : JTAG CK : JTAG DI : JTAG MS : JTAG RST : CHROMA PLAYBACK REFERENCE SIGNAL : Y PLAYBACK REFERENCE SIGNAL : FIELD REFERENCE SIGNAL : FORCED ODD/EVEN : ORIGINAL ODD/EVEN : HIGH : SD LOW : HD : 13.5 MHz CLOCK : SERIAL DATA : CROSS CHECK CLOCK : CROSS CHECK DATA : CROSS CHECK TEST : 18.1 MHZ CLOCK : TEST : CROSS CHECK GROUND : CHIP SELECT : POWER SAVE : RESET : SERIAL CLOCK

: JTAG DO : BRAM1/BRAM2 READ ADDRESS : BRAM1/BRAM2 READ FIELD SELECT : BRAM1/BRAM2 READ STROBE : BRAM1/BRAM2 WRITE ADDRESS : BRAM1/BRAM2 WRITE FIELD SELECT : BRAM1/BRAM2 WRITE STROBE : CHROMA LINE SEQUENTIAL : BRAM1/BRAM2 READ CLOCK : HIGH : REC, LOW : PB : SERIAL DATA : CROSS CHECK DATA : BRAM1/BRAM2 WRITE CLOCK

: BRAM1/BRAM2 PORT0 DATA : BRAM1/BRAM2 PORT1 DATA : BK DATA : BUP : CHROMA DATA : Y DATA : CHROMA SYNC : Y SYNC

CXD8525N-E2 (SONY)

4-LINE SERIAL/IIC BUS CONVERTER

—TOP VIEW—

CSB

DTS

DTM

SCKB

BUSY

RSTB

MODE2

EXCLK

OSC2

1

2

3

4

5

6

7

8

9

GND

10

20

V

DD

SDA

19

SCL

18

TEST4

17

TEST3

16

TEST2

15

TEST1

14

TEST0

13

MODE1

12

MODE0

11

9

8

CSB SCKB DTS RSTB MODE0 MODE1 MODE2 TEST0 TEST1 TEST2 TEST3

OSC2EXCLK

18

SCL

19

SDA

3

DTM

5

BUSY

17

TEST4

1 4 2

6 11 12

7 13 14 15 16

7-6

HSR-1/1P HSR-2/2P

CXD8608R (SONY)

C-MOS DIGITAL ENCODE/DECODE

—TOP VIEW—

75747372717069686766656463626160595857565554535251

NC

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

PIN NO.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

GND

DDS

V

GND

DD

V

DD

V

123456789

I/O SIGNAL

I

TMODE

I

SD

DD

—

V

RTST

I

FERR

O

GND

—

PH1

I

HRED

I

SRED

I

RMTH2

I

RMTH1

I

RMTH0

I

PMTH1

I

PMTH0

I

GND

—

IMA

I

ATH1

I

ATH0

I

RMOD

I

DIG

I

FSTA

I

GND

—

NC

—

NC

—

NC

—

PIN NO.

GND

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

GND

101112131415161718192021222324

RDT

DORZ

V

DD

TDON

DRET EACT0 EACT1 EASEL EQNM0 EQNM1 EQNM2 EQNM3 EQSEL

TBP

GND TDT0 TDT1 TDT2 TDT3 TDT4 TDT5 TDT6 TDT7 TDT8 TDT9

NO.

51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

I/O SIGNAL —

— — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O

O

— — —

I/O SIGNAL

O

I

—

I I I I I I I I I I

I/O

— I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

IC

INPUT

ATH1, ATH0

DD

V

GND

DD

V

GNDNCNC

NC

25

I/O SIGNAL

NO.

GND

76

I

GND

V

DD

DDT0 DDT1 DDT2 DDT3 DDT4 DDT5 DDT6 DDT7 DDT8 DDT9

DDT10

GND DDT11 DDT12 DDT13 DDT14 DDT15

DOBUP

I

DIBUP

GND

NC NC

100

TRCK

77

I

CIBUP

78

—

V 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

DDS

I

TTCK

—

GND

I/O

VDT7

I/O

VDT6

I/O

VDT5

I/O

VDT4

I/O

VDT3

I/O

VDT2

I/O

VDT1

I/O

VDT0

I/O

VBUP

—

GND

DD

—

V

I

RST

I

PS

REC

I

TRST

I

TCK

I

TMS

I

TDO

O

TDI

I

SMODE

I

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

CIBUP DIBUP DIG DORZ DRET EACT0, EACT1 EASEL EQNM0 - EQNM3 EQSEL FSTA HRED IMA PH1 PMTH0, PMTH1

PS

REC RMOD RMTH0 - RMTH2

RST

RTST SD SMODE SRED TCK TDI TDON TMODE TMS TRCK TRST TTCK

OUTPUT

DOBUP FERR RDT TDO

INPUT/OUTPUT

DDT0 - DDT15 TBP TDT0 - TDT9 VBUP VDT0 - VDT7

: ACTIVITY THRESHOLD : PB BUP : BUP : DIGEST MODE : TEST DATA SELECT : DCT RETURN : EXTERNAL ACTIVITY : EXTERNAL ACTIVITY ENABLE : EXTERNAL Q-NUMBER : EXTERNAL Q-NUMBER ENABLE : 3-PASS CUT MODE : RED DETECT (HD) : IMPACT : PHASE-1 COMPATIBLE MODE : PB MOTION THRESHOLD : POWER SAVE : REC/PB SELECT (H : REC, L : PB) : ROUND MODE : REC MOTION THRESHOLD : SYSTEM RESET : RAM TEST : MODE SETTING : FOR TEST : RED DETECT (SD) : JTAG CLOCK : JTAG DATA : TEST DATA OUTPUT ON : FOR TEST : JTAG MODE SET : CLOCK (18 MHz) : JTAG RESET : CLOCK (HD : 24 MHz, SD : 18 MHz)

: BUP : FRAMING ERROR : RED DETECT FLAG : JTAG DATA

: DATA (D1/SFY SIDE) : TEST DATA BUP : TEST DATA : BUP (V1 SIDE) : DATA (V1 SIDE)

HSR-1/1P HSR-2/2P

7-7

IC

CXD8804Q (SONY)

C-MOS 8-MPU COMMUNICATION CONTROLLER WITH PARALLEL PORT

—TOP VIEW—

8079787776757473727170696867666564636261605958575655545352

81 82 83 84 85 86 87 88 89 90

GND

91

DD

V 92 93 94 95 96 97 98 99

100

I/O SIGNAL

NO.

O

1

O

2

O

3

O

4

O

5

O

6

O

7

O

8

I

9

I

10

I

11

O

12

O

13

O

14

—

15

O

16

O

17

O

18

O

19

O

20

O

21

O

22

O

23

—

24

O

25

H SNC

S RDY

S RESP

MPUIF CS

P ON PST

SYSTEM CK

CPU CK

CPU WR

CPU RD

A0CPU - A12CPU

D0CPU - D7CPU

123456789

I/O I/O I/O

NO. OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20

INT H SNC S RDY

S RESP

SCK

SCMD

STRB

GND MPUCS7 MPUCS6 MPUCS5 MPUCS4 MPUCS3 MPUCS2 MPUCS1 MPUCS0

N.C

H SYNC

9 10 11

55

34 35 36

53 54

37 - 39, 42 - 51

57 - 64

O

26

I

27

I

28

I

29

I

30

I

31

O

32

I

33

I

34

I

35

I

36

I

37

I

38

I

39

—

40

—

41

I

42

I

43

I

44

I

45

I

46

I

47

I

48

I

49

I

50

TRANSMITTER

P S

CONVERTER

DATA/ADDRESS

CONTROL

101112131415161718192021222324252627282930

SIGNAL SIGNAL SIGNAL

V SYNC

VSNC LEN

HV CLK

S PULS IN

S PULS OUT

P ON RST

SYSTEM CK

CPU CK A12 CPU A11 CPU A10 CPU

A9 CPU A8 CPU A7 CPU A6 CPU A5 CPU A4 CPU A3 CPU A2 CPU A1 CPU

BUS

HD VD

TES 1

GND

V

GND

NO.

I

A0 CPU

51

O

16 - 23

77 - 89

69 - 76

12 13 14

52

65 67 68

I

CPU WR

I

CPU RD

I

MPUIF CS

I

CONT CS

I/O

D7 CPU

I/O

D6 CPU

I/O

D5 CPU

I/O

D4 CPU

I/O

D3 CPU

I/O

D2 CPU

I/O

D1 CPU

I/O

D0 CPU

O

RAM WR

—

O

RAM OE

O

RAMCE

I/O

D7 RAM

I/O

D6 RAM

I/O

D5 RAM

I/O

D4 RAM

I/O

D3 RAM

I/O

D2 RAM

I/O

D1 RAM

MPUCS0 - MPUCS7

8

INT SCK SCMD STRB

WAIT

RAMWR RAMOE RAMCE

A0RAM - A12RAM

D0RAM - D7RAM

WAIT

GND

52 53 54 55 56 57 58 59 60 61 62 63 64 65

DD

66 67 68 69 70 71 72 73 74 75

PIN NO.

NC

I/O

76

O

77

O

78

O

79

O

80

O

81

O

82

O

83

O

84

O

85

O

86

O

87

O

88

O

89

—

90

—

91

I

92

I

93

I

94

I

95

I

96

I

97

I

98

I

99

O

100

D0 RAM A12 RAM A11 RAM A10 RAM

A9 RAM

A8 RAM

A7 RAM

A6 RAM

A5 RAM

A4 RAM

A3 RAM

A2 RAM

A1 RAM

A0 RAM

GND

DD

V INP 07 INP 06 INP 05 INP 04 INP 03 INP 02 INP 01 INP 00

OUT 27

V

GND

51

55

MPUIF CS

54

CPU RD

53

50

CPU WR

49

51

48

A0CPU

50

47

A1CPU

49

46

A2CPU

48

45

A3CPU

47

44

A4CPU

46

43

A5CPU

45

42

A6CPU

44

41

DD

A7CPU

43

40

A8CPU

42

39

A9CPU

39

38

A10CPU

38

37

A11CPU

37

36

A12CPU

35

64

34

D0CPU

63

33

D1CPU

62

32

D2CPU

31

61

D3CPU

60

D4CPU

59

D5CPU

58

D6CPU

57

D7CPU

34

P ON RST

35

SYSTEM CK

36

CPU CK

9

H SNC

10

S RDY

11

S RESP

56

CONT CS

31

S PULS IN

99

INP 00

98

INP 01

97

INP 02

96

INP 03

95

INP 04

94

INP 05

93

INP 06

92

INP 07

30

VD

29

HD

28

HV CLK

27

VSNC LEN

33

TES 1

WAIT

RAM WR

RAM OE RAM CE

A0RAM A1RAM A2RAM A3RAM A4RAM A5RAM A6RAM A7RAM A8RAM

A9RAM A10RAM A11RAM A12RAM

D0RAM

D1RAM

D2RAM

D3RAM

D4RAM

D5RAM

D6RAM

D7RAM

MPUCS0 MPUCS1 MPUCS2 MPUCS3 MPUCS4 MPUCS5 MPUCS6 MPUCS7

SCMD

STRB

S PULS OUT

OUT 20

OUT 21

OUT 22

OUT 23

OUT 24

OUT 25

OUT 26

OUT 27

H SYNC

V SYNC

INT

SCK

52

65 67 68 89 88 87 86 85 84 83 82 81 80 79 78 77

76 75 74 73 72 71 70 69

23 22 21 20 19 18 17 16

8 12 13 14

32

7

6

5

4

3

2

1

100

25 26

INPUT

A0CPU - A12CPU CONT CS CPU CK CPU RD CPU WR HD H SNC HV CLK INP 00 - 07 MPUIF CS P ON RST S PULS S RDY S RESP SYSTEM CK TES 1 VD VSNC LEN

OUTPUT

A0RAM - A12RAM H SYNC INT MPUCS0 - MPUCS7 OUT 20 - 27 RAM CE RAM OE RAM WR SCK SCMD S PULS STRB V SYNC WAIT

INPUT/OUTPUT

D0CPU - D7CPU D0RAM - D7RAM

; CPU ADDRESS BUS ; INTERNAL/PARALLEL PORT ; CPU CLOCK ; CPU READ STROBE ; CPU WRITE STROBE ; VIDEO HORIZONTAL SYNCHRONIZING PULSE ; SERIAL RECEIVE WAIT ; VIDEO VERTICAL SAMPLING PULSE (13.5 MHz) ; PARALLEL PORT ; EXTERNAL RAM CHIP SELECT ; POWER IN RESET (L) ; MEDIOCRITY CLOCK PULSE ; SERIAL TRANSMISSION LEADY ; SERIAL RECEIVE DATA ; SYSTEM CLOCK ; TEST (L) ; VIDEO VERTICAL SYNCHRONIZING PULSE ; VIDEO VERTICAL SYNCHRONIZING PULSE OUTPUT WIDTH CONTROL

; EXTERNAL RAM ADDRESS BUS ; VIDEO HORIZONTAL SYNCHRONIZING PULSE ; SERIAL RECEIVE END ; SERIAL CORRESPONDENCE ENABLE ; PARALLEL PORT ; EXTERNAL RAM CHIP SELECT ; EXTERNAL RAM OUTPUT ENABLE ; EXTERNAL RAM WRITE STROBE ; SERIAL CORRESPONDENCE CLOCK ; SERIAL TRANSMISSION DATA ; MEDIOCRITY CLOCK PULSE FREQUENCY (1/2-1/27) ; SERIAL TRANSMISSION STROBE ; VIDEO VERTICAL SYNCHRONIZING PULSE ; CPU WAIT

; CPU DATA BUS ; EXTERNAL RAM DATA BUS

INP 00 - INP 07

S PULS IN

VSNC LEN

7-8

CONT CS

TES 1

HV CLK

92 - 99

56

37

33

29

HD

30

VD

27 28

PARALLEL PORT

CLOCK

PRESCALER

SYNC

GENERATOR

1 - 7, 100

32

25 26

OUT20 - OUT27

S PULS OUT

H SYNC V SYNC

HSR-1/1P HSR-2/2P

CXD9089R (NEC) CY62256-70SNC-T2 (CYPRESS)

SRAM CONTROL, INDI BUS I/F

—TOP VIEW—

156

155 150

157

160

165

170

175

180

185

190

195

200

205

208

145

140

135

130

125

120

115

110

105

104

100

95

90

85

80

75

70

65

60

55 53

C-MOS 256 K (32 K x 8)-BIT SRAM

—TOP VIEW—

A5

I/O0

I/O1

I/O2

A10

A11

A12

A13

A14

1

A6

2

A7

3

A8

4

A9

5

6

7

8

9

10

11

12

13

14

GND

28

V

DD

27

WE

A4

26

A3

25

A2

24

A1

23

22

OE

A0

21

20

CE

I/O7

19

I/O6

18

I/O5

17

I/O4

16

I/O3

15

21 23 24 25 26

1 2 3 4 5 6 7 8 9

10

20 22 27

INPUT

A0 - A14

CE OE WE

OUTPUT

I/O0 - I/O7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14

CE OE WE

: ADDRESS : CHIP ENABLE : OUTPUT ENABLE : WRITE ENABLE

: DATA

IC

11

I/O0

12

I/O1

13

I/O2

15

I/O3

16

I/O4

17

I/O5

18

I/O6

19

I/O7

PIN NO.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

1

5

I/O SIGNAL

—

GND

—

GND

—

NC

I

L PB

I

SMC

I

SIN

O

SOT

I

SCK

I

AMC

—

GND

I

TDI

O

TDO

I

TCK

I

TMS

I

L TRST

—

GND

I

BUNRI

I

TEST

I

NTEST1

I

NTEST2

—

NC

—

NC

—

NC

—

NC

I

TEST P

—

GND

CC

—

V

MODE

I

NC

—

L RES

I

GND

—

CDATA15

I/O

CDATA14

I/O

CDATA13

I/O

CDATA12

I/O

CDATA11

I/O

CDATA10

I/O

CDATA9

I/O

CDATA8

I/O

NC

—

CDATA7

I/O

CDATA6

I/O

CDATA5

I/O

CDATA4

I/O

CDATA3

I/O

CDATA2

I/O

CDATA1

I/O

CDATA0

I/O

GND

—

NC

—

GND

—

GND

—

10

PIN NO.

100 101 102 103 104

15

53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

20

I/O SIGNAL

V

CC

—

NC

—

GND

—

CPUCLK

I

GND

—

NC

—

L CWRH

I

L CWRL

I

L CRD

I

L CCS

I

NC

—

CADD17

I

CADD16

I

CADD15

I

CADD14

I

CADD13

I

CADD12

I

CADD11

I

CADD10

I

CADD9

I

CADD8

I

CADD7

I

CADD6

I

CADD5

I

CADD4

I

CC

V

—

GND

—

CADD3

I

CADD2

I

CADD1

I

CADD0

I

GND

—

M1ADD16

O

M1ADD15

O

M1ADD14

O

M1ADD13

O

M1ADD12

O

M1ADD11

O

M1ADD10

O

M1ADD9

O

M1ADD8

O

NC

—

M1ADD7

O

M1ADD6

O

M1ADD5

O

M1ADD4

O

M1ADD3

O

M1ADD2

O

M1ADD1

O

M1ADD0

O

NC

—

CC

V

—

25

30

35

PIN NO.

105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156

40 45 50

I/O SIGNAL

—

GND

—

GND

—

NC

O

L M1WRL

O

L M1WRH

O

L M1RD

O

L M1CS

—

GND

I/O

M1DATA15

I/O

M1DATA14

I/O

M1DATA13

I/O

M1DATA12

I/O

M1DATA11

I/O

M1DATA10

I/O

M1DATA9

I/O

M1DATA8

—

NC

I/O

M1DATA7

I/O

M1DATA6

I/O

M1DATA5

I/O

M1DATA4

I/O

M1DATA3

I/O

M1DATA2

I/O

M1DATA1

I/O

M1DATA0

CC

—

V

GND

—

M0ADD16

O

M0ADD15

O

M0ADD14

O

M0ADD13

O

M0ADD12

O

M0ADD11

O

M0ADD10

O

M0ADD9

O

M0ADD8

O

NC

—

M0ADD7

O

M0ADD6

O

M0ADD5

O

M0ADD4

O

M0ADD3

O

M0ADD2

O

M0ADD1

O

M0ADD0

O

L M0WRL

O

L M0WRH

O

L M0RD

O

L M0CS

O

NC

—

GND

—

GND

—

PIN NO.

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

52

I/O

SIGNAL

—

V

CC

NC

—

M0DATA15

I/O

M0DATA14

I/O

M0DATA13

I/O

M0DATA12

I/O

M0DATA11

I/O

M0DATA10

I/O

M0DATA9

I/O

M0DATA8

I/O

NC

—

M0DATA7

I/O

M0DATA6

I/O

M0DATA5

I/O

M0DATA4

I/O

M0DATA3

I/O

M0DATA2

I/O

M0DATA1

I/O

M0DATA0

I/O

GND

—

IDATA0

I/O

IDATA1

I/O

IDATA2

I/O

IDATA3

I/O

IDATA4

I/O

GND

—

CC

V

—

IDATA5

I/O

IDATA6

I/O

IDATA7

I/O

IDATA8

I/O

IDATA9

I/O

IDATA10

I/O

IDATA11

I/O

IDATA12

I/O

IDATA13

I/O

IDATA14

I/O

IDATA15

I/O

GND

—

IENPV

I

IOEC

I

IENPA

I

TRKT

I

FLTT

I

GND

—

TRCK

I

GND

—

L INDIOE

I

RBUP

I

PBUP

O

NC

—

CC

V

—

NO.

1 2 3 4 5 6 7

A10

A9 A8 A7 A6 A5 A4 A3 A2

CE

WE

OE

I/O SIGNAL

I I I I I I I

6 5 4 3 2 1 26 25 24

20 27

22

A5 A6 A7 A8

A9 A10 A11

ROW DECODER

I/O SIGNAL

NO.

8

I

9

I

10

I

11

I/O

12

I/O

13

I/O

14

—

INPUT BUFFER

512 x 512

COLUMN DECODER

1098723

A14

ARRAY

A13

A12 A13 A14 I/O0 I/O1 I/O2

GND

I/O SIGNAL

NO.

15

I/O

16

I/O

17

I/O

18

I/O

19

I/O

20

I

21

I

SENSE AMPS

POWER

DOWN

21

A1

A0

A12

A11

I/O3 I/O4 I/O5 I/O6 I/O7

I/O SIGNAL

NO.

22

I

OE

23 24 25 26 27

CE

A0

28

A1

I

A2

I

A3

I

A4

I I

WE

—

V

DD

11

I/O0

12

I/O1

13

I/O2

15

I/O3

16

I/O4

17

I/O5

18

I/O6

19

I/O7

HSR-1/1P HSR-2/2P

7-9

IC

EPF10K50RC240-3 (ALTERA) EPF10K50VRC240-3 (ALTERA)

C-MOS EMBEDDED PROGRAMMABLE LOGIC DEVICE

—TOP VIEW—

180

175

170

165

181

185

190

195

200

205

210

215

220

225

230

235

240

PIN NO.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

GND

V

DD

GND

V

DD

GND

V

DD

GND



VDDGND

1

5

I/O SIGNAL

I

TCK

I/O

CONF DONE

I

CEO

O

TDO

—

V

I/O

—

GND

I/O

CLKUSR, I/O

I/O

—

V

I/O

—

GND

I/O

RDY/

BSY

I/O

INIT DONE, I/O

—

V

I/O

—

GND

I/O

—

V

I/O

—

GND

I/O

—

V

I/O

GND

—

I/O

V

—

TMS

I

O

TRST

O

STATUS

160 155 150

DD

V

10

DD

, I/O

DD

PIN NO.

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120

GND

VDDGND

15

DD

V

20

I/O SIGNAL

I/O

—

GND

I/O

—

DD

V

I/O

—

GND

I/O

—

DD

V

I/O

IN, I/O

I/O

CLK, I/O

I/O

IN, I/O

—

GND

I/O

—

DD

V

I/O

—

GND

I/O

—

DD

V

I/O

GND

25

DD

V

VDDGND

30

PIN NO.

121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180

145

GND

VDDGND

35

I/O SIGNAL

I

—

I

I — I/O I/O I/O I/O — I/O I/O I/O I/O — I/O I/O I/O I/O — I/O I/O I/O I/O — I/O I/O I/O I/O — I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O — I/O I/O I/O I/O I/O —

I

140

135

DD

V

GND

VDDGND

40 45 50

NO.

181

CONFIG

182

V

DD

183

MSEL1

184

MSEL0

185

GND

186

I/O

187

I/O

188

I/O

189

I/O

190

DD

V

191

I/O

192

I/O

193

I/O

194

I/O

195

GND

196

I/O

197

I/O

198

I/O

199

I/O

200

DD

V

201

I/O

202

I/O

203

I/O

204

I/O

205

GND

206

I/O

207

I/O

208

I/O

209

I/O

210

DD

V

211

I/O

212

I/O

213

I/O

214

I/O

215

GND

216

I/O

217

I/O

218

I/O

219

I/O

220

DD

V

221

I/O

222

I/O

223

I/O

224

I/O

225

GND

226

I/O

227

I/O

228

I/O

229

I/O

230

DD

V

231

I/O

232

I/O

233

I/O

234

I/O

235

I/O

236

GND

237

TDI

238

CE

DCLK

239

DATA0

240

130

125

DD

V

GND

55

I/O SIGNAL

I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O — I/O I/O I/O I/O I/O I/O I/O I/O

121

DD

V

DD

GND

V

DD

GND

V

DD

GND

V

DD

GND

DD

V

60

DATA1, I/O DATA2, I/O DATA3, I/O

I/O DATA4, I/O DATA5, I/O

I/O DATA6, I/O

V

DD

DATA7, I/O

I/O

GND

I/O

DD

V

I/O

DEV CLR

IN, I/O

CLK, I/O

IN, I/O

DEV OE, I/O

I/O

GND

I/O

DD

V

I/O

GND

I/O

, I/O

RS

I/O

, I/O

WS

CS, I/O

, I/O

CS

HM530281RTT-25 (HITACHI)

(331,776 WORD x 8)-BIT FRAME MEMORY

—TOP VIEW—

1

DI0

2

DI1

3

WE

CGW

WCK

WRS WLRS WCLR

WWND

WAS

WAD

MODE0 MODE1

TEST0

DI0 - 7

11

WE

DI2 DI3 DI4 DI5 DI6 DI7

IN

1 - 8

4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22

WCK

CGW

WRS

WAS

WAD

WLRS

WWND

WCLR

GND V

CC

32-WORD

WRITE DATA REG.

13

12

14

18

19

15

17

16

120

115

110

105

100

95

90

85

80

75

70

65

61

, I/O

GND

V

CC

32-WORD

x 8

WRITE DATA BUFFER

WRITE

COUNTER

44

DO0

43

DO1

42

DO2

41

DO3

40

DO4

39

DO5

38

DO6

37

DO7 36 35

IN

34

OE

CGR

33

RCK

32

RRS

31

RLRS

30

RCLR

29

RWND

28

RAS

27

RAD

26

TEST1

25

TEST2

24

TEST3

23

x 8

1152 DOT x 288 LINE x 8 1024 DOT x 324 LINE x 8

10368 DOT x 32WORD x 8

NOTE :

*

DI0

2

DI1

3

DI2

4

DI3

5

DI4

6

DI5

7

DI6

8

DI7

11

WE

13

WCK

12

CGW

14

WRS

18

WAS

19

WAD

15

IN

WLRS

17

WWND

IN

16

WCLR

IN

CGR

IN

CGW

IN

DI0 - DI7 DO0 - DO7

IN

MODE0 - MODE1

IN

OE

IN

RAD

RAS

IN

RCK

IN

RCLR RLRS RRS RWND

TEST0 - TEST3 WAD

WAS

WCK

WCLR WE WLRS WRS WWND

MEMORY ARRAY

MEMORY

CONTROLLER

REFRESH

COUNTER

Select for MODE PIN (20, 21)

44

DO0

43

DO1

42

DO2

41

DO3

40

DO4

39

DO5

38

DO6

37

DO7

34

OE

32

RCK

33

CGR

31

RRS

27

RAS

26

RAD

30

RLRS

28

RWND

29

RCLR

: READ CLOCK GATE : WRITE CLOCK GATE : DATA INPUTS : DATA OUTPUTS : MODE SELECT INPUTS : OUTPUT ENABLE INPUT : READ ADDRESS : READ ADDRESS SET : READ CLOCK INPUT : READ CLEAR : READ LINE RESET : READ RESET : READ WINDOW MODE : TEST INPUTS : WRITE ADDRESS : WRITE ADDRESS SET : WRITE CLOCK INPUT : WRITE CLEAR : WRITE ENABLE INPUT : WRITE LINE RESET : WRITE RESET : WRITE WINDOW MODE

32-WORD

x 8

READ DATA BUFFER

* * *

READ

COUNTER

READ DATA REG.

37 - 44

DO0 - 7

34

OE

32

RCK

33

CGR

31

RRS

27

RAS

26

RAD

30

RLRS

28

RWND

29

RCLR

7-10

HSR-1/1P HSR-2/2P

IC

A

B D

M

P R

W

A B C C C C

C

R R

W W W W W

HD64F7045F28 (HITACHI)

32-BIT MICROCOMPUTER

—TOP VIEW—

108

105 100

109 110

115

120

125

130

135

140

144

1

I/O

NO.

I/O

1

I/O

2

PE14/TIOC4C/DACK0/

I/O

3

I/O

4

I/O

5

PE15/TIOC4D/DACK1/

—

6

I/O

7

I/O

8

I/O

9

I/O

10

I/O

11

—

12

I/O

13

—

14

I/O

15

I/O

16

I/O

17

I/O

18

I/O

19

I/O

20

I/O

21

I/O

22

I/O

23

I/O

24

I/O

25

—

26

I/O

27

—

28

I/O

29

I/O

30

PA19/

I/O

31

PB2/

I/O

32

PB3/

I/O

33

PA18/

I/O

34

PB4/

IRQ2/POE2/CASH

—

35

I/O

36

PB5/

IRQ3/POE3

I/O

37

PB6/

I/O

38

PB7/

I/O

39

PB8/

—

40

I/O

41

PB9/

—

42

I/O

43

O

44

I/O

45

PD31/D31/

I/O

46

PD30/D30/

I/O

47

I/O

48

95

5

10

SIGNAL



PA23/

WRHH

PA22/



WRHL

PA21/



CASHH

IRQOUT

GND PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4

CC

V

PC5/A5

GND PC6/A6 PC7/A7 PC8/A8 PC9/A9

PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15

PB0/A16

CC

V

PB1/A17

GND

PA20/



CASHL

/DRAK1

BACK

IRQ0/POE0/RAS

IRQ1/POE1/CASL

/DRAK0

BREQ

GND



/RDWR

/A18/

BACK

IRQ4

/A19/

IRQ5

BREQ

/A20/

IRQ6

WAIT

VCC

/A21/

IRQ7

ADTRG

GND



PA14/



RD



WDTOVF

ADTRG

IRQOUT

PA13/

WRH

PA12/

WRL

90

85

807573

72 70

65

60

55

50

45

40

37

15

20

25

303536

PIN NO.

49 50



AH

51 52 53



54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79



80 81



82 83 84 85



86



87



88 89



90 91 92 93



94



95 96

I/O

I/O I/O I/O I/O I/O I/O

— I/O I/O I/O I/O I/O

— I/O

— I/O I/O I/O I/O I/O I/O I/O

— I/O I/O I/O I/O I/O

— I/O

— I/O I/O I/O I/O I/O

— I/O

— I/O I/O I/O I/O I/O

—

I I I

SIGNAL

PA11/

PA10/ PA9/TCLKD/ PA8/TCLKC/

PA7/TCLKB/ PA6/TCLKA/

GND PD29/D29/ PD28/D28/

PD27/D27/DACK1 PD26/D26/DACK0 PD25/D25/

GND

PD24/D24/

VCC PD23/D23/ PD22/D22/ PD21/D21/ PD20/D20/ PD19/D19/ PD18/D18/ PD17/D17/

GND

PD16/D16/

PD15/D15 PD14/D14 PD13/D13 PD12/D12

CC

V

PD11/D11

GND

PD10/D10

PD9/D9 PD8/D8 PD7/D7 PD6/D6

CC

V

PD5/D5

GND PD4/D4 PD3/D3 PD2/D2 PD1/D1 PD0/D0

GND

XTAL

MD3

EXTAL

CS1 CS0

CS3 CS2

DREQ1

DREQ0

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1

IRQ0



 IRQ3 IRQ2

CS3 CS2

I/O

I I

— I/O I/O

I

I — — —

I/O

I

I/O

PE0/TIOC0A/

I/O

PE1/TIOC0B/DRAK0

I/O

PE2/TIOC0C/

—

I/O

PE3/TIOC0D/DRAK1 I/O I/O I/O

—

I I I I I I

—

I

I — — —

I/O I/O I/O

PA2/SCK0/ I/O I/O

—

I/O

PA5/SCK1/ I/O I/O I/O

PE10/TIOC3C

I/O

—

PE11/TIOC3D

I/O

PE12/TIOC4A

I/O

PE13/TIOC4B/

I/O

SIGNAL

MD2 NMI V

CC

PA16/

AH

PA17/

WAIT

MD1 MD0

CC

PLLV

PLLCAP PLLGND PA15/CK



RES

VCC

PE4/TIOC1A PE5/TIOC1B PE6/TIOC2A

GND PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5

AGND PF6/AN6 PF7/AN7

REF

AV

AVCC

GND PA0/RXD0 PA1/TXD0

DREQ0/IRQ0

PA3/RXD1 PA4/TXD1

V

CC

DREQ1/IRQ1

PE7/TIOC2B PE8/TIOC3A PE9/TIOC3B

GND



DREQ0

DREQ1

MRES

NO.

97 98 99



100



101



102



103 104



105



106 107 108



109 110



111 112



113



114



115



116



117



118



119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144



INPUTS

DTRG

AN0 - AN7

REQ REQ0, DREQ1

EXTAL FWP

-

IRQ0

IRQ7

MD0 - MD3

RES

NMI PF0 - PF7

-

OE0

POE3

ES

RXD0, RXD1 TCLKA - TCLKD

AIT

XTAL

OUTPUTS

A0 - A21

H ACK ASH ASHH ASHL ASL

CK

-

S0

CS3

DACK0, DACK1 DRAK0, DRAK1

IRQOUT

AS D

RDWR TXD0, TXD1

DTOVF RH RHH RHL RL

INPUTS/OUTPUTS

D0 - D31 PA0 - PA23 PB0 - PB9 PC0 - PC15 PD0 - PD31 PE0 - PE15 SCK0, SCK1 TIOC0A - TIOC0D TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A - TIOC3D TIOC4A - TIOC4D

: A/D CONVERTER TRIGGER : ANALOG : BUS REQUEST : DMA TRANSFER REQUEST : CRYSTAL OSCILLATOR AND EXTERNAL CLOCK : FLASH MEMORY WRITE DISABLE : INTERRUPT REQUEST : MODE SELECT : MANUAL RESET : NON-MASKABLE INTERRUPT : PORT F : PORT OUTPUT ENABLE : POWER ON RESET : RECEIVE DATA : MTU TIMER CLOCK : WAIT : EXTERNAL CRYSTAL OSCILLATOR

: ADDRESS BUS : ADDRESS HOLD : BUS REQUEST ACKNOWLEDGE : HIGH COLUMN ADDRESS STROBE : HH COLUMN ADDRESS STROBE : HL COLUMN ADDRESS STROBE : LOW COLUMN ADDRESS STROBE : SYSTEM CLOCK : CHIP SELECT : DMA TRANSFER STROBE : DREQ ACKNOWLEDGE : INTERRUPT REQUEST : ROW ADDRESS STROBE : READ : DRAM READ/WRITE : TRANSMIT DATA : WATCH-DOG TIMER OVERFLOW : HIGH WRITE : HH WRITE : HL WRITE : LOW WRITE

: DATA BUS : PORT A : PORT B : PORT C : PORT D : PORT E : SERIAL CLOCK : MTU INPUT CAPTURE/OUTPUT COMPARE : MTU INPUT CAPTURE/OUTPUT COMPARE : MTU INPUT CAPTURE/OUTPUT COMPARE : MTU INPUT CAPTURE/OUTPUT COMPARE : MTU INPUT CAPTURE/OUTPUT COMPARE

HSR-1/1P HSR-2/2P

7-11

IC

IDT71024S15Y-TL (IDT)

C-MOS 1 M (128 x 8)-BIT SRAM

—TOP VIEW—

A16

A14

A12

NC

1

IN

2

IN

3

IN

4

A7

IN

5

A6

IN

6

A5

IN

7

A4

IN

8

A3

IN

9

A2

IN

10

A1

IN

11

A0

IN

12

I/O0

13

I/O1

14

I/O2

15

GND

16

V

32

DD

A15

31

CS2

30

29

WE

A13

28

A8

27

A9

26

A11

25

24

OE

A10

23

22

CS1

I/O7

21

I/O6

20

I/O5

19

I/O4

18

I/O3

17

IDT71V256SA15Y (IDT)SOJ

C-MOS 256 K (32 K x 8)-BIT SRAM

—TOP VIEW—

11

I/O1

12

I/O2

13

I/O3

15

I/O4

16

I/O5

17

I/O6

18

I/O7

19

I/O8

WE27CS20OE

22

: ADDRESS : CHIP SELECT : OUTPUT ENABLE : WRITE ENABLE

: DATA

: LOW LEVEL : HIGH LEVEL : DON’T CARE : HIGH IMPEDANCE

 WE

A13

A8

A9

A11

OE

A10

CS

I/O8

I/O7

I/O6

I/O5

I/O4

READ

IN

10

A0

9

A1

8

A2

7

A3

6

A4

5

A5

4

A6

3

A7

25

A8

24

A9

21

A10

23

A11

2

A12

26

A13

1

A14

INPUT

A0 - A14

CS OE WE

INPUT/OUTPUT

I/O1 - 1/O8

0 1

x

HI-Z

12

A0

11

A1

10

A2

IN

9

A3

8

A4

IN

7

A5

6

A6

IN

5

A7

27

A8

IN

26

A9

23

A10

IN

25

A11

4

A12

IN

28

A13

3

A14

IN

31

A15

2

A16

IN

29

WE

IN

24

OE

22

CS1

IN

30

CS2

INPUTS

CS1

WE

1

x

0

1

0

1

0

1

: HIGH LEVEL

0

: LOW LEVEL : DON’T CARE

x

: HIGH IMPEDANCE

HI-Z

CS2

13

I/O0

14

I/O1

15

I/O2

17

I/O3

18

I/O4

19

I/O5

20

I/O6

21

I/O7

I/O FUNCTION

OE

x

HI-Z

0

x

HI-Z

1

HI-Z

1

0

DATA OUT

1

x

DATA IN

STANDBY STANDBY

OUTPUTS DISABLED

READ DATA

WRITE DATA

A14

A12

IN

1

IN

2

A7

IN

3

A6

IN

4

A5

IN

5

A4

IN

6

A3

IN

7

A2

IN

8

A1

IN

9

A0

IN

10

I/O1

11

I/O2

12

I/O3

13

14

GND

OE

WE

CS

OUTPUTS

x

1

0

1

0

x

0

D

HI-Z HI-Z

OUT

D

IN

28

V

DD

27

26

25

24

23

22

21

20

19

18

17

16

15

FUNCTION

NO SELECTION

OUTPUT DISABLE

WRITE

12

A0

11

A1

10

A2

9

A3

8

A4

7

A5

6

A6

5

I/O0 - I/O7

A7 A8

A9 A10 A11 A12 A13 A14 A15 A16

WE

OE CS1 CS2

27 26 23 25

4

28

3

31

2

13 - 15 17 - 21

29 24 22 30

ADDRESS

DECODER

8

CONTROL

LOGIC

1,048,576-BIT

MEMORY ARRAY

I/O CONTROLLER

LM2940CSX-5.0 (NS)

LOW DROPOUT TYPE VOLTAGE REGULATOR

1

OUTPUT

INPUT

GND

2

INPUT

GND

(1)

OUTPUT

(2)

(3)

10

A0

9

A1

8

A2

7

A3

6

BUFFER

A4

5

A5

4

A6

3

A7

25

A8

24

A9

21

A10

23

A11

2

BUFFER

A12

26

A13

1

A14

20

CS

22

CONTROL

OE

27

CIRCUIT

WE

8

DECODER

ROW

512 x 512

MEMORY

ARRAY

COLUMN

I/O

COLUMN

DECODER

INPUT

DATA

CIRCUIT

I/O

BUFFER

11

I/O1

12

I/O2

13

I/O3

15

I/O4

16

I/O5

17

I/O6

18

I/O7

19

I/O8

LM1881M (NS) LM1881MX

VIDEO SYNC SEPARATOR

—TOP VIEW—

COMPOSITE

3

TIMING CHART

COMPOSITE VIDEO IN

COMPOSITE SYNC OUT

VERTICAL SYNC OUT

BURST OUT

ODD/EVEN OUT

SYNC

VIDEO

VERTICAL

SYNC

1

OUT

2

IN

3

OUT

4

GND

V

CC

8

ODD/EVEN

7

RSET

6

BURST/BACK

5

OUT

COMPOSITE

2

OUT

VIDEO

6

RSET

COMPOSITE

SYNC

VERTICAL

SYNC

ODD/EVEN

BURST/BACK

1

3

7

5

7-12

HSR-1/1P HSR-2/2P

1M (128 K x 8)-BIT SRAM

—TOP VIEW—

A0

IN

A1

IN

A2

IN

A3

IN

CS

IN

I/O1 I/O2 V

CC

GND

I/O3 I/O4

WE

IN

A4

IN

A5

IN

A6

IN

A7

IN

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

A16

IN

A15

IN

A14

IN

A13

IN

OE

OUT

I/O8 I/O7 GND V

CC

I/O4 I/O5 A12

IN

A11

IN

A10

IN

A9

IN

A8

IN

INPUTS

A0 - A16

CS WE

OUTPUT

OE

INPUTS/OUTPUTS

I/O1 - I/O8

: ADDRESS : CHIP SELECT : WRITE ENABLE

: ENABLE

: DATA

CLK GEN.

PRECHARGE CIRCUIT

MEMORY ARRAY

512 ROWS

256 x 8 COLUMNS

ROW SELECT

DATA

CONT.

CLK

GEN.

I/O CIRCUIT

COLUMN SELECT

A9

A0

A8

I/O1 I/O8

CS

WE

DE

A16

LC74781M-9017-TLM (SANYO) KM68V1002AJ-15T (SAMSUNG)

ON SCREEN DISPLAY CONTROLLER

—TOP VIEW—

INPUTS

: CHIP ENABLE

CS

: OSCILLATION SELECT

CTRL1

: NTSC/PAL-M SELECT

CTRL2

IN

OUT

IN

OUT

: V SYNC INPUT SELECT

CTRL3

: COMPOSITE VIDEO

CV

: LC OSCILLATOR

OSC

: SYSTEM RESET

RST

: SERIAL CLOCK

SCLK

: V SYNC

SEP

: SERIAL DATA

SIN

: SYNC SEP VIDEO

SYN

: CRYSTAL OSCILLATOR

TAL

OUTPUTS

: BLANK

BLANK

: COMPOSITE VIDEO

CV

: LC OSCILLATOR

OSC

: CHARACTOR

CHARA

: SEPARATED COMPOSITE SYNC

SEP

: SYNC SEP BIAS MONITOR

SEPC

: CRYSTAL OSCILLATOR

TAL

CTRL1

BLANK

OSC

CHARA

SCLK

TAL

OSC

SIN

GND

CS

CC

1

IN

2

OUT

3

IN

4

OUT

5

IN

6

OUT

7

OUT

8

IN

9

IN

10

IN

11

V

CC

12

24

23

22

21

20

19

18

17

16

15

14

13

V

RST

CTRL3

CTRL2

SEP

SEPC

SYN

V

CC

CV

NC

CV

IC

9

CS

11

SIN

10

SCLK

23

RST

8

CHARA

6

OSC

7

OSC

17

SYN

18

SEPC

19

SEP

20

SEP

22

CTRL3

HSR-1/1P HSR-2/2P

S/P CONV.

DOT

CLOCK

GENERATOR

SYNC

SEPARATOR

8-BIT

LATCH

AND

COMMAND

DECODER

SYNC

DETECTOR

COMPOSITE

SYNC

SEPARATION

CONTROLLER

H

CHARACTER

REGISTER

COUNTER

SIZE

H SIZE

CHARACTER

REGISTER

COUNTER

TIMING

GENERATOR

V

SIZE

V SIZE

H POSITION

REGISTER

H DOT

COUNTER

H

POSITION

DETECTOR

CHARACTER

CONTROL COUNTER

GENERATOR

V POSITION

REGISTER

COUNTER

POSITION

DETECTOR

COLUMN

COUNTER

SYNC

V DOT

V

BLANK/

INVERT CONTROL REGISTER

BLINK/

INVERT

CONTROLLER

CHARACTER

OUTPUT/ BACKGROUND/ VIDEO OUTPUT CONTROLLERS

DISPLAY CONTROL REGISTER

RAM

WRITE

ADDRESS

COUNTER

DECODER

DISPLAY

RAM

DECODER

FONT

ROM

SHIFT

REGISTER

13

CV

15

CV

5

BLANK

3

TAL

2

TAL

4

CTRL1

21

CTRL2

7-13

IC

LM2990SX-5.0 (NS)

NEGATIVE VOLTAGE REGULATOR (1A)

—TOP VIEW—

COM(GND)

IN OUT

COM

OUTPUT

COM

OUTPUT

(GND)

INPUT

LM385M-1.2 (NS) LM385MX-1.2

MICROPOWER VOLTAGE REFERENCE DIODE

—TOP VIEW—

NC NC

IN+

NC

8

765

123

NC IN_

4

NC

M4T28-BR12SH1 (SGS)

TIMEKEEPER SNAP HAT LITHIUM BATTERY

—SIDE VIEW—

M4T28-BR12SH1 M48T18-100MH1TR

TOP HAT

POK

8 x 8

BIPORT

SRAM ARRAY

8184 x 8

SRAM ARRAY

14128

V

SS

11 - 13, 15 - 19

32768Hz

CRYSTAL

LITHIUM

CELL

OSCILLATOR

AND

CLOCK CHAIN

VOLTAGE SENSE

AND SWITCHING CIRCUITRY

V

DD

INT

M51958AFP600D (MITSUBISHI)

VOLTAGE DETECT DELAY

—TOP VIEW—

2 - 10, 23 - 25

A0 - A12

DQ0 - DQ7

20 26 27 22

E1

E2

W

G

M48T58Y-70MH1TR (SGS-TOM)

64 K (8,184 x 8)-BIT TIMEKEEPER SRAM

—TOP VIEW—

FT

A12

DQ0

DQ1

DQ2

A7

A6

A5

A4

A3

A2

A1

A0

GND

OUT

1

IN

2

IN

3

IN

4

IN

5

IN

6

IN

7

IN

8

IN

9

IN

10

I/O

11

I/O

12

I/O

13

14

CC

V

28

IN

27

W

E2

IN

26

25

24

23

22

21

20

19

18

17

16

15

A8

A9

A11

G

A10

E1

DQ7

DQ6

DQ5

DQ4

DQ3

32768 Hz

CRYSTAL

IN

LITHIUM

CELL

IN

I/O

FT

OSCILLATOR

AND

CLOCK CHAIN

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

DD

V

: ADDRESS INPUTS

A0 - A12

: DATA INPUTS/OUTPUTS

DQ0 - DQ7



: CHIP ENABLE 1 INPUT

E1

E2

: CHIP ENABLE 2 INPUT

FT

: FREQUENCY TEST OUTPUT



: WRITE ENABLE INPUT

W

: OUTPUT ENABLE INPUT

G

1

NC

2

IN

3

NC

4

GND

NC

8

V

CC

7

6

OUT

5

CD

1

V

8 x 8

BIPORT

SRAM ARRAY

8184 x 8

SRAM ARRAY

1428

GND

2 - 10, 23 - 25

A0 - A12

11 - 13, 15 - 19

DQ0 - DQ7

20 26 27 22

IN

E1

E2

W G

CC

5 µA 2.5 µA

2

_

+

6

OUT

+

1.25 V

5

CD

MC14577CF (MOTOROLA) MC14577CFEL

C-MOS DUAL VIDEO AMPLIFIERS

—TOP VIEW—

1

_ +

2

3

4

SS

V

8

V

DD

7

_ +

6

5

7-14

HSR-1/1P HSR-2/2P

IC

1

2

3

4

8

7

6

5

SENS

IN

DO

OUT

CO

OUT

VM

IN

V

CC

NC

ICT

IN

V

EE

BATTERY PROTECTOR

—TOP VIEW—

INPUTS

ICT SENS VM

OUTPUTS

CO DO

: SENSE DELAY CAPACITOR : EXCESSIVE CHARGE/DISCHARGE SENSE : OVER CURRENT SENSE

: CHARGE CONTROL : DISCHARGE CONTROL

CONTROL

LOGIC

+

_

+

_

+

_

2

DO

3

CO

R COL

OVER

CURRENT

DETECTOR

DELAY

DELAY INHIBIT

OVER CURRENT DELAY STARTER

EXCESSIVE CHARGING/ DISCHARGING DELAY STARTER

CONTROL

FINAL EXCESSIVE CHARGING DETECTION COMPARATOR

REFERENCE VOLTAGE

4

VM

6

ICT

1

SENS

EXCESSIVE CHARGING DETECTION COMPARATOR

EXCESSIVE DISCHARGING DETECTION COMPARATOR

MAX232CWE (MAXIM) MAX232CWE-TE-2

RS-232 TRANSMITTER/RECEIVER

—TOP VIEW—

V

TTL/CMOS

INPUTS

TTL/CMOS

OUTPUTS

GND

DD

16

15

14

T1

OUT

13

IN

12

OUT

11

IN

10

T2

IN

9

R2

OUT

1

+

C1

3

+

4

C2

5

11

10

12

9

1

C1 +

2

V +

3

C1 _

4

C2 + R1

5

C2 _ R1

6

V _ T1

7

T2

OUT

8

R2

IN

1

C1+

3

C1_

4

C2+

5

C2_

11

T1

10

T2

13

R1

8

R2

R1, 2

; RECEIVER 1, 2

T1, 2

; TRANSMITTER 1, 2

+5 V

INPUT

C5 C4

+

16

+5 V TO +10 V

VOLTAGE DOUBLER

+10 V TO _10 V

VOLTAGE INVERTER

+5 V

400 K

T1

+5 V

400 K

T2

R1

R2

15

2

V+

6

V_

14

T1

7

T2

12

R1

9

R2

ALL CAPACITORS 0.1µF

+

2

+10 V

–10 V 6

14

7

13

5 K

8

5 K

C3

+

R

DTR

R

DSR

TXD RS-232 OUTPUT

RTS RS-232 OUTPUT

RXD RS-232 INPUT

CTS RS-232 INPUT

NJM2286M-T1 (JRC)

3-CIRCUIT 2-INPUT SIGNAL SWITCH

—TOP VIEW—

IN1B

CTL1

OUT1

OUT2

OUT3

CTL3

IN3A

HL

1

2

3

HL

4

GND2

5

6

7

8

LH

GND1

V

GND3

IN1A

16

15

IN2B

14

13

CC

CTL2

12

IN2A

11

10

IN3B

9

NJM78M12DLA(TE1) (JRC)+12 V(500 mA)

POSITIVE VOLTAGE REGULATOR

—FRONT VIEW—

GND

(2)

31

IN OUT

GND 2

IN

(3)

OUT

(1)

MBM29F400BC-70PFTN (FUJITSU)

C-MOS 4 M (262,144 x 16)-BIT FLASH MEMORY

—TOP VIEW—

1

RY/BY

OUT

A17

A7 A6 A5 A4 A3 A2 A1 A0

CE

OE

DQ0

I/O

DQ8

I/O

DQ1

I/O

DQ9

I/O

DQ2

I/O

DQ10

I/O

DQ3

I/O

DQ11

I/O

INPUT

A0 - A17, A - 1

BYTE CE OE RESET WE

HSR-1/1P HSR-2/2P

NC

2

IN

3

IN

4

IN

5

IN

6

IN

7

IN

8

IN

9

IN

10

IN

11

IN

12 13

GND

IN

14 15 16 17 18 19 20 21 22

: ADDRESS : 8-BIT, 16-BIT MODE SELECT : CHIP ENABLE : OUTPUT ENABLE : HARDWARE RESET : WRITE ENABLE

44

IN

RESET

IN

43

WE

A8

IN

42

A9

IN

41

A10

IN

40

A11

IN

39

A12

IN

38

A13

IN

37

A14

IN

36

A15

IN

35

A16

IN

34

IN

33

GND

DD

V

BYTE

32

DQ15/A-1

31

DQ7

30

DQ14

29

DQ6

28

DQ13

27

DQ5

26

DQ12

25

DQ4

24 23

I/O

OUTPUT

RY/

BY

INPUT/OUTPUT

DQ0 - DQ15

3

A17

34

A16

35

A15

36

A14

37

A13

38

A12

39

A11

40

A10

41

A9

42

A8

4

A7

5

A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

43

WE

33

BYTE

44

RESET

12

CE

14

OE

DQ15/A-1

DQ14 DQ13 DQ12 DQ11 DQ10

DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

RY/BY

: READY/BUSY

: DATA

S-8231AOFN-CAO-T2 (SEIKO I&E)

31 29 27 25 22 20 18 16 30 28 26 24 21 19 17 15

2

7-15

IC

MSM7661GS-BK-R1 (OKI)

DIGITAL VIDEO NTSC/PAL DECODER

—TOP VIEW—

484746454443424140393837363534

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

123456789

I/O SIGNAL

NO.

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

I

11

I

12

I

13

I

14

I

15

I

16

I

CD0 CD1 CD2 CD3 CD4 CD5 CD6

CD7 CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7

PIN NO.

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

10111213141516

I/O SIGNAL

—

V

CC

—

GND

I

SCL

I/O

SDA

I

MODE0

I

MODE1

I

MODE2

I

MODE3

I

RESET L

I

PLLSEL

I

CLKSEL

I

TEST1

I

SLEEP

I

TE

—

GND

—

V

CC

NO.

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

33

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

I/O SIGNAL

O

Y7

O

Y6

O

Y5

O

Y4

O

Y3

O

Y2

O

Y1

O

Y0

O

C7

O

C6

O

C5

O

C4

O

C3

O

C2

O

C1

O

C0

PIN NO.

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

I/O SIGNAL

—

V

CC

—

GND

O

ODD

O

VVALID

O

HVALID

O

VSYNC L

O

HSYNC L

O

CLKXO

O

SYSSEL

O

CLKX2O

O

VCO CP

I/O

SYNC

O

HSY

I

CLKX2

—

GND

—

V

CC

INPUTS

CD0 - CD7 CLKSEL CLKX2 CVBS0 - CVBS7 MODE0 - MODE3 PLLSEL RESET L SCL SLEEP TE TEST1

OUTPUTS

C0 - C7 CLKX2O CLKXO HSY HSYNC L HVALID ODD SYSSEL VCO CP VSYNC L VVALID Y0 - Y7

INPUTS/OUTPUTS

SDA SYNC

: CHROMINANCE SIGNAL : CLOCK SELECT : CLOCK : COMPOSITE SIGNAL : MODE SELECT : (NOT IN USE) : SYSTEM RESET (ACTIVE L)

2

: I

C BUS CLOCK : SLEEP MODE : TEST : TEST

: CHROMA SIGNAL : CLOCK : INTERNAL CLOCK PULSE : A/D CONVERTER CLAMP TIMING SIGNAL : H SYNC : H EFFECTIVE PICTURE ELEMENT TIMING : FIELD DISPLAY : SYSTEM SELECT : (NOT IN USE) : V SYNC : V EFFECTIVE LINES TIMING : COLOR DIFFERENCE SIGNAL

2

: I

C BUS DATA : COMPOSITE SYNC SIGNAL

Y7 - Y0

VVALID

HVALID VSYNC L HSYNC L

SYSSEL

CLKSEL

CLKXO CLKX2

CLKX2O

PLLSEL

SYNC

VCO CP

CVBS7 - CVBS0

7-16

ODD

HSY

33 - 40

51 52 53 54 55 61 57 27 56 62 58 26 60

59

9 - 16

SYNCHRONI-

ZATION

BLOCK

8-BIT

(YCbCr)

EPILOGUE

BLOCK

LUMINANCE

BLOCK

(AGC + LPF)

Lum.

PROLOGUE BLOCK

(2Dim. Y/C SEPARATE)

DECIMATION

FILTER

CHROMINANCE

BLOCK

(ACC + LPF)

chr.

LINE MEMORY

(1Kb) x 2

DECIMATION

FILTER

OUTPUT

FORMATTER

TEST

CONTROL

LOGIC

2

I

C-BUC

CONTROL

LOGIC

41 - 48

21 - 24

1 - 8

30 28 29

25 20 19

C7 - C0

TE

TEST1 SLEEP

RESET L SDA SCL

MODE3 MODE0

CD7 - CD0

SC7S00F (MOTOROLA)CHIP PACKAGE TC7S00F(TE85R)

C-MOS 2-INPUT NAND GATE

—TOP VIEW—

DD

2

A

4

1

B

Y = A • B = A +

A

B

Y

0

1

0

1

0

1

0

A

Y

B

01: LOW LEVEL

: HIGH LEVEL

GND 3

1

5 V

2

4

SN74HC04ANS (TI) SN74HC04ANS-E05

C-MOS HEX INVERTERS

—TOP VIEW—

12 11 10 9 8

14 13

DD

V

GND

7654321

Y=

AAY = Y

Y =

A

Y

0

1

0

0 : LOW LEVEL 1 : HIGH LEVEL

HSR-1/1P HSR-2/2P

IC

B1

18

A1

2

1

2

3

4

5

6

7

8

9

10

17

A2

3

B3

16

A3

4

B4

15

A4

5

B5

14

A5

6

B6

13

A6

7

B7

12

A7

8

B8

11

A8

9

19

1

EN

DIR

20

19

18

17

16

15

14

13

12

11

DIR

IN

A1

A2

A3

A4

A5

A6

A7

A8

EN

IN

B1

B2

B3

B4

B5

B6

B7

B8

GND

V

DD

2 3 4 5 6 7 8 9

18 17 16 15 14 13 12 11

DIR

AB

DIR EN

119

EN

0 0 1

DIR

0 1

x

OPERATION

B to A A to B

HI-Z

0 1

x

HI-Z

: LOW LEVEL : HIGH LEVEL : DON’T CARE : HIGH IMPEDANCE

B2

C-MOS BILATERAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

—TOP VIEW—

TC74HC138AF(EL) (TOSHIBA) TC74VHC138FT(EL) (TOSHIBA)

C-MOS 3-TO-8 LINE DECODER/DEMULTIPLEXER

—TOP VIEW—

EN1

EN2

EN3

Y7

IN

1

A

IN

2

B

IN

3

C

IN

4

IN

5

IN

6

OUT

7

8

GND

16

V

DD

15

OUT

Y0

14

OUT

Y1

13

OUT

Y2

12

OUT

Y3

11

OUT

Y4

10

OUT

Y5

9

OUT

Y6

4

EN1

5

EN2

6

EN3

INPUTS OUTPUTS

EN

C

0

x

1

0

1

0

1

0

1

0

1

EN =

EN1

TC74VHC00F (TOSHIBA) TC74VHC00F(EL)

C-MOS QUAD 2-INPUT NAND GATES

—TOP VIEW—

14 13

12 11 10 9 8

DD

V

GND

7654321

A B

Y = A • B = A + B

A

B

Y

0

1

0

1

0

1

0

1

15

A

Y0

2

14

B

Y1

3

13

C

Y2

12

Y3

11

Y4

10

Y5

9

EN

Y6

7

Y7

Y6

B

A

1

x

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

•

• EN3

EN2

A

Y =

B

0 ; LOW LEVEL 1 ; HIGH LEVEL

Y5

Y4 1 1 1 1 1 1 0 1 1

Y3

Y2

1

0

1

0

1

0

1

0

: LOW LEVEL

1

: HIGH LEVEL

x

: DON’T CARE

Y

TC74VHC153FT(EL) (TOSHIBA)

C-MOS DUAL 4-LINE-TO-1-LINE DATA SELECTOR/MULTIPLEXER

—TOP VIEW—

INH

1

INHX

IN

B

IN

2

X3

IN

3

X2

IN

4

X1

IN

5

X0

IN

Y1

Y0

1

0

1

XC

OUT

CONTROL IN

INH

0 0 0 0 1

6

7

GND

8

B

A

0

1

0

1

x

ON

CHANNEL

0 1 2 3

GND

V

DD

16

Y IN

INH

15

A

IN

14

Y3

IN

13

Y2

IN

12

Y1

IN

11

Y0

IN

10

YC

OUT

9

0

: LOW LEVEL

1

: HIGH LEVEL : DON’T CARE

x

X

6

X0

5

X1 4 3

14

2

10 11 12 13

15

XC

X2

X3

A

B

Y0

Y1

Y2

Y3

Y

INH

7

YC

9

TC74VHC175FT(EL) (TOSHIBA)

C-MOS QUAD D-TYPE FLIP-FLOPS WITH RESET

—TOP VIEW—

Q4

D4 D3

Q4

15 14 13 12 11

16

DD

V

Q

RD

D

RD

Q

18723456

RDQ1Q1

D1 D2

Q3 CK

Q3

910

4

Q

RD

D

RD

Q

GND

Q2

D1

5

D2

12

D3

13

D4

9

RD 1

RD

CK

D

2

Q1

3

Q1

Q2

Q3

Q4

0

7

1

Q2

6

1

10

Q3

11

1

15

Q4

14

0 1

x

0

Q

0

Q

x

1 0

0

x

: LOW LEVEL : HIGH LEVEL : DON’T CARE : NO CHANGE : NO CHANGE

Q

0

1

0

1

0

Q

0

TC74VHC125FT(EL) (TOSHIBA)

C-MOS BUS BUFFER GATES WITH 3-STATE OUTPUT

—TOP VIEW—

10 9 8

DD

V

TC74VHC139FT(EL) (TOSHIBA)

C-MOS DUAL 2-TO-4 DECODER/DEMULTIPLEXER

—TOP VIEW—

IN

1EN

1A

IN

1B

IN

OUT

1Y0

OUT

1Y1

OUT

1Y2

OUT

1Y3

111214 13

V

DD

143

134

125

116

107

98

2EN

2A

2B

2Y0

2Y1

2Y2

2Y3

116

GND

HSR-1/1P HSR-2/2P

GND

G

GA Y

00

0

7651234

1

x

HI-Z

2

A

3

B

IN152

IN

INPUTS

OUT

0

OUT

0 0

OUT

1

OUT

0

: LOW LEVEL

1

: HIGH LEVEL

x

: DON’T CARE

YA

0

10

1

x1

HI-Z

: LOW LEVEL : HIGH LEVEL : DON’T CARE : HIGH IMPEDANCE

4

Y0

5

Y1

6

Y2

79

Y3

EN

115

OUTPUTS

BAEN

Y2 Y0Y1Y3 1101000 111

0

1

0

1

xx111111

Y0

14 11

A

Y1

13

B

Y2 Y3

EN

10 1

1

12

10

TC74VHC245FT(EL) (TOSHIBA)

7-17

IC

TC74VHC32FT(EL) (TOSHIBA)

C-MOS QUAD 2-INPUT OR GATES

—TOP VIEW—

12 11 10 9 8

14 13

V

DD

GND

7654321

A B

Y = A + B = A • B

A

B

Y

0

1

0

1

0 : LOW LEVEL 1 : HIGH LEVEL

A

Y = Y

B

TC74VHC541F (TOSHIBA) TC74VHC541F(EL) TC74VHC541FT(EL) (TOSHIBA) TC74VHCT541AF(EL) (TOSHIBA) TC74VHCT541AFT(EL) (TOSHIBA)

C-MOS BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

—TOP VIEW—

Y3 Y8Y7Y6

Y5Y2G2Y1 Y4

DD

V

G1

G1 G2

171820 19

A3

G1

YA

0 0 1

x

1316 15 14

12

11

2

A1

3

A2

4

A3

5

A4

6

A5

7

A6

8

GND

8

7651234

9

10

A7A6 A8

A5A4A2A1

G2

A

Y

0

HI-Z HI-Z

1

: LOW LEVEL

1

: HIGH LEVEL

x

: DON’T CARE

HI-Z

: HIGH IMPEDANCE

0

1

x

1

x

9

A7 A8

G1

119

TC74VHC74FT(EL) (TOSHIBA)

C-MOS DUAL D-TYPE FLIP-FLOPS WITH DIRECT SET/RESET

—TOP VIEW—

14 13

12 11 10 9 8

V

DD

Q

S

D

R

D

4

S

D

2

D

3

Q

R

D

1

Q

S

D

R

D

GND

7654321

10

S

5

6

D

12

D

11

9

Q

8

Q

R

D

13

INPUTS OUTPUTS

S

D

R

D

CK

0

1

x

1

0

x

0

x

1

0

: LOW LEVEL

1

: HIGH LEVEL

x

: DON’T CARE

D

Qn+1

x

1

0

x

0

1

x

1

0

1

x

Qn

TC7S08FU(TE85R) (TOSHIBA)

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13

Y6

12

Y7

11

Y8

G2

TC7SET08F(TE85L) (TOSHIBA) TC7SET08FU(TE85R) TC7SH08FU-TE85R (TOSHIBA)CHIP PACKAGE

C-MOS 2-INPUT AND GATE

—TOP VIEW—

1 2

GND 3

5 V

4

DD

2

4

A

1

Y =

B

Y = A • B = A + B

A

B

Y

0

1

0

1

0

0 : LOW LEVEL

1

1 : HIGH LEVEL

A

Y

B

TC74VHC574F (TOSHIBA) TC74VHC574F(EL) TC74VHCT574AF(EL) (TOSHIBA)

C-MOS 3-STATE D-TYPE EDGE-TRIGGERED FLIP-FLOP

—TOP VIEW—

2

D1

1

IN

EN

2

D1

IN

3

D2

IN

4

D3

IN

5

D4

IN

6

D5

IN

7

D6

IN

8

D7

IN

9

D8

IN

10

GND

D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8

2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12

20

V

DD

19

Q1

18

Q2

17

Q3

16

Q4

15

Q5

14

Q6

13

Q7

12

Q8

11

CK

3

D2

4

D3

5

OUT

IN

D4

6

D5

7

D6

8

D7

9

D8

11

19

Q1

18

Q2

17

Q3

16

Q4

15

Q5

14

Q6

13

Q7

12

Q8

EN

1

DQ

Q

EN EN

11

CK

1

EN

7-18

EACH FLIP-FLOP

INPUTS OUT

EN

CKxD 0 0 0 1

0

: LOW LEVEL

1

: HIGH LEVEL

x

: DON’T CARE

HI-Z

: HIGH IMPEDANCE

Q

: NONSTABLE

0

QD

Q

TC7SH02FU (TOSHIBA)CHIP PACKAGE TC7SH02FU-TE85R

C-MOS 2-INPUT NOR GATE

—TOP VIEW—

1 2

Q

1

0

x

Q

HI-Z

x

GND 3

1

A

5 V

DD

2

B

4

Y =

A + B

A

B

0

1

0

1

= A •

Y 1 0 0 0

A

4

Y =

B

: LOW LEVEL

0

: HIGH LEVEL

1

Y

TC7SH04FU (TOSHIBA)CHIP PACKAGE TC7SH04FU-TE85R TC7SHU04FU-TE85R (TOSHIBA)CHIP PACKAGE

C-MOS INVERTER

—TOP VIEW—

1 2

GND 3

5 V

4

24

AA

DD

Y =

A

0 1

Y =

Y 1

0 : LOW LEVEL

0

1 : HIGH LEVEL

Y

HSR-1/1P HSR-2/2P

IC

* : OPEN COLLECTOR

1 2 3 4 5 6 7 8

18 17 16 15 14 13 12 11

O1 O2 O3 O4 O5 O6 O7 O8

I1 I2 I3 I4 I5 I6 I7 I8

10

COM

123456789

GND

I1 I2 I3 I4 I5 I6 I7 I8

18 17 16 15 14 13 12 11 10

O1 O2 O3 O4 O5 O6 O7 O8 COM

********

*

DARLINGTON DRIVER

—TOP VIEW—

TC7SH86FU-TE85R (TOSHIBA)

C-MOS 2-INPUT EXCLUSIVE OR GATE

—TOP VIEW—

1 2

GND 3

5 V

4

2

DD

A

4

Y

1

B

• B + A •

Y =

A

B

A

B

Y

0

1

0

1

: LOW LEVEL

0

1

0

: HIGH LEVEL

1

TC7W53FU(TE12R) (TOSHIBA)

C-MOS 2-CHANNEL MULTIPLEXER/DEMULTIPLEXER

—TOP VIEW—

ch1

8 V

7 6 5

OPEN

6

DD

ch0

7

OPEN

A

5

INH V

1

C

EE

23

ON

ch0

0

: LOW LEVEL

ch1

1

: HIGH LEVEL

x

: DON’T CARE

1 2 3

GND 4

CONT. INPUT

INH

0 0 1

A 0 1

x

CHANNEL

TD62083F (TOSHIBA) TD62083F(EL)

OCTAL DRIVER

—TOP VIEW—

05 0908 14 13 12

151618 17

I4

01- 08

: OUTPUTS

I1 - I8

: INPUTS

20 K

10 K

INPUT

2.6 K

TD62783AF (TOSHIBA)

0704030201 06

11

10

8

9

7651234

CC

V

I8I7

I6I5I3I2I1

V

CC

10 K

OUTPUT

5 K

TC7WH74FU(TE12R) (TOSHIBA)

C-MOS D-TYPE FLIP-FLOPS WITH PRESET AND CLEAR

—TOP VIEW—

1 2 3

GND 4 5

INPUTS OUTPUTS

CK

CLR

PR

0

1

X

1

0

X

0

X

1

TC7WU04FU(TE12R) (TOSHIBA)

C-MOS HEX INVERTERS

—TOP VIEW—

1 2 3

GND 4

HSR-1/1P HSR-2/2P

8 VDD

2

7

1

6

D

Qn+1

X

0

1

X

1

0

X

1

0

1

0

X

Qn

NO CHANGE

n

Q

17

AA

DD

8 V 7 6 5

35

62

Y =

A 0 1

7

PR

Q

D

Q

CLR

6

FUNCTION

CLEAR

PRESET

– – –

Y =

A

Y 1

0 : LOW LEVEL

0

1 : HIGH LEVEL

5

3

0

: LOW LEVEL

1

: HIGH LEVEL

x

: DON’T CARE

Y

TL082M (TI) TL082CPS-E05

DUAL OPERATIONAL AMPLIFIERS (DUAL-SUPPLY TYPE)

—TOP VIEW—

1

_ +

2

3

V

EE

4

8

V

CC

7

+ _

6

5

7-19

IC

C

I N

R

S

C

H

V

TMS320AV410 (TI)

DIGITAL NTSC/PAL ENCODER

—TOP VIEW—

8079787776757473727170696867666564636261605958575655545352

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

123456789

I/O SIGNAL

NO.

1

I

2

—

3

O

4

—

5

O

6

I

7

I

8

I

9

—

10

I

11

O

12

I

13

—

14

O

15

I/O

16

—

17

I/O

18

—

19

I

20

I

21

I

22

I

23

—

24

I/O

25

—

VCOIN AGND

PHERR

GND

CLKBOUT

CLKBIN

RESET

EXTEN

V

CC

OSCIN

OSCOUT

TEST0

GND

EVEN

VSYNC

SVCC

HSYNC

GND

D0 D1 D2 D3

V

CC

CLK0 GND



101112131415161718192021222324252627282930

D4 D5 D6 D7

CC

V

GND

D8

D9 D10 D11 V

CC

D12 D13 D14 D15

GND

D16 D17 D18 D19 V

CC

D20 D21

SETUP

GND



NO.

51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

I/O SIGNAL

—

I I I I

—

I I I I

—

CLK1OUT

O —

SCL/FLTMD

I

SDA/IMOD1

I/O

SOUT/IMOD0

I/O

AS/

I

—

IFMOD0/OMOD

I I I I

I — —

PIN NO.

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

I/O SIGNAL

I I I

I — —

I

I —

I

I —

I

I —

I

I —

VCC

NTSC

D22 D23 OLC

GND

OL0 OL1 OL2 OL3

CC

SV

GND

CS/INTER

VCC

IFMOD1

CLKSEL

TEST1 TEST2

GND

AGND

PIN NO.

100

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

51

I/O SIGNAL

—

AGND

—

AV

—

AVCC

I

COMP0

I

BIAS0

I

COMP1

I

BIAS1

I

COMP2

I

BIAS2

I

VREF

—

AGND

O

DAOUT2

—

AGND

O

DAOUT1

—

AGND

O

DAOUT0

—

AGND

—

GND

O

CSYNC

—

VCC

—

VCC

AVCC

— O

TEST3

I

RBIAS1

I

RBIAS0

INPUTS

AS BIAS0 - BIAS2 CLKBIN

50

CLKSEL

49

COMP0 - COMP2

48

S

47

D0 - D23

46

EXTEN

45

FLTMD

44

IFMOD0, IFMOD1

43

IMOD0, IMOD1

42

NTER

41

TSC

40

OL0 - OL3

39

OLC

38

OSCIN

37

RBIAS0, RBIAS1

36

ESET

35

SCL

34

ETUP

33

TEST0 - TEST2

32

VCOIN

31

VREF

OUTPUTS

CLK1OUT CLKBOUT

SYNC

DAOUT0 DAOUT1

CC

DAOUT2 EVEN OMOD OSCOUT PHERR TEST3

INPUTS/OUTPUTS

CLK0

SYNC

SDA SOUT

SYNC

: SLAVE ADDRESS SELECT : D/A BIAS : SECONDARY SYSTEM CLOCK : CLOCK SELECT : D/A COMPENSATION CAPACITOR : CHIP SELECT : VIDEO DATA : EXTERNAL/INTERNAL SYNC MODE SELECT : COLOR SIGNAL CUTOFF FREQUENCY SELECT : SERIAL INTERFACE MODE SELECT : FORMAT SELECT : INTERLACE/NON-INTERLACE SELECT : PAL/NTSC MODE SELECT : OVERLAY COLOR SELECT : OVERLAY SWITCHING SELECT : CRYSTAL OSCILLATOR : VCO BIAS RESISTOR 1, 2 : RESET : SERIAL CLOCK : SETUP LEVEL SELECT : TEST : VCO CONTROL VOLTAGE : DAC REFERENCE VOLTAGE

: ALTERNATE PIXEL CLOCK : INTERNAL PLL CLOCK : COMPOSITE SYNC : Y OR R VIDEO SIGNAL : COMPOSITE OR G VIDEO SIGNAL : C OR B VIDEO SIGNAL : FIELD ID : OUTPUT MODE SELECT : CRYSTAL OSCILLATOR : PHASE ERROR : TEST

: CLOCK : HORIZONTAL SYNC : SERIAL DATA : DEVICE STATUS : VERTICAL SYNC

12, 72, 73, 98

TEST0 -TEST8

7

RESET

52

NTSC

8

EXTEN

24

CLK0

LPF

BURST PHASE

PHASE

COMPARATOR

CLOCK

CLOSED

CAPTION

ENCODER

BLANKING

LIMITER

SIN

GEN

62

CLK1OUT

HSYNC

VSYNC

D8 - D15

D16 - D22

CL0 - CL3

IFMOD1

IFMOD0/

AS/CS/

SCL/FLTMD

SDA/IMOD1

SOUT/IMOD0

CLKSEL

7-20

EVEN

D0 - D7

YCbCr/CbCr/R

CLC

SETUP

OMOD

INTER

17

15

14

19 - 22, 26 - 29

32 - 35, 37 - 40

42 - 45, 47, 48, 53, 54

57 - 60 55

49

70 69 67

64 65 66

71

Y/G

B

OVERLAY

SWITCH

CONTROL

AND

HOST

INTERFACE

SYNC SIGNAL

GENERATOR

RGB TO

YCbCr/

YCbCr TO RGB MATRIX

COS GEN

1/35

1/33

VCO

OSC

D/A

100

85

3 6 5

1

99

11 10

94

80 91 79

82 89 81

84 87 83

PHERR

CLKBIN

CLKBOUT

VCOIN RBIAS1 RBIAS0

OSCOUT OSCIN

CSYNC

VREF

BIAS0 DAOUT0 COMP0

BIAS1 DAOUT1 COMP1

BIAS2 DAOUT2 COMP2

HSR-1/1P HSR-2/2P

IC

UPD4516821AG5-A10B-9NF (NEC)

C-MOS 16 M (1 M WORD x 8-BIT x 2) -BIT DRAM

—TOP VIEW—

18

A0

19

A1

20

A2

21

A3

24

A4

25

A5

26

A6

27

A7

28

A8

29

A9

17

A10

16

A11

32

CLK

31

CKE

12

WE

14

RAS

13

CAS

33

DOM

13

CS

INPUT

A0 - A11

: ADDRESS : COLUMN ADDRESS STROBE

CAS

CKE

: CLOCK ENABLE

CLK

: SYSTEM CLOCK : CHIP SELECT

CS

DOM

: DATA I/O MASK ENABLE : ROW ADDRESS STROBE

RAS

: WRITE ENABLE

WE

I/O

D0 - D7

: DATA

CAS

RAS

A11

A10

1

DD

V

2

D0

3

GND

4

D1

5

V

DD

6

D2

7

GND

8

D3

9

V

DD

10

NC

11

NC

12

WE

13

14

15

CS

16

17

18

A0

19

A1

20

A2

21

A3

22

V

DD

GND

V

GND

V

GND

44

43

D7

42

41

D6

40

DD

39

D5

38

37

D4

36

DD

35

NC

34

NC

33

DOM

32

CLK

31

CKE

30

NC

29

A9

28

A8

27

A7

26

A6

25

A5

24

A4

23

ZA4024 (TI)

SIGNAL PROCESSOR FOR DIGITAL VCR

—TOP VIEW—

2

D0

4

D1

6

D2

8

D3

37

D4

39

D5

41

D6

43

D7

80

85

90

95

100

PIN No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

75

VCC GND GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC GND

GND VCC

1

I/O SIGNAL

—

V

CC

O

DO0

O

DO1

O

DO2

O

DO3

O

DO4

O

DO5

O

DO6

O

DO7

—

GND

I

OE

I

CKR

I

RS

I

RFSH

—

VCC

I

RA0

I

RA1

I

RA2

I

RA3

—

GND

VCC

70

5

No.

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

65

GND

10

I/O SIGNAL

—

GND

—

GND

—

GND

I

RFSEL

—

GND

—

GND

CC

—

V VCC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

60

CC

V

GND

VCC

VCC VCC

GND

VCCGND

15

20

I/O SIGNAL

No.

41

—

42

—

43

—

44

—

45

—

46

—

47

—

48

—

49

—

50

—

51

—

52

WFSEL

I

53

—

54

—

55

—

56

—

57

I

58

I

59

I

60

I

55

GND

GND GND

GND GND GND GND WA3 WA2 WA1 WA0

V VCC

NC NC NC NC NC NC NC

GND

CC

GND

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

GND

25

No.

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

50

45

40

35

30

I/O SIGNAL

CC

V

—

I

CLR

I

WS

CKW

I I

WE

GND

—

DIN7

I

DIN6

I

DIN5

I

DIN4

I

DIN3

I

DIN2

I

DIN1

I

DIN0

I

V

CC

—

VCC

—

GND

—

GND

—

NC

—

NC

—

PIN No.

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

I/O SIGNAL

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

NC

—

GND

—

V

CC

—

GND

—

UPD4564163G5-A10BL-9JF (NEC)

C-MOS 64 M (1 M WORD x 16-BIT x 4)-BIT DRAM

—TOP VIEW—

V

1

DQ0

2

QV

3

DQ1

4

DQ2

5

QGND

6

DQ3

7

DQ4

8

QV

9

DQ5

10

DQ6

11

QGND

12

DQ7

13

V

14

LDQM

15 16

WE

17

CAS

18

RAS

19

CS

20

A13

21

A12

22

A10

23

A0

24

A1

25

A2

26

A3

27

V

DD

GND

54 53 52

QGND

DD

51 50 49

DD

QV

48 47

QGND

46

DD

45 44 43

QV

DD

42

DD

GND

41 40

NC

39 38 37 36

NC

35 34 33 32 31 30 29 28

DD

GND

DQ15

DQ14 DQ13

DQ12 DQ11

DQ10 DQ9

DQ8

UDQM CLK CKE

A11 A9 A8 A7 A6 A5 A4

INPUT

A0 - A13

CAS

CKE CLK

CS

LDQM

RAS

UDQM

WE

INPUT/OUTPUT

DQ0 - DQ15

: ADDRESS : COLUMN ADDRESS STROBE : CLOCK ENABLE : CLOCK : CHIP SELECT : LOWER DQ MASK ENABLE : ROW ADDRESS STROBE : UPPER DQ MASK ENABLE : WRITE ENABLE

: DATA

DIN0 - DIN7

: DATA INPUTS

DO0 - DO7

: DATA OUTPUTS

CKR

: READ CLOCK INPUT

CKW

: WRITE CLOCK INPUT : RESET INPUT

CLR

: OUTPUT ENABLE INPUT

OE

RA0 - RA3

: READ ADDRESS INPUT

RFSEL

: READ FIELD SELECT INPUT : REFRESH CONTROL INPUT

RFSH

: READ ADDRESS STOROBE INPUT

RS

WA0 - WA3

: WRITE ADDRESS INPUTS : WRITE ENABLE INPUT

WE

WFSEL

: WRITE FIELD SELECT INPUT : WRITE ADDRESS STOROBE INPUT

WS

74 - 67

DIN0 - 7

8 x 8

WRITE BUFFER

64

CKW

60 - 57

WA0 - 3

WE

WS

ADDRESS

65

CONTROLLER

63

WRITE

DRAM

MEMORY

ARRAY 4M-BIT

MEMORY ARRAY

CONTROLLER

MEMORY

WRITE/READ

ARBITRATION

CIRCUIT

62 14

CLR RFSH

8 x 8

READ BUFFER

READ

ADDRESS

CONTROLLER

2 - 9

16 - 19

DO0 - 7

11

OE

12

CKR

RA0 - 3

13

RS

HSR-1/1P HSR-2/2P

7-21

IC

,

UPD78P0208GF-3BA-H101 (NEC)

8-BIT SINGLE-CHIP MICROCOMPUTER

—TOP VIEW—

8079787776757473727170696867666564636261605958575655545352

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

I/O SIGNAL

NO.

1

—

2

I/O

3

I/O

4

I/O

5

I/O

6

I/O

7

I/O

8

I/O

9

I/O 10 11 12 13

—

14

O 15 16

— 17

I/O

18

I/O

19

I/O

20

I/O

21

I/O

22

I/O

23

I/O

24

I/O

25

—

TO0/P30

TI0/INTP0/P00

TO1/P31

TI1/P33

TO2/P32

TI2/P34

SI0/SB0/P25

SO0/SB1/P26

SCK0

SI1/P20

SO1/P21

SCK1

STB/P23

BUSY/P24

ANI0/P10 ANI7/P17

INTP0/TI0/P00 INTP3/P03

BUZ/P36

PCL/P35

I I I

I

/P27

/P22

123456789

V

CC

P37 P36/BUZ P35/PCL

P34/TI2

P33/TI1 P32/TO2 P31/TO1 P30/TO0

RESET

X2



X1

PP

V XT2

P04/XT1

CC

V

P27/

SCK0

P26/SO0/SB1

P25/SI0/SB0

P24/BUSY

P23/STB

P22/

SCK1

P21/SO1

P20/SI1

AGND

9

16-BIT TIMER/

39

EVENT

COUNTER

8

8-BIT TIMER/

EVENT

6

COUNTER 1

7

8-BIT TIMER/

EVENT

5

COUNTER 2

WATCHDOG

TIMER

WATCH

TIMER

19



18

SERIAL

INTERFACE 0

17

24 23 22

SERIAL

INTERFACE 1

21 20

26 - 33

A/D

CONVERTER

36 - 39

INTERRUPT

CONTROL

3

BUZZER

OUTPUT

CLOCK

4

OUTPUT

CONTROL

101112131415161718192021222324252627282930

NO.

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

I/O SIGNAL I/O

I/O I/O I/O I/O I/O I/O I/O

—

I

P03/INTP3

I/O

P02/INTP2

I/O

P01/INTP1

I/O

P00/INTP0/TI0

I

— I/O I/O I/O I/O I/O

—

P127/FIP52

I/O

P126/FIP51

I/O

P125/FIP50

I/O

P124/FIP49

I/O

P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0

CC

AV

REF

GND

P74 P73 P72 P71 P70

CC

V

78 K/0

CPU CORE

I/O SIGNAL

NO.

51

I/O

52

I/O

53

I/O

54

I/O

55

I/O

56

I/O

57

I/O

58

I/O

59

I/O

60

I/O

61

I/O

62

I/O

63

I/O

64

I/O

65

I/O

66

I/O

67

I/O

68

I/O

69

I/O

70

I/O 71 72 73 74 75

PROM

60 K BYTES

O O O O O

P123/FIP48 P122/FIP47 P121/FIP46 P120/FIP45 P117/FIP44 P116/FIP43 P115/FIP42 P114/FIP41 P113/FIP40 P112/FIP39 P111/FIP38 P110/FIP37 P107/FIP36 P106/FIP35 P105/FIP34 P104/FIP33 P103/FIP32 P102/FIP31 P101/FIP30 P100/FIP29

RAM

P97/FIP28 P96/FIP27 P95/FIP26 P94/FIP25 P93/FIP24

PIN NO.

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

PORT0

PORT1

PORT2

PORT3

PORT7

PORT8

PORT9

PORT10

PORT11

PORT12

FIP

CONTROLLER/

DRIVER

SYSTEM

CONTROL

51

I/O SIGNAL

O

P92/FIP23

O

P91/FIP22

O

P90/FIP21

LOAD

—

V

P87/FIP20

O

P86/FIP19

O

P85/FIP18

O

P84/FIP17

O

P83/FIP16

O

P82/FIP15

O

P81/FIP14

O

P80/FIP13

O

FIP12

O

FIP11

O

FIP10

O

FIP9

O

FIP8

O

FIP7

O

FIP6

O

FIP5

O

FIP4

O

FIP3

O

FIP2

O

FIP1

O

FIP0

O

39

P00

36 - 38

P01 - P03

15

P04

26 - 33

P10 - P17

17 - 24

P20 - P27

2 - 9

P30 - P37

41 - 45

P70 - P74

80 - 87

P80 - P87

71 - 78

P90 - P97

63 - 70

P100 - P107

55 - 62

P110 - P117

47 - 54

P120 - P127

47 - 78, 80 - 100

FIP0 - FIP52

79

V

LOAD

10

RESET

12

X1

11

X2

15

XT1/P04

14

XT2

INPUTS

ANI0 - ANI7 BUSY INTP0 - INTP3

50

P00, P04

49

RESET

48

SI0, SI1

47

TI0 - TI2

46

X1, X2

45

XT1, XT2

44 43

OUTPUTS

42

BUZ

41

FIP0 - FIP12, FIP13 - FIP20,

40

FIP21 - FIP28, FIP29 - FIP36,

39

FIP37 - FIP44, FIP45 - FIP52

38

P80 - P87

37

P90 - P97

36

PCL

35

SO0, SO1

34

STB

33

TO0 - TO2

32 31

INPUTS/OUTPUTS

P01 - P03 P10 - P17 P20 - P27 P30 - P37 P70 - P74 P100 - P107 P110 - P117 P120 - P127 SB0, SB1

SCK0

SCK1

: ANALOG : BUSY : INTERRUPT FROM PERIPHERALS : PORT0 : RESET : SERIAL : TIMER : CRYSTAL (MAIN SYSTEM CLOCK) : CRYSTAL (SUBSYSTEM CLOCK)

: BUZZER CLOCK : FLUORESCENT INDICATOR PANEL

: PORT8 : PORT9 : PROGRAMMABLE CLOCK : SERIAL : STROBE : TIMER

: PORT0 : PORT1 : PORT2 : PORT3 : PORT7 : PORT10 : PORT11 : PORT12 : SERIAL BUS : SERIAL CLOCK

UPD485505G-35 (NEC) UPD485505G-35-E2

C-MOS 40 K (5,048 x 8)-BIT FIFO MEMORY

—TOP VIEW—

1

DO 0 OUT

DO 1 OUT

2

3

DO 2 OUT

4

DO 3 OUT

IN

5

RE

IN

6

RSTR

7

GND V

RCK IN

8

DO 4 OUT

9

DO 5 OUT

10

DO 6 OUT

11

DO 7 OUT

12 13

WCK

17

24

DI 0

23

DI 1

22

DI 2

21

DI 3

16

DI 4

15

DI 5

14

DI 6

13

DI 7

20

WE

8

RCK

WRITE ADDRESS

MEMORY CELL

INPUT BUFFER

READ ADDRESS

POINTER

40384-BIT (5048 x 8)

ARRAY

POINTER

24

IN

OUTPUT BUFFER

DI 0

23

DI 1

22

DI 2

21

DI 3

16

DI 4

15

DI 5

14

DI 6

13

DI 7

8

17

19

RSTW

6

RSTR

DI 0 - 7 DO 0 - 7 RCK

RE RSTR RSTW

WCK

WE

RCK WCK

19

5

1 2 3 4

9 10 11 12

6

24

DI 0 IN

23

DI 1 IN

22

DI 2 IN

21

DI 3 IN

IN

20

WE

19

RSTW

18

DD

WCK IN

17

DI 4 IN

16

DI 5 IN

15

DI 6 IN

14

DI 7 IN

1

DO 0

2

DO 1

3

DO 2

4

DO 3

9

DO 4

10

DO 5

11

DO 6

12

DO 7

RE WE 520

: DATA INPUTS : DATA OUTPUTS : READ CLOCK INPUT : READ ENABLE INPUT : RESET READ INPUT : RESET WRITE INPUT : WRITE CLOCK INPUT : WRITE ENABLE INPUT

RSTW RE

DO 0 DO 1 DO 2 DO 3 DO 4 DO 5 DO 6 DO 7

RSTR

7-22

HSR-1/1P HSR-2/2P

SPARE PARTS AND OPTIONAL FIXTURES

8-1. NOTES ON REPAIR PARTS

(1) Safety Related Components Warning

Components marked ! are critical to safe operation. Therefore, specified parts should be used in the case of replacement.

(2) Standardization of Parts

Repair parts supplied from Sony Parts Center may not be always identical with the parts which actually in use due to “accommodating the improved parts and/or engineering changes” or “standardization of genuine parts”. This manual's exploded views and electrical spare parts list are indicating the part numbers of “the standardized genuine parts at present” .

(3) Stock of Parts

Parts marked with “o” SP (Supply Code) column of the spare parts list are not normally required for routine service work. Orders for parts marked with “o” will be processed, but allow for additional delivery time.

SECTION 8

(4) Units for Capacitors, Inductors and Resistors

The following units are assumed in schematic diagrams, electrical parts list and exploded views unless otherwise specified.

Capacitors : µF Inductors : µH Resistors : Z

HSR-1/1P HSR-2/2P

8-1

Cabinets

8-2. EXPLODED VIEWS Cabinets

No. Part No. SP Description 1 A-8320-900-A o MOUNTED CIRCUIT BOARD, KY-425

2 X-3605-317-2 o BRACKET R ASSY, HINGE 3 X-3605-318-3 o DOOR ASSY, FRONT (For UC, CE models) X-3605-328-2 o DOOR ASSY (J), FRONT (For J model) 4 X-3605-319-2 o PANEL SUB ASSY, FRONT (For HSR-1 UC, J models) X-3605-320-2 o PANEL SUB ASSY (CE), FRONT (For HSR-1P CE model) X-3605-878-2 o PANEL SUB ASSY, FRONT (For HSR-2 J, UC model) X-3605-879-2 o PANEL SUB ASSY, FRONT (For HSR-2P CE model) 5 X-3678-708-3 s FOOT, ASSY

6 1-418-121-11 s KEY UNIT, 16 7 1-507-743-21 s JACK, STEREO MINIATURE 8 1-564-002-11 s PIN, CONNECTOR 3P 9 1-672-342-11 o PWB, RM-178 10 1-959-306-11 o HARNESS, SUB (RM-KY)

11 1-959-307-11 o HARNESS, SUB (KY-MB) 12 3-319-224-21 s DAMPER, SMALL 13 3-724-455-41 s SCREW +P M2X3 14 3-510-027-00 s SPRING, COMPRESSION 15 3-615-418-02 o PIN,DOOR

16 3-615-426-01 o COLLAR 2 17 3-615-436-03 o CASE,TOP 18 3-615-437-03 o CASE,BOTTOM 19 3-733-690-01 s +B 4X6 (CU, NI) 20 4-316-015-00 o HOLDER, WIRE

21 4-862-338-00 s RING, STOPPER

8-2

HSR-1/1P HSR-2/2P

Sony HSR-1 Service manual

TABLE OF CONTENTS

Purpose of this manual

Related manuals

MANUAL STRUCTURE

Contents

8-1. NOTES ON REPAIR PARTS