Sony CXP87948, CXP87940 Datasheet

CXP87940/87948

CMOS 8-bit Single Chip Microcomputer

Description

The CXP87940/87948 is a CMOS 8-bit single chip
microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, high
precision timing pattern generation circuit, PWM
output, VISS/VASS circuit, 32kHz timer/counter,
remote control reception circuit, VSYNC separator and
the measurement circuit which measures signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port.

Also the CXP87940/87948 provides sleep/stop
functions which enable to lower power consumption.

Features

• A wide instruction set (213 instructions) which covers various types of data

— 16-bit operation/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz operation (4.5V to 5.5V)

122µs at 32kHz operation (2.7V to 5.5V)

• Incorporated ROM capacity 40K bytes (CXP87940), 48K bytes (CXP87948)

• Incorporated RAM capacity 1376 bytes

• Peripheral functions

— A/D converter 8 bits, 12 channels, successive approximation method

(Conversion time of 20.0µs at 16MHz)

— Serial Interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel

Incorporated 8-bit and 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
Incorporated two-wire 8-bit and 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel

— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,

32kHz timer/counter

— High-precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable

RTG: 5 pins, 2 channels

— PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency of 62kHz at 16MHz)

DA gate pulse output: 13 bits, 4 channels
— Servo input control Capstan FG, drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14 bits
— VISS/VASS circuit Pulse duty auto detection circuit
— Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO

• Interruption 22 factors, 15 vectors, multi-interruption possible

• Standby mode Sleep/stop

• Package 100-pin plastic QFP

• Piggyback/evaluator CXP87800 100-pin ceramic PQFP

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Structure

Silicon gate CMOS IC

100 pin QFP (PIastic)

– 1 –

E96X01-PS

CXP87940/87948

Vss

V

DD

MP
RST
XTAL

EXTAL
TX
TEX

INT2

2

INT1/NMI

INT0

PA0 to PA7

PB0 to PB7

PC0 to PC7

8

PORT A8PORT B8PORT C

CLOCK

GENERATOR/

SYSTEM CONTROL

SPC700

CPU CORE

PD0 to PD7

PE0 to PE1

PE2 to PE7

2

8

PORT D

6

PORT E

RAM

1376 BYTES

ROM

40K/48K BYTES

INTERRUPT CONTROLLER

PF4 to PF7

PF0 to PF3

4

PG0 to PG7

PH0 to PH7

4

PORT F8PORT G8PORT H7PORT I

32kHz

PRESCALER/

TIME BASE TIMER

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

PI1 to PI7

REALTIME

2

PJ0 to PJ7
8

PORT J

CH1

PULSE

CH0

GENERATOR

RAM

PATTERN

GENERATOR

PROGRAMMABLE

5

19

RTO3 to RTO7

PPO0 to PPO18

2

AVss

AV

REF

AV

DD

A/D CONVERTER

12

AN0 to AN11

Block Diagram

FIFO

(CH2)

SERIAL

INTERFACE UNIT

CS0

SCL1

SCL0

SDA0

SDA1

RAM

(CH0)

SERIAL

SERIAL

INTERFACE UNIT

SO0

SCK0

SI1

SI0

2

FIFO

(CH1)

INTERFACE UNIT

SO1

8 BIT TIMER 1

8 BIT TIMER/COUNTER 0

EC

SCK1

TO/DDO

2

2

SERVO INPUT

VSYNC SEPARATOR

DRUM

CAPSTAN

DFG

CFG

EXI1

EXI0

SYNC1

SYNC0

– 2 –

3

CONTROL

CTL

DPG

PBCTL

FIFO

VISS/VASS

REMOCON INPUT

RMC

14 BIT PWM GENERATOR

PWM

4

2

12 BIT PWM GENERATOR CH1

12 BIT PWM GENERATOR CH0

ADJ

DAB1

DAA1

DAB0

DAA0

PWM1

PWM0

CKOUT

Pin Assignment (Top View)

PB7/PPO15

PB6/PPO14

PA2/PPO2

PA1/PPO1

PA0/PPO0

PA5/PPO5

PA4/PPO4

PA3/PPO3

NC

PA7/PPO7

PA6/PPO6

DD

V

SS

V

TX

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/DDO/ADJ

CXP87940/87948

PB5/PPO13
PB4/PPO12
PB3/PPO11
PB2/PPO10

PB1/PPO9

PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3

PC2/PPO18
PC1/PPO17
PC0/PPO16

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5
PD4

PD3/SDA1
PD2/SDA0

PD1/SCL1
PD0/SCL0

10

11
12
13
14
15
16
17
18
19
20

21

22

23

24

25

26

27

28
29
30

100

99

98

1

2
3
4

5
6
7
8
9

32

31

33

97

34

96

35

95

36

94

37

93

38

92

39

91

40

90

41

89

42

88

43

87

44

86

45

85

46

47

84

48

83

82

49

81

50

80

78
77
76
75
74

70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

79

73
72
71

PI6/SO1
PI7/SI1
PE0/INT0/CKOUT
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AVDD
AVREF
AVSS
PF4/AN8

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

MP

RST

SS

V

XTAL

CS0

EXTAL

SI0

Note) 1. NC (Pin 90) is always connected to VDD.

2. Vss (Pins 41 and 88) are both connected to GND.

3. MP (Pin 39) is always connected to GND.

– 3 –

SO0

SCK0

PF7/AN11

PF5/AN9

PF6/AN10

Pin Description

Symbol I/O Description

(Port A)

PA0/PPO0

to

PA7/PPO7

Output/
Real-time
output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port B)

PB0/PPO8

to

PB7/PPO15

Output/
Real-time
output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

CXP87940/87948

Programmable pattern generator (PPG)
output.
Functions as high-precision real-time
pulse output port.
PB0 and PB2 can be 3-state controlled
with PPG.
(19 pins)

PC0/PPO16

to

PC2/PPO18

PC3/RTO3

to

PC7/RTO7
PD0/SCL0

PD1/SCL1
PD2/SDA0

PD3/SDA1
PD4 to PD7

PE0/INT0/
CKOUT

PE1/EC/INT2

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0

I/O/
Real-time
output

I/O/
Real-time
output

I/O

Input/Input/Output

Input/Input/Input

Output/Output
Output/Output
Output/Output
Output/Output
Output/Output

(Port C)
8-bit I/O port. I/O can be set
in a unit of single bits.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)

Real-time pulse generator (RTG) output.
Functions as high-precision real-time
pulse output port. PC3 can be 3-state
controlled with RTG. (5 pins)

(Port D)
8-bit I/O port. I/O can be set in a unit of
single bits for upper 4 bits.
Can drive 12mA sink current.
Lower 4-bit output is N-ch open drain.
(8 pins)

Input to request external
interruption.
Active at the falling edge.

(Port E)
8-bit port.

External event
input for
timer/counter.

Input to request external interruption.
Active at the falling edge.

Lower 2 bits
are for inputs;
upper 6 bits

PWM outputs.
(2 pins)

are for outputs.
(8 pins)

DA gate pulse outputs.
(4 pins)

Serial clock (CH2) I/O.
(2 pins)

Serial data (CH2) I/O.
(2 pins)

System clock
frequency dividing
output.

PE7/DAB1
AN0 to AN3
PF0/AN4

to

PF3/AN7
PF4/AN8

to

PF7/AN11
SCK0
SO0
SI0
CS0

Output/Output
Input

Input/Input

Output/Input

I/O
Ouput
Input
Input

Analog inputs to A/D converter. (12 pins)
(Port F)

8-bit port. Lower 4 bits are for inputs; upper 4 bits are for
outputs.
Lower 4 bits also serve as standby release input pin.
(8 pins)

Serial clock (CH0) I/O.
Serial data (CH0) output.
Serial data (CH0) input.
Serial chip select (CH0) input.

– 4 –

Symbol I/O Description

CXP87940/87948

PG0/CFG
PG1/DFG
PG2/DPG

PG3/PBCTL
PG4/SYNC0

PG5/SYNC1
PG6/EXI0
PG7/EXI1

PH0 to PH7

PI1/RMC
PI2/PWM
PI3/TO/

DDO/ADJ
PI4/INT1/

NMI
PI5/SCK1

Input/Input
Input/Input
Input/Input

Input/Input
Input/Input

Input/Input
Input/Input
Input/Input

Output

I/O/Input
I/O/Output
I/O/Output/

Output/Output
I/O/Input/Input
I/O/I/O

Capstan FG input.
Drum FG input.
Drum PG input.

(Port G)
8-bit input port.
(8 pins)

Playback CTL pulse input.
External event input for timer/counter.

Composite sync signal input.
(2 pins)

External input to FRC capture unit.
(2 pins)

(Port H)
8-bit output port. N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)

Remote control reception circuit input.
14-bit PWM output.

(Port I)
7-bit I/O port.
I/O port can be
set in a unit of
single bits.
(7 pins)

Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output.

Input to request external interruption and
non-maskable interruption. Active at the falling edge.

Serial clock (CH1) I/O.
PI6/SO1
PI7/SI1

PJ0 to PJ7

EXTAL
XTAL
TEX
TX

RST
MP
AVDD
AVREF
AVss
VDD
NC
Vss

I/O/Output
I/O/Input

I/O

Input
Output
Input
Output

Input
Input

Input

Serial data (CH1) output.

Serial data (CH1) input.

(Port J)
8-bit I/O port. I/O and standby release input function can be set in a
unit of single bits.

Connects a crystal oscillator for system clock. When supplying the
external clock, input the external clock to EXTAL and input the
opposite phase clock to XTAL .

Connects a crystal oscillator for 32kHz timer/counter clock. The 32kHz
crystal oscillator is inserted between TEX and TX. When used as event
input, connect the clock source to TEX and leave TX open.

System reset; active at Low level.
Test mode input. Always connect to GND.
Positive power supply of A/D converter.
Reference voltage input of A/D converter.
GND of A/D converter.
Positive power supply. Connect VDD pin to VDD.
No connected. Connect to VDD in normal operation.
GND. Connect both Vss pins to GND.

– 5 –

A

Input/Output Circuit Formats for Pins

CXP87940/87948

Pin

PA0 /PPO0

to

PA7/PPO7
PB4/PPO12

to

PB7/PPO15

12 pins

PB0/PPO8
PB2/PPO10

Port A
Port B

Data bus

PPO data

Ports A, B data

RD (Ports A, B)

PPO8, PPO10 data

PB0, PB2 data

Circuit format

Output becomes active from high
impedance by data writing to port register.

When reset

Hi-Z

Hi-Z

2 pins

PB1/PPO9
PB3/PPO11

2 pins

Data bus

RD (Port B)

PPO9, PPO11 data

PPG control
status register
bit 0
3-state control selection

AA

PPO9, PPO11 data

PB1, PB3 data

Data bus

RD (Port B)

Output becomes active from high
impedance by data writing to port register.

Hi-Z

Output becomes active from high
impedance by data writing to port register.

– 6 –

CXP87940/87948

AAA

AAA

A

AAA

AAA

AAA

PC0/PPO16

to

PC2/PPO18
PC5/RTO5

to

PC7/RTO7

6 pins

Port C

Data bus

PPO, RTO data

Port C data

Port C direction

“0” when reset

RD (Port C)

RTO3 data

PC3 data

Circuit format

When resetPin

Input
protection
circuit

Hi-Z

IP

PC3/RTO3

1 pin

PC4/RTO4

1 pin

PC3 direction

“0” when reset

Data bus

RD (Port C)

RTO4 data

RTG interruption
control register

AAA

bit 7
3-state control selection

“0” when reset

RTO4 data

PC4 data

PC4 direction

“0” when reset

Data bus

RD (PortC)

Hi-Z

IP

Hi-Z

IP

RTO data is OR-gate data of CH0 and CH1.

– 7 –

CXP87940/87948

PD0/SCL0
PD1/SCL1
PD2/SDA0
PD3/SDA1

4 pins

Port D

SCL, SDA

Serial interface CH2
output enable

Port D data

Data bus

RD (Port D)

SCL, SDA
(Serial interface CH2 circuit)

Port D

Circuit format

∗

IP

Schmitt input

BUS SW

To another serial CH2 pin

∗

Large current 12mA

When resetPin

Hi-Z

PD4 to PD7

4 pins

PE0/INT0/
CKOUT

1 pin

Port D data

Port D direction

“0” when reset

Data bus

Port E

Data bus

Interruption circuit

RD (Port D)

ESL0

Port E selection

ESL1

RD (Port E)

PS1
PS2
PS3

10
11

01

MPX

∗

IP

∗

Large current 12mA

IP

Hi-Z

Hi-Z

– 8 –

CXP87940/87948

PE1/EC/INT2

1 pin

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1

4 pins

Port E

Port E

Data bus

DA gate output,
PWM output

Hi-Z control

Port/DA output
selection

“0” when reset

IP

Port E data

RD (Port E)

Circuit format

RD (Port E)

MPX

When resetPin

Data bus

Hi-Z

Interruption circuit/
event counter

Hi-Z

PE6/DAB0
PE7/DAB1

2 pins

AN0 to AN3

4 pins

Port E

Hi-Z control

Data bus

DA gate output

Port E data

Port/DA output
selection

“1” when reset

RD (Port E)

Input multiplexer

IP

MPX

High level

Hi-Z

A/D converter

– 9 –