The CXP87940/87948 is a CMOS 8-bit single chip
microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, high
precision timing pattern generation circuit, PWM
output, VISS/VASS circuit, 32kHz timer/counter,
remote control reception circuit, VSYNC separator and
the measurement circuit which measures signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port.
Also the CXP87940/87948 provides sleep/stop
functions which enable to lower power consumption.
Features
• A wide instruction set (213 instructions) which covers various types of data
— 16-bit operation/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle250ns at 16MHz operation (4.5V to 5.5V)
122µs at 32kHz operation (2.7V to 5.5V)
• Incorporated ROM capacity40K bytes (CXP87940), 48K bytes (CXP87948)
— Serial InterfaceIncorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel
Incorporated 8-bit and 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
Incorporated two-wire 8-bit and 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
— Timer8-bit timer, 8-bit timer/counter, 19-bit time base timer,
32kHz timer/counter
— High-precision timing pattern generatorPPG: maximum of 19 pins, 32 stages programmable
RTG: 5 pins, 2 channels
— PWM/DA gate outputPWM: 12 bits, 2 channels (Repetitive frequency of 62kHz at 16MHz)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
2. Vss (Pins 41 and 88) are both connected to GND.
3. MP (Pin 39) is always connected to GND.
– 3 –
SO0
SCK0
PF7/AN11
PF5/AN9
PF6/AN10
Pin Description
SymbolI/ODescription
(Port A)
PA0/PPO0
to
PA7/PPO7
Output/
Real-time
output
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
(Port B)
PB0/PPO8
to
PB7/PPO15
Output/
Real-time
output
8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)
CXP87940/87948
Programmable pattern generator (PPG)
output.
Functions as high-precision real-time
pulse output port.
PB0 and PB2 can be 3-state controlled
with PPG.
(19 pins)
(Port C)
8-bit I/O port. I/O can be set
in a unit of single bits.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)
Real-time pulse generator (RTG) output.
Functions as high-precision real-time
pulse output port. PC3 can be 3-state
controlled with RTG. (5 pins)
(Port D)
8-bit I/O port. I/O can be set in a unit of
single bits for upper 4 bits.
Can drive 12mA sink current.
Lower 4-bit output is N-ch open drain.
(8 pins)
Input to request external
interruption.
Active at the falling edge.
(Port E)
8-bit port.
External event
input for
timer/counter.
Input to request external interruption.
Active at the falling edge.
Lower 2 bits
are for inputs;
upper 6 bits
PWM outputs.
(2 pins)
are for outputs.
(8 pins)
DA gate pulse outputs.
(4 pins)
Serial clock (CH2) I/O.
(2 pins)
Serial data (CH2) I/O.
(2 pins)
System clock
frequency dividing
output.
PE7/DAB1
AN0 to AN3
PF0/AN4
to
PF3/AN7
PF4/AN8
to
PF7/AN11
SCK0
SO0
SI0
CS0
Output/Output
Input
Input/Input
Output/Input
I/O
Ouput
Input
Input
Analog inputs to A/D converter. (12 pins)
(Port F)
8-bit port. Lower 4 bits are for inputs; upper 4 bits are for
outputs.
Lower 4 bits also serve as standby release input pin.
(8 pins)
Serial clock (CH0) I/O.
Serial data (CH0) output.
Serial data (CH0) input.
Serial chip select (CH0) input.
– 4 –
SymbolI/ODescription
CXP87940/87948
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
PH0 to PH7
PI1/RMC
PI2/PWM
PI3/TO/
DDO/ADJ
PI4/INT1/
NMI
PI5/SCK1
Input/Input
Input/Input
Input/Input
Input/Input
Input/Input
Input/Input
Input/Input
Input/Input
Output
I/O/Input
I/O/Output
I/O/Output/
Output/Output
I/O/Input/Input
I/O/I/O
Capstan FG input.
Drum FG input.
Drum PG input.
(Port G)
8-bit input port.
(8 pins)
Playback CTL pulse input.
External event input for timer/counter.
Composite sync signal input.
(2 pins)
External input to FRC capture unit.
(2 pins)
(Port H)
8-bit output port. N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)
Remote control reception circuit input.
14-bit PWM output.
(Port I)
7-bit I/O port.
I/O port can be
set in a unit of
single bits.
(7 pins)
Input to request external interruption and
non-maskable interruption. Active at the falling edge.
Serial clock (CH1) I/O.
PI6/SO1
PI7/SI1
PJ0 to PJ7
EXTAL
XTAL
TEX
TX
RST
MP
AVDD
AVREF
AVss
VDD
NC
Vss
I/O/Output
I/O/Input
I/O
Input
Output
Input
Output
Input
Input
Input
Serial data (CH1) output.
Serial data (CH1) input.
(Port J)
8-bit I/O port. I/O and standby release input function can be set in a
unit of single bits.
Connects a crystal oscillator for system clock. When supplying the
external clock, input the external clock to EXTAL and input the
opposite phase clock to XTAL .
Connects a crystal oscillator for 32kHz timer/counter clock. The 32kHz
crystal oscillator is inserted between TEX and TX. When used as event
input, connect the clock source to TEX and leave TX open.
System reset; active at Low level.
Test mode input. Always connect to GND.
Positive power supply of A/D converter.
Reference voltage input of A/D converter.
GND of A/D converter.
Positive power supply. Connect VDD pin to VDD.
No connected. Connect to VDD in normal operation.
GND. Connect both Vss pins to GND.
– 5 –
A
Input/Output Circuit Formats for Pins
CXP87940/87948
Pin
PA0 /PPO0
to
PA7/PPO7
PB4/PPO12
to
PB7/PPO15
12 pins
PB0/PPO8
PB2/PPO10
Port A
Port B
Data bus
PPO data
Ports A, B data
RD (Ports A, B)
PPO8, PPO10 data
PB0, PB2 data
Circuit format
Output becomes active from high
impedance by data writing to port register.
When reset
Hi-Z
Hi-Z
2 pins
PB1/PPO9
PB3/PPO11
2 pins
Data bus
RD (Port B)
PPO9, PPO11 data
PPG control
status register
bit 0
3-state control selection
AA
PPO9, PPO11 data
PB1, PB3 data
Data bus
RD (Port B)
Output becomes active from high
impedance by data writing to port register.
Hi-Z
Output becomes active from high
impedance by data writing to port register.
– 6 –
CXP87940/87948
AAA
AAA
A
AAA
AAA
AAA
PC0/PPO16
to
PC2/PPO18
PC5/RTO5
to
PC7/RTO7
6 pins
Port C
Data bus
PPO, RTO data
Port C data
Port C direction
“0” when reset
RD (Port C)
RTO3 data
PC3 data
Circuit format
When resetPin
Input
protection
circuit
Hi-Z
IP
PC3/RTO3
1 pin
PC4/RTO4
1 pin
PC3 direction
“0” when reset
Data bus
RD (Port C)
RTO4 data
RTG interruption
control register
AAA
bit 7
3-state control selection
“0” when reset
RTO4 data
PC4 data
PC4 direction
“0” when reset
Data bus
RD (PortC)
Hi-Z
IP
Hi-Z
IP
RTO data is OR-gate data of CH0 and CH1.
– 7 –
CXP87940/87948
PD0/SCL0
PD1/SCL1
PD2/SDA0
PD3/SDA1
4 pins
Port D
SCL, SDA
Serial interface CH2
output enable
Port D data
Data bus
RD (Port D)
SCL, SDA
(Serial interface CH2 circuit)
Port D
Circuit format
∗
IP
Schmitt input
BUS SW
To another serial CH2 pin
∗
Large current 12mA
When resetPin
Hi-Z
PD4 to PD7
4 pins
PE0/INT0/
CKOUT
1 pin
Port D data
Port D direction
“0” when reset
Data bus
Port E
Data bus
Interruption circuit
RD (Port D)
ESL0
Port E selection
ESL1
RD (Port E)
PS1
PS2
PS3
10
11
01
MPX
∗
IP
∗
Large current 12mA
IP
Hi-Z
Hi-Z
– 8 –
CXP87940/87948
PE1/EC/INT2
1 pin
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
4 pins
Port E
Port E
Data bus
DA gate output,
PWM output
Hi-Z control
Port/DA output
selection
“0” when reset
IP
Port E data
RD (Port E)
Circuit format
RD (Port E)
MPX
When resetPin
Data bus
Hi-Z
Interruption circuit/
event counter
Hi-Z
PE6/DAB0
PE7/DAB1
2 pins
AN0 to AN3
4 pins
Port E
Hi-Z control
Data bus
DA gate output
Port E data
Port/DA output
selection
“1” when reset
RD (Port E)
Input multiplexer
IP
MPX
High level
Hi-Z
A/D converter
– 9 –
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