Sony CXP878P60 Datasheet

CMOS 8-bit Single Chip Microcomputer

Description

The CXP878P60 is a CMOS 8-bit microcomputer
which consists of A/D converter, serial interface,
timer/counter, time base timer, high precision timing
pattern generation circuit, PWM output, VISS/VASS
circuit, 32kHz timer/counter, remote control reception
circuit, HSYNC counter, VSYNC separator and the
measurement circuit which measures signals of capstan
FG and drum FG/PG and other servo systems, as
well as basic configurations like 8-bit CPU, PROM,
RAM and I/O port. They are integrated into a single
chip.

Also the CXP878P60 provides sleep/stop functions
which enable to lower power consumption.

The CXP878P60 is the PROM-incorporated version
of the CXP87860 with built-in mask ROM. This
provides the additional feature of being able to write
directly into the program. Thus, it is most suitable for
evaluation use during system developement and for
small-quantity production.

Structure

Silicon gate CMOS IC

CXP878P60

100 pin QFP (PIastic)

Features

• A wide instruction set (213 instructions) which covers various types of data

— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz operation (4.5V to 5.5V)

122µs at 32kHz operation

• Incorporated PROM capacity 60K bytes

• Incorporated RAM capacity 2048 bytes

• Peripheral functions

— A/D converter 8 bits, 12 channels, successive approximation system

(Conversion time of 20.0µs at 16MHz)

— Serial interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel

Incorporated 8-bit and 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel
Incorporated two-wire 8-bit and 8-stage FIFO
(Auto transfer for 1 to 8 bytes), 1 channel

— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,

32kHz timer/counter

— High precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable

RTG: 5 pins, 2 channels

— PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency of 62kHz at 16MHz)

DA gate pulse output: 13 bits, 4 channels
— Servo input control Capstan FG, drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14 bits
— VISS/VASS circuit Pulse duty auto detection circuit
— Remote control reception circuit 8-bit pulse measurement counter with on-chip, 6-stage FIFO
— HSYNC counter 12-bit event counter (Counts SYNC1 input.)

• Interruption 23 factors, 15 vectors, multi-interruption possible

• Standby mode Sleep/stop

• Package 100-pin plastic QFP

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E96214-PS

Vpp

Vss
V

DD

MP
RST
XTAL

EXTAL

TX

TEX

PC0 to PC7

PB0 to PB7

PA0 to PA7
8

PORT A8PORT B8PORT C

CLOCK

GENERATOR/

SYSTEM CONTROL

RAM

2048 BYTES

PD0 to PD7
8

PORT D

PE0 to PE1

PE2 to PE7

2

6

PORT E

PF4 to PF7

PF0 to PF3
4

PRESCALER/

PG0 to PG7

PH0 to PH7

4

PORT F8PORT G8PORT H7PORT I

32kHz

TIME BASE TIMER

TIMER/COUNTER

2

PI1 to PI7

PULSE

REALTIME

PJ0 to PJ7
8

PORT J

CH1

CH0

GENERATOR

CXP878P60

5

RTO3 to RTO7

INT2
INT1/NMI

INT0

AVss

AV

REF

AV

DD

2

2

A/D CONVERTER

SPC700

CPU CORE

FIFO

SERIAL

INTERFACE UNIT

(CH2)

PROM

60K BYTES

INTERRUPT CONTROLLER

RAM

SERIAL

INTERFACE UNIT

(CH0)

FIFO

SERIAL

INTERFACE UNIT

2

8 BIT TIMER 1

(CH1)

8 BIT TIMER/COUNTER 0

FIFO

FRC

CAPTURE UNIT

2

2
2

CONTROL

SERVO INPUT

VSYNC SEPARATOR

DRUM

CAPSTAN

3

FIFO

CTL

REMOCON INPUT

RAM

PATTERN

GENERATOR

PROGRAMMABLE

2

VISS/VASS

14 BIT PWM GENERATOR

12 BIT PWM GENERATOR CH0

19

4

HSYNC COUNTER

12 BIT PWM GENERATOR CH1

PPO0 to PPO18

Block Diagram

12

SCL1

SCL0

AN0 to AN11

SDA0

SDA1

CS0

SI0

SO0

SCK0

SI1

SO1

SCK1

EC

TO/DDO

SYNC1

SYNC0

EXI1

EXI0

– 2 –

CFG

DFG

DPG

PBCTL

RMC

PWM

DAA0

PWM0

DAB0

PWM1

DAA1

DAB1

ADJ

HCOUT

CKOUT

Pin Assignment (Top View)

PB6/PPO14

PA1/PPO1

PA0/PPO0

PB7/PPO15

PA4/PPO4

PA3/PPO3

PA2/PPO2

PA7/PPO7

PA6/PPO6

PA5/PPO5

Vpp

CXP878P60

SS

DD

V

TX

V

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/DDO/ADJ

PB5/PPO13
PB4/PPO12
PB3/PPO11
PB2/PPO10

PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4

PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5
PD4

PD3/SDA1
PD2/SDA0

PD1/SCL1
PD0/SCL0

10

12
13
14
15
16
17

19

11

18

20
21
22
23
24
25
26
27
28
29
30

100

99

98

1

2
3
4

5
6
7
8
9

32

31

33

97

34

96

35

95

36

94

37

93

38

92

39

91

40

90

41

89

42

88

43

87

44

45

86

85

46

84

47

83

48

82

49

81

50

80
79
78
77
76
75

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52

74
73

51

PI6/SO1
PI7/SI1
PE0/INT0/CKOUT
PE1/EC/INT2/HCOUT
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AV

DD

AVREF
AVSS
PF4/AN8

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

MP

RST

SS

V

XTAL

CS0

EXTAL

SI0

SO0

SCK0

Note) 1. Vpp (Pin 90) is always connected to VDD.

2. Vss (Pins 41 and 88) are both connected to GND.

3. MP (Pin 39) is always connected to GND.

– 3 –

PF5/AN9

PF6/AN10

PF7/AN11

Pin Description

Symbol I/O Description

(Port A)

PA0/PPO0

to

PA7/PPO7

Output/
Real-time
output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port B)

PB0/PPO8

to

PB7/PPO15

Output/
Real-time
output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

CXP878P60

Programmable pattern generator (PPG)
output.
Functions as high precision real-time
pulse output port.
PB0 and PB2 can be 3-state controlled
with PPG.
(19 pins)

PC0/PPO16

to

PC2/PPO18

PC3/RTO3

to

PC7/RTO7
PD0/SCL0

PD1/SCL1
PD2/SDA0

PD3/SDA1
PD4 to PD7

PE0/INT0/
CKOUT

PE1/EC/INT2/
HCOUT

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
AN0 to AN3

I/O/
Real-time
output

I/O/
Real-time
output

I/O

Input/Input/Output

Input/Input/Input/
Output

Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Input

(Port C)
8-bit I/O port. I/O can be set
in a unit of single bits.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)

(Port D)
8-bit I/O port. I/O can be set in a

Real-time pulse generator (RTG) output.
Functions as high precision real-time
pulse output port. PC3 can be 3-state
controlled with RTG. (5 pins)

Serial clock (CH2) I/O. (2 pins)

unit of single bits for upper 4 bits.
Can drive 12mA sink current.

Serial data (CH2) I/O. (2 pins)
Lower 4-bit output is N-ch open
drain. (8 pins)

Input to request external
interruption.
Active at the falling edge.

(Port E)
8-bit port.
Lower 2 bits
are for inputs;
upper 6 bits
are for outputs.

External event
input for
timer/counter.

PWM outputs.
(2 pins)

Input to request external
interruption.
Active at the falling edge.

(8 pins)

DA gate pulse outputs.
(4 pins)

Analog input to A/D converter. (12 pins)

System clock
frequency dividing
output.

Coinsidence
signal output of
HSYNC counter.

PF0/AN4

to

PF3/AN7
PF4/AN8

to

PF7/AN11
SCK0
SO0
SI0
CS0

Input/Input

Output/Input

I/O
Ouput
Input
Input

(Port F)
8-bit port. Lower 4 bits are for inputs; upper 4 bits are
for outputs.
Lower 4 bits also serve as standby release input pin.
(8 pins)

Serial clock (CH0) I/O.
Serial data (CH0) output.
Serial data (CH0) input.
Serial chip select (CH0) input.

– 4 –

Symbol I/O Description

CXP878P60

PG0/CFG
PG1/DFG
PG2/DPG

PG3/PBCTL
PG4/SYNC0

PG5/SYNC1
PG6/EXI0
PG7/EXI1

PH0 to PH7

PI1/RMC
PI2/PWM
PI3/TO/

DDO/ADJ
PI4/INT1/

NMI
PI5/SCK1

Input/Input
Input/Input
Input/Input

Input/Input
Input/Input

Input/Input
Input/Input
Input/Input

Output

I/O/Input
I/O/Output
I/O/Output/

Output/Output
I/O/Input/Input
I/O/I/O

Capstan FG input.
Drum FG input.
Drum PG input.

(Port G)
8-bit input port.
(8 pins)

Playback CTL pulse input.
External event input for timer/counter.

Composite sync signal input.
(2 pins)

External input to FRC capture unit.
(2 pins)

(Port H)
8-bit output port ; N-ch open drain output of medium drive voltage (12V)
and large current (12mA).
(8 pins)

Remote control reception circuit input.
14-bit PWM output.

(Port I)
7-bit I/O port.
I/O port can be
set in a unit of
single bits.
(7 pins)

Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output.

Input to request external interruption and
non-maskable interruption. Active at the falling edge.

Serial clock (CH1) I/O.
PI6/SO1
PI7/SI1

PJ0 to PJ7

EXTAL
XTAL
TEX
TX

RST
MP
AVDD
AVREF
AVss
VDD

Vpp

I/O/Output
I/O/Input

I/O

Input
Output
Input
Output

Input
Input

Input

Serial data (CH1) output.

Serial data (CH1) input.

(Port J)
8-bit I/O port. I/O and standby release input function can be set in a
unit of single bits.

Connects a crystal oscillator for system clock. When supplying the
external clock, input the external clock to EXTAL and input the
opposite phase clock to XTAL.

Connects a crystal oscillator for 32kHz timer/counter clock. The 32kHz
crystal oscillator is inserted between TEX and TX. When used as event
counter, connect the clock source to TEX and leave TX open.

System reset; active at Low level.
Test mode input. Always connect to GND.
Positive power supply of A/D converter.
Reference voltage input of A/D converter.
GND of A/D converter.
Positive power supply. Connect VDD pin to VDD.
Positive power supply for incorporated PROM writing.

In normal operation, connect to VDD.

Vss

GND. Connect both Vss pins to GND.

– 5 –

A

Input/Output Circuit Formats for Pins

CXP878P60

Pin

PA0 /PPO0

to

PA7/PPO7
PB4/PPO12

to

PB7/PPO15

12 pins

PB0 /PPO8
PB2/PPO10

Port A
Port B

Port A, Port B data

Data bus

PPO data

RD (Port A or Port B)

PPO8, PPO10 data

PB0, PB2 data

Circuit format

Output becomes active from high
impedance by data writing to port register.

When reset

Hi-Z

Hi-Z

2 pins

PB1/PPO9
PB3/PPO11

2 pins

Data bus

RD (Port B)

PPO9, PPO11 data

PPG control
status register
bit 0
3-state control selection

AA

PPO9, PPO11 data

PB1, PB3 data

Data bus

RD (Port B)

Output becomes active from high
impedance by data writing to port register.

Hi-Z

Output becomes active from high
impedance by data writing to port register.

– 6 –

CXP878P60

AAA

AAA

A

AAA

PC0/PPO16

to

PC2/PPO18
PC5/RTO5

to

PC7/RTO7

6 pins

PC3/RTO3

Port C

Data bus

Data bus

PPO, RTO data

Port C data

Port C direction

“0” when reset

RD (Port C)

RTO3 data

PC3 data

PC3 direction

“0” when reset

Circuit format

IP

Input
protection
circuit

IP

When resetPin

Hi-Z

Hi-Z

1 pin

PC4/RTO4

1 pin

RTO4 data

RTG interruption
control register

AAA

bit 7
3-state control selection

RTO4 data

PC4 data

PC4 direction

“0” when reset

Data bus

RD (Port C)

Hi-Z

IP

RD (Port C)

RTO data is OR-gate data of CH0 and CH1.

– 7 –

CXP878P60

PD0/SCL0
PD1/SCL1
PD2/SDA0
PD3/SDA1

4 pins

Port D

SCL, SDA

Serial interface CH2
output enable

Port D data

Data bus

SCL, SDA
(Serial CH2 circuit)

Port D

RD (Port D)

Circuit format

∗

IP

Schmitt input

To another serial CH2 pin

∗

Large current 12mA

When resetPin

Hi-Z

BUS SW

PD4 to PD7

4 pins

PE0/INT0/
CKOUT

1 pin

Port D data

Port D direction

“0” when reset

Data bus

Port E

Data bus

Interruption circuit

RD (Port D)

ESL0

Port E selection

ESL1

RD (Port E)

PS1

PS2

PS3

01
10
11

MPX

∗

IP

∗

Large current 12mA

IP

Hi-Z

Hi-Z

– 8 –

CXP878P60

A

PE1/EC/INT2
/HCOUT

1 pin

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1

4 pins

Port E

From
HSYNC counter

Interruption circuit/
event counter

Port E

Data bus

Hi-Z control

Data bus

DA gate output,
PWM output

Hi-Z control

Port E data

Port/DA output
selection

“0” when reset

RD (Port E)

HCOUT

Circuit format

RD (Port E)

MPX

A

When resetPin

IP

Hi-Z

Hi-Z

PE6/DAB0
PE7/DAB1

2 pins

AN0 to AN3

4 pins

Port E

Data bus

DA gate output

Hi-Z control

Port E data

Port/DA output
selection

“1” when reset

RD (Port E)

Input multiplexer

IP

MPX

A/D converter

High level

Hi-Z

– 9 –