Sony CXP87540, CXP87532 Datasheet

CMOS 8-bit Single Chip Microcomputer

Description

The CXP87532/87540 is a CMOS 8-bit micro­computer which consists of arithmetic coprocessor,
A/D converter, serial interface, timer/counter, time
base timer, vector interruption, high precision timing
pattern generation circuit, PWM generator and the
measuring circuit which measures signals of capstan
FG, drum FG/PG, reel FG and other servo systems,
as well as basic configurations like 8-bit CPU, ROM,
RAM and I/O port. They are integrated into a single
chip.

Also this IC provides power on reset function,
sleep/stop function which enables to lower power
consumption.

Features

• A wide instruction set (213 instructions) which covers various types of data

— 16-bit operation multiplycation and division/boolean bit operation instructions

• Minimum instruction cycle During operation 326ns/12.288MHz

• Incorporated ROM capacity 32K bytes (CXP87532)

40K bytes (CXP87540)

• Incorporated RAM capacity 1344 bytes

• Peripheral functions

— Arithmetic coprocessor Multiplying with code, sum of products with code, high speed

execution of many bits shift rotation operation

— A/D converter 8-bit, 8-channel, successive approximation system

(Conversion time 13µs/12.288MHz)
Incorporated 3-stage FIFO for A/D conversion data

— Serial interface Incorporated buffer RAM for data

(1 to 128 bytes auto transfer) 2-channel
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer
— High precision timing pattern generator PPG (11 pins) 32-stage programmable
— PWM output 12-bit, 2-channel (Repeated frequency 48kHz)

8-bit, 3-channel (Repeated frequency 48kHz)
— Servo input control Capstan FG, Drum FG/PG, Reel FG input
— FRC capture unit Incorporated 28-bit and 8-stage FIFO

• Interruption 12 factors, 12 vectors, multi-interruption possible

• Standby mode Sleep/stop

• Package 100-pin plastic QFP/LQFP

• Piggyback/Evaluation CXP87500 100-pin ceramic QFP/LQFP

Structure

Silicon gate CMOS IC

– 1 –

E93820A81-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXP87532/87540

100 pin QFP (Plastic) 100 pin LQFP (Plastic)

– 2 –

CXP87532/87540

6

SPC700

CPU CORE

CO-PROCESSOR

PROM

32K/40K BYTES

CLOCK GENERATOR/

SYSTEM CONTROL

RAM

1344 BYTES

PRESCALER/

TIME BASE TIMER

FRC

CAPTURE

UNIT

FIFO

INTERRUPT CONTROLLER

8BIT PWM GENERATOR 3CH

12BIT PWM GENERATOR 2CH

ATF SYNC UNIT

SWITCHING PULSE

GENRATOR

8BIT TIMER/COUNTER 0

8BIT TIMER 1

A/D CONVERTER

FIFO

SERVO

INPUT

CONTROL

DRUM

CAPSTAN

REEL

SERIAL

INTERFACE

UNIT

RAM

NM1
PE1/INT2
PE3/INT1
PE0/INT0

PE2/PWM0

PE3/PWM1

PE4/PWM2

PE5/PWM3

PE6/PWM4

PF0/AN0

to PF7/AN7

AV

DD

AVREF

AVSS

PA4/ATFS1

PA5/ATFS3

PA7/ATFS2

PK0/RFDT

PK1/MCLK

PE7/SWP

PA6/AREA

PG2/DREF

PG3/DPG

PG4/DFG

PG5/CFG

PG6/RFG0

PG7/RFG1

PA3/PROUT

PG0/EXI0

PG1/EXI1

SI0

SO0

PH2/SI1

PH1/SO1

PE1/EC

PB0/PPO0

to

PA2/PPO10

8

CS0

SCK0

PH3/CS1

PH0/SCK1

PA0 to PA7

PORT A

PB0 to PB7

PORT B

PC0 to PC7

PORT C

PD0 to PD7

PORT D

PE0 to PE1

PE2 to PE7

PORT E

PF0 to PF7

PORT F

PG0 to PG7

PORT G

PH0 to PH3

PH4 to PH7

PORT H

PI0 to PI7

PORT I

PK0 to PK3

PORT K

PJ0 to PJ7

PORT J

PROGRAMMABLE

PATTERN

GENERATOR

RAM

V

SS

V

DD

MP

XTAL
EXTAL

RST

Block Diagram

– 3 –

CXP87532/87540

Pin Assignment 1 (Top View) 100pin QFP

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70
69
68
67

63

64

65

66

61

62

71

72

73

74

81

82

83

84

75

76

77

78

88

87

86

85

79

89

90

100

99

98

97

96

95

94

91

92

93

1

80

PE6/PWM4
PE7/SWP
PK0/RFDT
PK1/MCLK
PK2
PK3
PG0/EXI0
PG1/EXI1
PG2/DREF
PG3/DPG
PG4/DFG
PG5/CFG
PG6/RFG0
PG7/RFG1
PF0/AN0
PF1/AN1
PF2/AN2
PF3/AN3
PF4/AN4
PF5/AN5
PF6/AN6
PF7/AN7
AV

DD

AVREF
AVSS
SCK0
SO0
SI0
CS0
PH0/SCK1

PB5/PPO5
PB4/PPO4
PB3/PPO3
PB2/PPO2
PB1/PPO1
PB0/PPO0

PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0

PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0

PB6/PPO6

PB7/PPO7

PA0/PPO8

PA1/PPO9

PA2/PPO10

PA3/PROUT

PA4/ATFS1

PA5/ATFS3

PA6/AREA

PA7/ATFS2

NC

V

DD

V

SS

NMI

PE0/INT0

PE1/INT2/EC

PE2/PWM0

PE3/PWM1

PE4/PWM2

PE5/PWM3

PJ7

PJ6

PJ5

PJ4

PJ3

PJ2

PJ1

PJ0

MP

RST

V

SS

XTAL

EXTAL

PH7

PH6

PH5

PH4

PH3/INT1/CS1

PH2/SI1

PH1/SO1

Note) 1. NC (Pin 90) is always connected to VDD.

2. VSS (Pins 41 and 88) are both connected to GND.

3. MP (Pin 39) is always connected to VSS.

– 4 –

CXP87532/87540

Pin Assignment 2 (Top View) 100pin LQFP

2
3
4
5
6
7
8
9

10
11

12
13
14
15
16
17
18
19
20

21

22

23
24

25

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70

69

68
67

63

64

65

66

61

62

71

72

73

74

81

82

83

84

75

76

77

78

88

87

86

85

79

89

90

100

99

98

97

96

95

94

91

92

93

1

80

PE6/PWM4

PE7/SWP

PK0/RFDT

PK1/MCLK
PK2
PK3
PG0/EXI0
PG1/EXI1
PG2/DREF
PG3/DPG
PG4/DFG
PG5/CFG
PG6/RFG0
PG7/RFG1
PF0/AN0
PF1/AN1
PF2/AN2
PF3/AN3
PF4/AN4
PF5/AN5
PF6/AN6
PF7/AN7
AV

DD

AVREF
AVSS

PB3/PBO3
PB2/PPO2
PB1/PPO1
PB0/PPO0

PC7
PC6
PC5
PC4
PC3
PC2
PC1

PC0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0

PI7
PI6
PI5

PB6/PPO6

PB7/PPO7

PA0/PPO8

PA1/PPO9

PA2/PPO10

PA3/PROUT

PA4/ATFS1

PA5/ATFS3

PA6/AREA

PA7/ATFS2

NC

V

DD

V

SS

NMI

PE0/INT0

PE1/EC/INT2

PE2/PWM0

PE3/PWM1

PE4/PWM2

PE5/PWM3

PJ2

PJ1

PJ0

MP

RST

V

SS

XTAL

EXTAL

PH7

PH6

PH5

PH4

PH3/INT1/CS1

PH2/SI1

PH1/SO1

PJ7

PJ6

PJ5

PJ4

PJ3

26

27

28

29

30

PI4
PI3

PI2

PI1

PI0

PH0/SCK1

CS0

SCK0
SO0
SI0

PB4/PPO4

PB5/PPO5

Note) 1. NC (Pin 88) is always connected to VDD.

2. VSS (Pins 39 and 86) are both connected to GND.

3. MP (Pin 37) is always connected to VSS.

– 5 –

CXP87532/87540

(Port C)
8-bit input/output port, enables to specify input/output by 4-bit unit.
(8 pins)

Output/
Real time output

Output/
Monitor output

Output/
Real time output

I/O

I/O

Input/Input

Input/Input/
Input

Output/Output

Output/Output

Input/Input

Input/Input
Input/Input
Input/Input
Input/Input
Input/Input
Input/Input
Input/Input
Input/Input

(Port B)
8-bit output port. Data is
gated with PPO by OR-gate
and they are output. (8 pins)

(Port D)
8-bit input/output port. Lower 4 bits can be specified as input/output by
bit unit and upper 4 bits can be specified as input/output by 4-bit unit.
(8 pins)

(Port E)
8-bit port. Lower 2 bits
are input pins and upper
6 bits are output pins.
(8 pins)

External input pin 0.
External input pin 1.
Drum reference signal input pin.
Drum PG input pin.
Drum FG input pin.
Capstan FG input pin.

Reel FG input pin.

Input pin to request external interruption.
Active when falling edge.

PWM output pins (5 pins)

SWP output pin.

Programmable pattern generator (PPG)
Output (3 pins) and capstan servo control
signal (1 pin).

Symbol I/O Description

PA0/PPO8
PA1/PPO9
PA2/PPO10
PA3/PROUT

PA4/ATFS1
PA5/ATFS3
PA6/AREA
PA7/ATFS2

PB0/PPO0

to

PB7/PPO7

PC0 to PC7

PD0 to PD7

PE0/INT0

PE1/EC/INT2

PE2/PWM0

to

PE6/PWM4
PE7/SWP

PF0/AN0

to

PF7/AN7

PG0/EXI0
PG1/EXI1
PG2/DREF
PG3/DPG
PG4/DFG
PG5/CFG
PG6/RFG0
PG7/RFG1

(Port A)
8-bit output port.
Data is gated with PPO
(3 pins), monitor signal
(4 pins) in relation to ATF,
control signal (1 pin) for
capstan servo by OR-gate
and they are output. (8 pins)

Monitor output in relation to ATF.
(4 pins)

Programmable pattern generator (PPG)
output. (8 pins)

External event
input pin for
timer/counter.

(Port F)
8-bit input port. (8 pins)
Upper 4 bits serve as
standby release input pin.

(Port G)
8-bit input port.
(8 pins)

Analog input pins to A/D converter.
(8 pins)

Pin Description

Input pin to request
external interruption.
Active when falling edge.

– 6 –

CXP87532/87540

Symbol I/O Description
PH0/SCK1
PH1/SO1
PH2/SI1

PH3/INT1/
CS1

PH7 to PH4

PI0 to PI7

PJ0 to PJ7

PK0/RFDT
PK1/MCLK
PK2, PK3
SCK0
SO0
SI0
CS0
NMI

EXTAL
XTAL

RST

MP
AVDD
AVREF

AVSS
VDD
VSS

Input/I/O
Input/Output
Input/Input

Input/Input/Input

Output

I/O

I/O

I/O/Input
I/O/Input
I/O
I/O
Output
Input
Input
Input
Input

Output

I/O

Input

Input

Serial clock input/output pin.
Serial data output pin.
Serial data input pin.

Chip select input pin to serial interface.

Serial clock input/output pin.
Serial data output pin.
Serial data input pin.
Chip select input pin to serial interface.
Non-maskable interrupt request pin. Active during falling edge.
Connecting pin of crystal oscillator for system clock. When supplying

the external clock, input the external clock to EXTAL pin and set XTAL
pin to open.

System reset pin of active “L” level. RST pin is input/output pin, which
output “L” level by incorporated power on reset function when power
ON. (Mask option)

(Port H)
4-bit input port.
(4 pins)

Input pin to request
external interruption.
Active when falling edge.

(Port H)
4-bit output port. N-ch open drain output of middle tension proof (12V)
and large current (12mA). (4 pins)

(Port I)
8-bit input/output port, enables to specify input/output by 4-bit unit.
(8 pins)

(Port J)
8-bit input/output port, enables to specify input/output by 4-bit unit.
(8 pins)

(Port K)
4-bit input/output port,
enables to specify input/
output by bit unit. (4 pins)

Playback data input pin.
Channel clock input pin.

Test mode pin. This pin is always connected to GND.
Positive power supply pin of A/D converter.

Set the same voltage as VDD.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
Positive power supply pin.
GND pin. Connect both VSS pins to GND.

– 7 –

CXP87532/87540

I/O Circuit Formats for Pins

Pin Circuit format When reset

Port A
Port B

Port C

Port D

Port E

Hi-Z

Hi-Z

Hi-Z

Hi-Z

PA0/PPO8

to
PA2/PPO10
PA3/PROUT
PA4/ATFS1
PA5/ATFS3
PA6/AREA
PA7/ATFS2
PB0/PPO0

to
PB7/PPO7

16 pins

PC0

to

PC7

8 pins

PD0

to

PD7

8 pins

PE0/INT0
PE1/EC/
INT2

2 pins

PPO, PROUT,
ATFS1 to ATFS3,
AREA, data

Data bus

Output becomes active from high impedance
by data writing to port register.

Port A or Port B

RD

Data bus

RD (Port D)

Port D direction

Port D data

IP

Large current
12mA

Lower 4 bits are by bit unit
and upper 4 bits are by 4­bit unit

Data bus

RD (Port C)

Port C direction

Port C data

IP

Input protection
circuit

(Every 4 bits)

Buffer

IP

RD (Port E)

Data bus

Schmitt input

– 8 –

CXP87532/87540

Port E

Port E

Port F

Port G

Hi-Z

H level

Hi-Z

Hi-Z

PE2/PWM0
PE3/PWM1
PE4/PWM2
PE5/PWM3

4 pins

PE6/PWM4
PE7/SWP

2 pins

PF0/AN0

to

PF7/AN7

8 pins

PG0/EXI0
PG1/EXI1
PG2/DREF
PG3/DPG
PG4/DFG
PG5/CFG
PG6/RFG0
PG7/RFG1

8 pins

Data bus

RD (Port E)

PWM output

MPX

Port/PWM output
select

Port E data

Hi-Z control

Data bus

RD (Port E)

Port/PWM, SWP
output select

PWM, SWP output

MPX

Port E data

IP

Input multiplexer

A/D converter

Analog/Digial
input select

RD (Port F)

Data bus

IP

RD (Port G)

Data bus

Schmitt input

Servo input

For PG0/EXI0 to PG7/RFG1, TTL schmitt input can be
selected with the mask option.

Pin Circuit format When reset