Sony CXP87460, CXP87452 Datasheet

CXP87452/87460
CMOS 8-bit Single Chip Microcomputer
Description
The CXP87452/87460 is a CMOS 8-bit micro­computer which consists of A/D converter, serial interface (2ch independently), timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit (PPG 2ch independently, RTG 2ch independently), PWM generator, general purpose prescaler, PWM for tuner, VCR vertical sync separation circuit and the measuring circuit which measure signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip.
Also CXP87452/87460 provides power on reset function, sleep/stop function which enables to lower power consumption .
100 pin QFP (PIastic) 100 pin LQFP (PIastic)
Structure
Silicon gate CMOS IC
Features
A wide instruction set (213 instructions) which cover various types of data
— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction
Minimum instruction cycle During operation 333ns/12MHz (3.0 to 5.5V)
During operation 250ns/16MHz (4.5 to 5.5V)
Incorporated ROM capacity 52K bytes (CXP87452)
60K bytes (CXP87460)
Incorporated RAM capacity 1568 bytes
Peripheral functions
— A/D converter 8-bit, 12-channel, successive approximation system
(Conversion time: 20µs/16MHz)
— Serial interface Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel
Incorporated 8-bit and 8-stage FIFO
(1 to 8 bytes auto transfer) 1-channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer — High precision timing pattern generator PPG 19 pins 32-stage programmable
PPG 10 pins 21-stage programmable
RTG 5 pins 2-channel — PWM/DA gate output PWM 12-bit, 2-channel (Repetitive frequency 62.5kHz/16MHz)
DA gate pulse 12-bit, 4-channel — Servo input control Capstan FG, Drum FG/PG, CTL input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14-bit, 1-channel — General purpose prescaler 10-bit (System clock asynchronous) — Pulse cycle measurement circuit
Interruption 18 factors, 14 vectors, multi-interruption possible
Standby mode SLEEP/STOP
Package 100-pin plastic QFP/LQFP
Piggyback/evaluation chip CXP87400 100-pin ceramic QFP/LQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95111-PS
CXP87452/87460
Vss V
DD
MP RST
XTAL EXTAL
PA0 to PA7
8
PORT A
CLOCK
GENERATOR/
SYSTEM CONTROL
SPC700
CPU CORE
PB0 to PB7
8
PORT B
PC0 to PC7 8
PORT C
RAM
ROM
PE2 to PE7
PE0 to PE1
PD0 to PD7
2
8
PORT D
6
PORT E
1568 BYTES
52K/60K BYTES
PF4 to PF7
PF0 to PF3
4
4
PORT F
PH0 to PH7
8 PG0 to PG7
PORT G
FIFO
PI1 to PI7
PI0 1
8
PORT H
7
PORT I
PRESCALER/
TIME BASE TIMER
PJ0 to PJ7
8
PORT J
PROGRAMMABLE
2
PK0
1
PORT K
RAM
2
10
PATTERN
GENERATOR (CH1)
RAM
19
PULSE
REALTIME
GENERATOR
CH1
CH0
RTO7
to
RTO3
5
10
PPO113
to
PPO112 PPO107
to
PPO100
PPO000 to PPO018
19
PE1/INT2 PI4/INT1
PE0/INT0
AVss
AV
REF
AV
DD
2
A/D CONVERTER
12
to
PF0/AN4
PF7/AN11
AN0 to AN3
RAM
BUFFER
(CH0)
SERIAL
SERIAL
INTERFACE UNIT
SI0
SO0
CS0
SCK0
PI7/SI1
INTERRUPT CONTROLLER
2
FIFO
8BIT TIMER 1
(CH1)
8BIT TIMER/COUNTER 0
INTERFACE UNIT
PI3/TO
PI6/SO1
PE1/EC
PI5/SCK1
PG4/SYNC0
FRC
2
2
CONTROL
SERVO INPUT
V SYNC SEPARATOR
PG6/EXI0
PG7/EXI1
PG5/SYNC1
CTL
DRUM
CAPSTAN
PG0/CFG
PG1/DFG
PG2/DPG
UNIT
CAPTURE
3
14BIT PWM GENERATOR
PROGRAMMABLE PRESCALER
PI1/PO
PK0/OSCO
PG3/PBCTL
PI0/PCK/OSCI
PI2/PWM
PE0/XOUT
PATTERN
PROGRAMMABLE
GENERATOR (CH0)
4
4
2
PULSE MEASURE UNIT
12BIT PWM GENERATOR CH1
12BIT PWM GENERATOR CH0
PE4/DAA0
PE6/DAB0
PE3/PWM1
PE2/PWM0
PG4/PMI
PE7/DAB1
PE5/DAA1
PG7/PMSK
Block Diagram
– 2 –
Pin Configuration 1 (Top View) 100 pin QFP Package
PA7/PPO007/PPO107
PA5/PPO005/PPO105
PA6/PPO006/PPO106
93
92
91
40
38
39
PB5/PPO013/PPO113 PB4/PPO012/PPO112
PB3/PPO011 PB2/PPO010 PB1/PPO009 PB0/PPO008
PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4
PC3/RTO3 PC2/PPO018 PC1/PPO017 PC0/PPO016
PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1
PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
100
1 2 3 4
5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
24
25 26 27 28
29 30
PB7/PPO015
PB6/PPO014
99
98
32
31
33
PA0/PPO000/PPO100
PA1/PPO001/PPO101
PA2/PPO002/PPO102
PA4/PPO004/PPO104
PA3/PPO003/PPO103
95
94
96
97
35
37
36
34
CXP87452/87460
option
Mask
SS
DD
NC
V
89
90
41
42
V
88
43
PI0/PCK/OSCI
PK0/OSCO
86
87
45
44
PI1/PO
85
46
PI2/PWM
84
83
48
47
PI4/INT1
PI3/TO
82
49
PI5/SCK1
81
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60
58 57 56 55 54 53 52 51
50
PI6/SO1 PI7/SI1 PE0/INT0/XOUT PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PF2/DPG PG3/PBCTL PG4/SYNC0/PMI PG5/SYNC1 PG6/EXI0 PG7/EXI1/PMSK AN0 AN1 AN2
59
AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AV
DD
AVREF AVSS PF4/AN8
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
MP
RST
SS
V
XTAL
CS0
EXTAL
SI0
SO0
SCK0
Note) 1. NC (Pin 90) is always connected to VDD.
2. Vss (Pins 41 and 88) are both connected to GND.
– 3 –
PF6/AN10
PF7/AN11
PF5/AN9
Pin Configuration 2 (Top View) 100 pin LQFP Package
PB7/PPO015
PB6/PPO014
PB5/PPO013/PPO113
PB4/PPO012/PPO112
99
98
100
96
97
PA0/PPO000/PPO100
PA3/PPO003/PPO103
PA1/PPO001/PPO101
95
PA4/PPO004/PPO104
PA2/PPO002/PPO102
93
94
92
91
PA6/PPO006/PPO106
PA7/PPO007/PPO107
PA5/PPO005/PPO005
NC
89
88
90
CXP87452/87460
option
Mask
SS
DD
V
V
86
87
PI0/PCL/OSCI
PK0/OSCO
84
85
83
PI1/PO
PI2/PWM
82
PI3/TO
81
PI4/INT1
80
PI5/SCK1
78
79
PI7/SI1
PI6/SO1
77
76
PE0/INT0/XOUT
PB3/PPO011 PB2/PPO010 PB1/PPO009
PB0/PPO008
PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3
PC2/PPO018 PC1/PPO017 PC0/PPO016
PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1
PJ0 PD7 PD6 PD5 PD4 PD3
1
2 3 4
5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22
23
24 25
75 74 73 72
71
70 69 68 67
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PF2/DPG PG3/PBCTL PG4/SYNC0/PMI PG5/SYNC1 PG6/EXI0 PG7/EXI1/PMSK AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AV
DD
AVREF
35
PH2
PH1
36
37
PH0
32
31
PH6
PH5
PH4
33
34
PH3
26
27
28
30
29
PD1
PD2
PD0
PH7
MP
40
38
39
SS
V
RST
41
XTAL
42
CS0
EXTAL
43
44
SI0
SO0
Note) 1. NC (Pin 88) is always connected to VDD.
2. Vss (Pins 39 and 86) are both connected to GND.
– 4 –
45
46
SCK0
48
47
PF7/AN11
PF6/AN10
49
50
PF4/AN8
PF5/AN9
SS
AV
Pin Description
Symbol I/O Description
CXP87452/87460
PA0/PPO000 /PPO100
to PA7/PPO007 /PPO107
PB0/PPO008
to PB7/PPO015
PC0/PPO016
to PC2/PPO018
PC3/RTO3
to PC7/RTO7
PD0 to PD7
PE0/INT0 /XOUT
Output/ Real time output
Output/ Real time output
I/O/ Real time output
I/O/ Real time output
I/O
Input/input/output
(Port A) 8-bit output port. Data is gated with PPO0 and PPO1 contents by OR-gate and they are output. (8 pins)
(Port B) 8-bit output port. Data is gated with PPO0 and PPO1 contents by OR-gate and they are output. (8 pins)
(Port C) 8-bit I/O port. Enables to specify I/O by bit unit. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins)
(Port D) 8-bit I/O port. Enable to specify I/O by 4-bit unit. Enables to drive 12mA sinc current. (During 5V ± 0.5V operation) (8 pins)
Programmable pattern generator (PPG0, PPG1) output. Functions as high precision real time pulse output port.
PPG0 19 pins
(
PPG1 10 pins
Real time pulse generator (RTG) output. Functions as high precision real time pulse output port. (5 pins)
Input pin to request external interruption. Active when falling edge.
)
1/2 dividing clock output of XTAL or OSCO.
PE1/EC/INT2
PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4
to PF3/AN7
PF4/AN8
to PF7/AN11
SCK0 SO0 SI0
Input/input/input
Output/output Output/output Output/output Output/output Output/output Output/output Input
Input/input
Output/input
I/O Ouput Input
External event
(Port E) 8-bit port. Lower 2 bits are input port and upper 6 bits are output port. (8 pins)
Analog input pins to A/D converter. (12 pins)
(Port F) Lower 4 bits are input port and upper 4 bits are output port. Lower 4 bits also serve as standby release input pin. (8 pins)
Serial clock (CH0) I/O pin. Serial data (CH0) output pin. Serial data (CH0) input pin.
input pin for timer/counter.
PWM output pins. (2 pins)
DA gate pulse output pins. (4 pins)
Input pin to request external interruption. Active when falling edge.
CS0
Input
Serial chip select (CH0) input pin.
– 5 –
Symbol I/O Description
CXP87452/87460
PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0
/PMI PG5/SYNC1 PG6/EXI0 PG7/EXI1/
PMSK
PH0 to PH7
PI0/PCK /OSCI
PI1/PO PI2/PWM PI3/TO
PI4/INT1 PI5/SCK1
PI6/SO1 PI7/SI1
Input/input Input/input Input/input Input/input
Input/input/input Input/input
Input/input Input/input/input
Output
Input/input/input
I/O/output I/O/output I/O/output
I/O/input I/O/I/O
I/O/output I/O/input
Capstan FG input pin. Drum FG input pin. Drum PG input pin. Playback CTL pulse input pin.
(Port G) 8-bit input port. (8 pins)
Composite sync signal input pin.
Measuring pulse signal input pin of pulse cycle measuring unit.
External input pin to FRC capture unit.
Measuring enable signal input pin of pulse cycle measuring unit.
(Port H) 8-bit output port; large current, N-ch open drain output. (8 pins)
Connecting pin of crystal oscillation circuit for general purpose prescaler. (Mask option)
(Port I) Lower 1 bit is
External clock input pin of general purpose prescaler.
General purpose prescaler output pin.
input port (mask option) and upper 7 bits
14-bit PWM output pin. Timer/counter, output pin. (duty = 50%)
are I/O port. I/O port can be specified by bit unit.
Input pin to request external interruption. Active when falling edge.
Serial clock (CH1) I/O pin.
(8 pins)
Serial data (CH1) output pin. Serial data (CH1) input pin.
PJ0 to PJ7
I/O
(Port J) 8-bit I/O port. Function as standby release input can be specified by bit unit. I/O can be specified by bit unit.
– 6 –
Symbol I/O Description
PK0/OSCO
EXTAL
Input/output
Input
Input port. (Mask option)
Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input
XTAL
Output
opposite phase clock to XTAL pin.
System reset pin of active "L" level. RST pin is I/O pin, which output
RST
I/O
"L" level by incorporated power on reset function when power on. (Mask option)
CXP87452/87460
Connecting pin of crystal oscillation circuit for general purpose prescaler. (Mask opiton)
MP AVDD AVREF AVSS VDD VSS
Input
Input
Microprocessor mode input pin. Always connect to GND. Positive power supply pin of A/D converter. Reference voltage input pin of A/D converter. GND pin of A/D converter. Positive power supply pin. GND pin. Connect both Vss pins to GND.
– 7 –
Input/Output Circuit Format for Pins
Pin When resetCircuit format
PA0/PPO000 /PPO100
to PA7/PPO007 /PPO107
Port A Port B
PPO0 data PPO1 data
CXP87452/87460
PB4/PPO012 /PPO112
to PB5/PPO013 /PPO113
10 pins
PB0/PPO008
to PB3/PPO011
PB6/PPO014
to PB7/PPO015
6 pins
PC0/PPO016
to
PC2/PPO018 PC3/RTO3
to
PC7/RTO7
Data bus
Port B
Data bus
Port C
Port A or Port B
RD
PPO0 data
Port A or Port B
RD
PPO, RTO data
Port C data
Port C direction
Output becomes active from high impedance by data writing to port register.
Output becomes active from high impedance by data writing to port register.
Input protection circuit
IP
(Every bit)
Hi-Z
Hi-Z
Hi-Z
8 pins
PD0
to
PD7
8 pins
Data bus
Port D
Data bus
RD (Port C)
Port D data
Port D direction
RD (Port D)
– 8 –
(Every 4 bits)
PD0 to 3 PD4 to 7
IP
Large current 12mA
Hi-Z
A
A
AAA
AAA
AAA
Pin When resetCircuit format
CXP87452/87460
PE1/EC/INT2
1 pin
PE0/INT0 /XOUT
1 pin
PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1
Port E
Port E
Data bus
Port E
DA gate output or PWM output
PS1
OSCO
Port E function select register
Hi-Z control
1/2
RD (Port E)
Port E data
Port E function select register
AA
Schmitt input
IP
MPX
A
MPX
A
RD (Port E)
Data bus
To interruption circuit
Hi-Z
IP
Hi-Z
Hi-Z
4 pins
PE6/DAB0 PE7/DAB1
2 pins
Data bus
Port E
Data bus
RD (Port E)
DA gate output
Hi-Z control
Port E data
Port E function select register
RD (Port E)
MPX
H level
– 9 –
Pin When resetCircuit format
CXP87452/87460
AN0
to
AN3
4 pins
PF0/AN4
to
PF3/AN7
4 pins
PF4/AN8
to
PF7/AN11
Port F
Port F
Data bus
Port F data
Input multiplexer
IP
Input multiplexer
IP
RD (Port F)
A/D converter
Data bus
A/D converter
IP
Hi-Z
Hi-Z
Hi-Z
4 pins
PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0/PMI PG5/SYNC1 PG6/EXI0 PG7/EXI1/PMSK
8 pins
PH0
to
PH7
8 pins
RD (Port F)
Port/AD select
Input multiplexer
A/D converter
Port G
Schmitt input
IP
RD (Port G)
Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt input can be selected with the mask option.
Pulse cycle measurement unit input Servo input
Data bus
Port H
Port H data
Data bus
RD (Port H)
Large current 12mA
Hi-Z
Hi-Z
– 10 –
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