Sony CXP87360, CXP87352 Datasheet

CXP87352/87360

CMOS 8-bit Single Chip Microcomputer

Description

The CXP87352/87360 is a CMOS 8-bit micro­computer which consists of A/D converter, serial
interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, VISS/VASS
circuit, 32kHz timer/event counter, remote control
receiving circuit, general purpose prescaler, HSYNC
counter, VCR vertical sync separation circuit and the
measurement circuit which measure signals of
capstan FG and drum FG/PG and other servo
systems, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.

Also the CXP87352/87360 provides sleep/stop
function which enables to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.

100 pin QFP (PIastic) 100 pin LQFP (PIastic)

Structure

Silicon gate CMOS IC

Features

• A wide instruction set (213 instructions) which cover various types of data

— 16-bit operation/multiplication and division/boolean bit operation instructions

• Minimum instruction cycle 250ns at 16MHz operation

333ns at 12MHz operation
122µs at 32kHz operation

• Incorporated ROM capacity 52K bytes (CXP87352), 60K bytes (CXP87360)

• Incorporated RAM capacity 2048 bytes

• Peripheral functions

— A/D converter 8-bit, 12-channel, successive approximation system

(Conversion time 20.0µs/16MHz)

— Serial Interface Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel

Incorporated 8-bit and 8-stage FIFO for data
(1 to 8 bytes auto transfer) 1-channel

— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,

32kHz timer/counter

— High precision timing pattern generator PPG 19-pin 32-stage programmable

RTG 5-pin 2-channel

— PWM/DA gate output PWM 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)

DA gate pulse output 13-bit, 4-channel
— Servo input control Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14-bit, 1-channel
— VISS/VASS circuit Pulse duty auto detection circuit
— Remote control receiving circuit 8-bit pulse measurement counter with on-chip, 6-stage FIFO
— General purpose prescaler 7-bit (SYNC1 input frequency divided, FRC capture possible)
— HSYNC counter 12-bit event counter (Counts SYNC1 input.)

• Interruption 22 factors, 15 vectors, multi-interruption possible

• Standby mode SLEEP/STOP

• Package 100-pin plastic QFP/LQFP

• Piggyback/evaluation chip CXP87300 100-pin ceramic QFP/LQFP

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94415-PS

CXP87352/87360

Vss
V

DD

MP
RST
XTAL

EXTAL
TX

TEX

PE1/INT2
PI4/INT1/NMI
PE0/INT0

AVss

PA0 to PA7
8

PORT A

CLOCK

GENERATOR/

SYSTEM CONTROL

SPC700

CPU CORE

NMI

2

PB0 to PB7
8

PORT B

RAM

PC0 to PC7

8

PORT C

PE0/CKOUT

PD0 to PD7
8

PORT D

RAM

2048 BYTES

ROM

52K/60K BYTES

INTERRUPT CONTROLLER

2

FIFO

PE0 to PE1

PE2 to PE7

2

6

PORT E

2

PF4 to PF7

PF0 to PF3

4

4

PORT F

PRESCALER/

TIME BASE TIMER

2
2

PG0 to PG7
8

PORT G

32kHz

TIMER/COUNTER

FIFO

FRC

CAPTURE UNIT

3

FIFO

PH0 to PH7
8

PORT H

2

PORT I

PULSE

REALTIME

GENERATOR

PJ0 to PJ7
8

PI1 to PI7
7

RAM

PATTERN

GENERATOR

PROGRAMMABLE

2

PORT J

CH1

CH0

4

PC7/RTO7

5

19

to

PC3/RTO3

PC2/PPO18

to

PA0/PPO0

AV

REF

AV

DD

AN0 to AN3

Block Diagram

A/D CONVERTER

SERIAL

12

CS0

PF0/AN4

PF7/AN11

to

(CH0)

SERIAL

SO0

SCK0

INTERFACE UNIT

PI7/SI1

PI6/SO1

INTERFACE UNIT

SI0

(CH1)

8 BIT TIMER 1

8 BIT TIMER/COUNTER 0

PE1/EC

PI5/SCK1

PI3/TO/DDO

SERVO INPUT

VSYNC SEPARATOR

DRUM

CAPSTAN

PG1/DFG

PG0/CFG

PG7/EXI1

PG6/EXI0

PG5/SYNC1

PG4/SYNC0

– 2 –

CONTROL

CTL

PG2/DPG

PG3/PBCTL

VISS/VASS

REMOCON INPUT

PI1/RMC

14 BIT PWM GENERATOR

PI2/PWM

HSYNC COUNTER

12 BIT PWM GENERATOR CH1

12 BIT PWM GENERATOR CH0

PE6/DAB0

PE4/DAA0

PE2/PWM0

PROGRAMMABLE PRESCALER

PE7/DAB1

PE5/DAA1

PE3/PWM1

PI3/ADJ

PE1/HCOUT

Pin Configuration 1 (Top View) 100-pin QFP package

PA0/PPO000/PPO100

PB7/PPO015

PB6/PPO014

PA1/PPO001/PPO101

PA2/PPO002/PPO102

PA5/PPO005/PPO105

PA3/PPO003/PPO103

PA6/PPO006/PPO106

PA4/PPO004/PPO104

option

Mask

DD

Vpp

V

SS

PK0/OSCO

V

PA7/PPO007/PPO107

PI1/PO

PI2/PWM

PI3/TO

PI0/PCK/OSCI

PI4/INT1

PI5/SCK1

CXP87352/87360

PB5/PPO013/PPO113
PB4/PPO012/PPO112

PB3/PPO011
PB2/PPO010
PB1/PPO009
PB0/PPO008

PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3

PC2/PPO018

PC1/PPO017
PC0/PPO016

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

95

93

94

92

39

40

91

90

41

97

96

98

100

99

1

2
3
4
5
6
7
8
9

31

32

33

34

35

36

37

38

42

89

88

43

44

87

86

45

46

85

47

84

83

48

82

49

50

81

80
79
78
77

75
74
73
72

68
67
66
65
64
63
62
61
60
59
58

56
55

52
51

76

71
70
69

57

54
53

PI6/SO1
PI7/SI1
PE0/INT0/XOUT
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PF2/DPG
PG3/PBCTL
PG4/SYNC0/PMI
PG5/SYNC1
PG6/EXI0
PG7/EXI1/PMSK
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7

AV

DD

AVREF
AVSS
PF4/AN8

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

MP

RST

V

XTAL

CS0

EXTAL

SI0

SS

Note) 1. NC (Pin 90) is always connected to VDD.

2. Vss (Pins 41 and 88) are both connected to GND.

– 3 –

SO0

SCK0

PF7/AN11

PF6/AN10

PF5/AN9

Pin Configuration 2 (Top View) 100-pin LQFP package

NC

PA7/PPO7

PA6/PPO6

PA5/PPO5

PA4/PPO4

PA3/PPO3

PA2/PPO2

PA1/PPO1

PA0/PPO0

PB7/PPO15

PB6/PPO14

PB5/PPO13

PB4/PPO12

CXP87352/87360

SS

DD

V

TX

V

TEX

PI2/PWM

PI1/RMC

PI5/SCK1

PI4/INT1/NMI

PI3/TO/DDO/ADJ

PI7/SI1

PI6/SO1

PE0/INT0/CKOUT

PB3/PPO11
PB2/PPO10

PB1/PPO9
PB0/PPO8
PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4

PC3/RTO3
PC2/PPO18
PC1/PPO17
PC0/PPO16

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5
PD4
PD3

100

99

98

1

2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19

20
21
22

23

24
25

27

28

26

95

93

94

96

97

30

31

29

92

32

33

34

89

88

91

90

35

36

87

37

38

39

84

86

85

40

41

42

81

82

83

43

80

78

79

46

45

44

47

76

77

75
74
73
72

71
70
69

68
67

66
65
64
63
62
61

60
59
58
57
56
55
54
53
52
51

49

48

50

PE1/EC/INT2/HCOUT
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0
PG5/SYNC1
PG6/EXI0
PG7/EXI1
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AV

DD

AVREF

SS

MP

PD2

PD1

PD0

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

RST

V

XTAL

EXTAL

Note) 1. NC (Pin 88) is always connected to VDD.

2. Vss (Pins 39 and 86) are both connected to GND.

– 4 –

CS0

SI0

SO0

SCK0

PF5/AN9

PF6/AN10

PF7/AN11

SS

AV

PF4/AN8

Pin Description

Symbol I/O Description

(Port A)

PA0/PPO0

to

PA7/PPO7

Output/
Real time
output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

(Port B)

PB0/PPO8

to

PB7/PPO15

Output/
Real time
output

8-bit output port. Data is
gated with PPO contents by
OR-gate and they are output.
(8 pins)

PC0/PPO16

to

PC2/PPO18

I/O/
Real time
output

(Port C)
8-bit I/O port, enables to
specify I/O by bit unit.
Data is gated with PPO or

PC3/RTO3

to

PC7/RTO7

I/O/
Real time
output

RTO contents by OR-gate
and they are output.
(8 pins)

CXP87352/87360

Programmable pattern generator (PPG)
output.
Functions as high precision real time
pulse output port.
(19 pins)
PB0 and PB2 can be 3-state controlled
with PPG.

Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)

PD0 to PD7

PE0/INT0/
CKOUT

PE1/EC/INT2/
HCOUT

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
AN0 to AN3
PF0/AN4

to

PF3/AN7
PF4/AN8

to

PF7/AN11

I/O

Input/Input/Output

Input/Input/Input/
Output

Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Input

Input/Input

Output/Input

(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current.
(8 pins)

Input pin to request external interruption.
Active when falling edge.

PC3 can be 3-state controlled with RTG.

System clock frequency division output.
(Port E)
8-bit port.
Lower 2 bits
are input pins
and upper 6
bits are output
pins.

External event
input pin for
timer/counter.

Input pin to request
external interruption.
Active when falling edge.

PWM output pins.
(2 pins)

Coinsidence
signal output of
HSYNC counter.

(8 pins)

DA gate pulse output pins.
(4 pins)

Analog input pins to A/D converter. (12 pins)

(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)

SCK0
SO0
SI0
CS0

I/O
Ouput
Input
Input

Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.
Serial data (CH0) input pin.
Serial chip select (CH0) input pin.

– 5 –

Symbol I/O Description

CXP87352/87360

PG0/CFG
PG1/DFG
PG2/DPG

PG3/PBCTL
PG4/SYNC0

PG5/SYNC1
PG6/EXI0
PG7/EXI1

PH0 to PH7

PI1/RMC
PI2/PWM
PI3/TO/

DDO/ADJ
PI4/INT1/

NMI
PI5/SCK1

Input/Input
Input/Input
Input/Input

Input/Input
Input/Input

Input/Input
Input/Input
Input/Input

Output

I/O/Input
I/O/Output
I/O/Output/

Output/Output
I/O/Input/Input
I/O/I/O

Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.

(Port G)
8-bit input port.

Playback CTL pulse input pin.
External event input pin of timer/counter.

(8 pins)

Composite sync signal input pin.

External input pin to FRC capture unit.

(Port H)
8-bit output port ; Medium withstand voltage (12V) and high current
(12mA), N-ch open drain output.
(8 pins)

Remote control receiving circuit input pin.
14-bit PWM output pin.

(Port I)
7-bit I/O port.
I/O port can be
specified by bit
unit.
(7 pins)

Timer/counter, CTL duty detection, 32kHz oscillation
adjustment output pin.

Input pin to request external interruption and
non-maskable interruption. Active when falling edge.

Serial clock (CH1) I/O pin.
PI6/SO1
PI7/SI1

PJ0 to PJ7

EXTAL
XTAL
TEX
TX

RST
MP
AVDD
AVREF
AVss
VDD
Vss

I/O/Output
I/O/Input

I/O

Input
Output
Input
Output

Input
Input

Input

Serial data (CH1) output pin.

Serial data (CH1) input pin.

(Port J)
8-bit I/O port. Function as standby release input can be specified by bit
unit. I/O can be specified by bit unit.

Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.

Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open. (Feedback
resistor is not removed.)

System reset pin of active "L" level.
Microprocessor mode input pin. Always connect to GND.
Positive power supply pin of A/D converter.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
Positive power supply pin.
GND pin. Connect both Vss pins to GND.

– 6 –

AAA

A

Input/Output Circuit Formats for Pins

CXP87352/87360

Pin

PA0 /PPO0

to

PA7/PPO7
PB4/PPO12

to

PB7/PPO15

12 pins

PB0 /PPO8
PB2/PPO10

Port A
Port B

Data bus

PPO data

Port A or Port B

RD

PPO8 or PPO10

PB0 or PB2 data

Circuit format

Output becomes active from high
impedance by data writing to port register.

When reset

Hi-Z

Hi-Z

2 pins

PB1/PPO9
PB3/PPO11

2 pins

Data bus

Output becomes active from high impedance
by data writing to port register.

PPO9 or PPO11

PPG contorl
status register
bit 0

AAA

3-state control selection

PPO9 or PPO11

PB1 or PB3 data

Data bus

RD

RD

Hi-Z

Output becomes active from high
impedance by data writing to port register.

– 7 –

CXP87352/87360

AAA

A

AAA

AAA

AAA

AAA

PC0/PPO16

to

PC2/PPO18
PC5/RTO5

to

PC7/RTO7

6 pins

Port C

Data bus

Data bus

PPO, RTO data

Port C data

Port C direction

RD (Port C)

RD (Port C direction)

RTO3

PC3 data

Circuit format

(Every bit)

When resetPin

Input
protection
circuit

IP

Hi-Z

PC3/RTO3

1 pin

PC4/RTO4

PC3 direction

Data bus

RD

Data bus

RD

RTG interruption
control register

AAA

bit 7
3-state control selection

PC4 data

PC4 direction

Data bus

RD

Data bus

Hi-Z

RTO4

RTO4

Hi-Z

RTO data is OR-gate data of ch0 and ch1.

RD

1 pin

– 8 –

CXP87352/87360

PD0

to

PD7

8 pins

Port D

Data bus

Port E

Port E/PWM
selection register
bit 0, 1

Port D data

Port D direction

RD (Port D)

Circuit format

(Every 4 bits)

PD0 to 3
PD4 to 7

IP

Large
current
12mA

When resetPin

Hi-Z

PE0/INT0/
CKOUT

1 pin

PE1/EC/INT2

Data bus

Port E

From
HSYNC counter

RD

Data bus

PS1
PS2
PS3

Interruption circuit

Hi-Z control

HCOUT

MPX

RD (Port E)

IP

IP

Input
protection
circuit

Input
protection
circuit

Hi-Z

Hi-Z

1 pin

Interruption circuit/
event counter

– 9 –

CXP87352/87360

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1

4 pins

PE6/DAB0
PE7/DAB1

Port E

Data bus

Port E

DA gate output
or PWM output

Hi-Z control

Port E data

Port/DA output
select

RD (Port E)

DA gate output

Hi-Z control

Port E data

Port/DA output
select

Circuit format

MPX

MPX

When resetPin

Hi-Z

H level

2 pins

AN0

to

AN3

4 pins

PF0/AN4

to

PF3/AN7

4 pins

Data bus

Port F

RD (Port E)

Input multiplexer

IP

Input multiplexer

IP

RD (Port F)

Data bus

A/D converter

A/D converter

Hi-Z

Hi-Z

– 10 –