Sony CXP87132, CXP87140 Datasheet

Description

The CXP87132/87140 is a CMOS 8-bit microcomputer
which consists of A/D converter, serial interface (2ch
independently), timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit (PPG 2ch independently, RTG 2ch independently),
PWM generator, general purpose prescaler, PWM for
tuner, VCR vertical sync separation circuit and the
measuring circuit which measure signals of capstan
FG and drum FG/PG and other servo systems, as
well as basic configurations like 8-bit CPU, ROM,
RAM and I/O port. They are integrated into a single
chip.

Also the CXP87132/87140 provides power on reset
function, sleep/stop function which enables to lower
power consumption.

Features

• A wide instruction set (213 instructions) which covers various types of data

— 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction

• Minimum instruction cycle During operation 333ns/12MHz (3.0 to 5.5V)

During operation 250ns/16MHz (4.5 to 5.5V)

• Incorporated ROM capacity 32K bytes (CXP87132)

40K bytes (CXP87140)

• Incorporated RAM capacity 1312 bytes

• Peripheral functions

— A/D converter 8-bit, 12-channel, successive approximation system

(Conversion time: 20µs/16MHz)

— Serial I/O Incorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel

Incorporated 8-bit and 8-stage FIFO

(1 to 8 bytes auto transfer) 1-channel
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer
— High precision timing pattern generator PPG 19 pins 32-stage programmable

PPG 10 pins 21-stage programmable

RTG 5 pins 2-channel
— PWM/DA gate output PWM 12-bit, 2-channel (Repetitive frequency 62.5kHz/16MHz)

DA gate pulse 12-bit, 4-channel
— Servo input control Capstan FG, Drum FG/PG, CTL input
— VSYNC separator
— FRC capture unit Incorporated 26-bit and 8-stage FIFO
— PWM output 14-bit, 1-channel
— General purpose prescaler 10-bit (System clock asynchronous)
— Pulse cycle measuring circuit

• Interruption 18 factors, 14 vectors, multi-interruption possible

• Standby mode Sleep/stop

• Package 100-pin plastic QFP/LQFP

• Piggyback/evaluation chip CXP87100 100-pin ceramic QFP/LQFP

CMOS 8-bit Single Chip Microcomputer

– 1 –

E93631A7Z-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXP87132/87140

100 pin QFP (PIastic) 100 pin LQFP (PIastic)

Structure

Silicon gate CMOS IC

– 2 –

CXP87132/87140

A/D CONVERTER

SERIAL

INTERFACE UNIT

(CH0)

BUFFER

RAM

INTERRUPT CONTROLLER

SPC700

CPU CORE

ROM

32K/40K BYTES

PRESCALER/

TIME BASE TIMER

RAM

1312 BYTES

CLOCK

GENERATOR/

SYSTEM CONTROL

12

AN0 to AN3

SI0

CS0

PI7/SI1

SCK0

AV

DD

PE1/INT2

EXTAL

XTAL

V

DD

Vss

PORT C

8

PC0 to PC7

PORT D

8

PD0 to PD7

PORT I

PI1 to PI7

RST

PORT J

8

PJ0 to PJ7

PORT G

8

PG0 to PG7

PORT H

8

PH0 to PH7

PORT A

8

PA0 to PA7

PORT E

2

6

PE0 to PE1

PE2 to PE7

REALTIME

PULSE

GENERATOR

2

PF0/AN4

to

PF7/AN11

2

PE0/INT0

FRC

CAPTURE

UNIT

FIFO

RAM

CH0

CH1

19

5

2

PORT B

8

PB0 to PB7

PORT F

PF0 to PF3

4

4

PF4 to PF7

AV

REF

AVss

MP

PI4/INT1

PORT K

1

PK0

PROGRAMMABLE

PATTERN

GENERATOR (CH1)

RAM

10

2

3

2

4

4

2

2

SERIAL

INTERFACE UNIT

(CH1)

FIFO

8BIT TIMER/COUNTER 0

8BIT TIMER 1

V SYNC SEPARATOR

CAPSTAN

DRUM

CTL

SERVO INPUT

CONTROL

PROGRAMMABLE PRESCALER

14BIT PWM GENERATOR

12BIT PWM GENERATOR CH0

12BIT PWM GENERATOR CH1

PULSE MEASURE UNIT

SO0

PI6/SO1

PI5/SCK1

PE1/EC

PI3/TO

PG4/SYNC0

PG5/SYNC1

PG6/EXI0

PG7/EXI1

PG0/CFG

PG1/DFG

PG2/DPG

PG3/PBCTL

PI0/PCK/OSCI

PK0/OSCO

PI1/PO

PE0/XOUT

PE2/PWM0

PE4/DAA0

PE6/DAB0

PE3/PWM1

PE5/DAA1

PE7/DAB1

PG4/PMI

PG7/PMSK

PI2/PWM

1

7

PI0

PPO100

to

PPO107

PPO112

to

PPO113

RTO3

to

RTO7

PPO000 to PPO018

19

10

PROGRAMMABLE

PATTERN

GENERATOR (CH0)

Block Diagram

– 3 –

CXP87132/87140

PI6/SO1
PI7/SI1
PE0/INT0/XOUT
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PF2/DPG
PG3/PBCTL
PG4/SYNC0/PMI
PG5/SYNC1
PG6/EXI0
PG7/EXI1/PMSK
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AV

DD

AVREF
AVSS
PF4/AN8

PB5/PPO013/PPO113
PB4/PPO012/PPO112

PB3/PPO011
PB2/PPO010
PB1/PPO009
PB0/PPO008

PC7/RTO7

PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3

PC2/PPO018

PC1/PPO017
PC0/PPO016

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5

PD4
PD3
PD2
PD1
PD0

PB6/PPO014

PB7/PPO015

PA0/PPO000/PPO100

PA1/PPO001/PPO101

PA2/PPO002/PPO102

PA3/PPO003/PPO103

PA4/PPO004/PPO104

PA5/PPO005/PPO105

PA6/PPO006/PPO106

PA7/PPO007/PPO107

NC

V

DD

V

SS

PK0/OSCO

PI0/PCK/OSCI

PI1/PO

PI2/PWM

PI3/TO

PI4/INT1

PI5/SCK1

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

MP

RST

V

SS

XTAL

EXTAL

CS0

SI0

SO0

SCK0

PF7/AN11

PF6/AN10

PF5/AN9

Mask

option

81

82

83

84

88

87

86

85

89

90

100

99

98

97

96

95

94

91

92

93

51

52

53

54

55

56

57

58

59

60

70
69
68
67

63

64

65

66

61

62

71

72

73

74

75

76

77

78

79

80

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

2
3
4
5
6
7
8
9

10

11
12
13
14
15
16

17
18
19

20

21

22

23

24

25

26

27

28

29
30

1

Pin Configuration 1 (Top View) 100 pin QFP Package

Note) 1. NC (Pin 90) is always connected to VDD.

2. Vss (Pins 41 and 88) are both connected to GND.
– 4 –

CXP87132/87140

Pin Configuration 2 (Top View) 100 pin LQFP Package

PI6/SO1

PI7/SI1

PE0/INT0/XOUT

PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
PG0/CFG
PG1/DFG
PF2/DPG
PG3/PBCTL
PG4/SYNC0/PMI
PG5/SYNC1
PG6/EXI0
PG7/EXI1/PMSK
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6

PB3/PPO011
PB2/PPO010
PB1/PPO009

PB0/PPO008

PC7/RTO7
PC6/RTO6
PC5/RTO5
PC4/RTO4
PC3/RTO3

PC2/PPO018
PC1/PPO017
PC0/PPO016

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0

PD7
PD6
PD5

PB6/PPO014

PB7/PPO015

PA0/PPO000/PPO100

PA1/PPO001/PPO101

PA2/PPO002/PPO102

PA3/PPO003/PPO103

PA4/PPO004/PPO104

PA5/PPO005/PPO005

PA6/PPO006/PPO106

PA7/PPO007/PPO107

NC

V

DD

V

SS

PK0/OSCO

PI0/PCL/OSCI

PI1/PO

PI2/PWM

PI3/TO

PI4/INT1

PI5/SCK1

PH2

PH1

PH0

MP

RST

V

SS

XTAL

EXTAL

CS0

SI0

SO0

SCK0

PF7/AN11

PF6/AN10

PF5/AN9

Mask

option

PH7

PH6

PH5

PH4

PH3

PD4
PD3

PD2

PD1

PD0

PF4/AN8

AV

SS

PF3/AN7
AV

DD

AVREF

PB4/PPO012/PPO112

PB5/PPO013/PPO113

51

52

53

54

55

56

57

58

59

60

70
69
68
67

63

64

65

66

61

62

71

72

73

74

75

76

77

78

79

80

81

82

83

84

88

87

86

85

89

90

100

99

98

97

96

95

94

91

92

93

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19

20
21
22

23
24
25

1

26 27

28

29

30

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

Note) 1. NC (Pin 88) is always connected to VDD.

2. Vss (Pins 39 and 86) are both connected to GND.

– 5 –

CXP87132/87140

Output/
Real time
output

Output/
Real time
output

I/O/
Real time
output

I/O/
Real time
output

I/O

Input/Input/Output

Input/Input/Input

Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Output/Output
Input

Input/Input

Output/Input

I/O
Ouput
Input
Input

(Port A)
8-bit output port. Data is gated
with PPO0 and PPO1 contents
by OR-gate and they are output.
(8 pins)

(Port B)
8-bit output port. Data is gated
with PPO0 and PPO1 contents
by OR-gate and they are output.
(8 pins)

(Port C)
8-bit I/O port. Enables to
specify I/O by a bit unit.
Data is gated with PPO or
RTO contents by OR-gate
and they are output.
(8 pins)

(Port D)
8-bit I/O port. Enable to specify I/O by 4-bit unit.
Enables to drive 12mA sink current. (During 5V ± 0.5V operation)
(8 pins)

(Port E)
8-bit port. Lower 2 bits are
input port and upper 6 bits
are output port.
(8 pins)

Analog input pins to A/D converter. (12 pins)

(Port F)
Lower 4 bits are input port and upper 4 bits are output port.
Lower 4 bits also serve as standby release input pin.
(8 pins)

Serial clock (CH0) I/O pin.
Serial data (CH0) output pin.
Serial data (CH0) input pin.
Serial chip select (CH0) input pin.

External event
input pin for
timer/counter.

Input pin to request
external interruption.
Active when falling edge.

Input pin to request
external interruption.
Active when falling edge.

1/2 dividing clock
output of XTAL
or OSCO.

PWM output pins.
(2 pins)

DA gate pulse output pins.
(4 pins)

Programmable pattern generator
(PPG0, PPG1) output.
Functions as high precision real time
pulse output port.

(

PPG0 19 pins

)

PPG1 10 pins

Real time pulse generator (RTG) output.
Functions as high precision real time
pulse output port. (5 pins)

Symbol I/O Description

PA0/PPO000
/PPO100

to
PA7/PPO007
/PPO107

PB0/PPO008

to
PB7/PPO015

PC0/PPO016

to
PC2/PPO018

PC3/RTO3

to
PC7/RTO7

PD0 to PD7

PE0/INT0
/XOUT

PE1/EC/INT2

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
PE6/DAB0
PE7/DAB1
AN0 to AN3
PF0/AN4

to
PF3/AN7

PF4/AN8

to
PF7/AN11

SCK0
SO0
SI0
CS0

Pin Description

– 6 –

CXP87132/87140

PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0

/PMI
PG5/SYNC1
PG6/EXI0
PG7/EXI1/

PMSK

PH0 to PH7

PI0/PCK
/OSCI

PI1/PO
PI2/PWM
PI3/TO

PI4/INT1
PI5/SCK1

PI6/SO1
PI7/SI1

PJ0 to PJ7

Input/Input
Input/Input
Input/Input
Input/Input

Input/Input/Input
Input/Input

Input/Input
Input/Input/Input

Output

Input/Input/Input

I/O/Output
I/O/Output
I/O/Output

I/O/Input
I/O/I/O

I/O/Output
I/O/Input

I/O

Capstan FG input pin.
Drum FG input pin.
Drum PG input pin.
Playback CTL pulse input pin.

Composite sync
signal input pin.

Measuring pulse signal input pin
of pulse cycle measuring unit.

Measuring enable signal input pin
of pulse cycle measuring unit.

(Port G)
8-bit input port.
(8 pins)

(Port H)
8-bit output port; large current, N-ch open drain output.
(8 pins)

External clock input
pin of general
purpose prescaler.

General purpose prescaler output pin.
14-bit PWM output pin.
Timer/counter output pin. (duty = 50%)
Input pin to request external interruption.

Active when falling edge.
Serial clock (CH1) I/O pin.
Serial data (CH1) output pin.
Serial data (CH1) input pin.

(Port I)
Lower 1 bit is
input port
(mask option)
and upper 7 bits
are I/O port.
I/O port can be
specified by a bit
unit.
(8 pins)

Symbol I/O Description

External input pin
to FRC capture
unit.

Connecting pin of crystal for
general purpose prescaler
oscillation circuit. (Mask option)

(Port J)
8-bit I/O port. Function as standby release input can be specified by a
bit unit. I/O can be specified by a bit unit.

– 7 –

CXP87132/87140

PK0/OSCO

RST

MP
AVDD
AVREF
AVSS
VDD
VSS

Input/Output

I/O

Input

Input

Connecting pin of crystal for system clock oscillation. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.

Input port. (Mask option)

System reset pin of active "L" level. RST pin is I/O pin, which outputs
"L" level by incorporated power on reset function when power on.
(Mask option)

Microprocessor mode input pin. Always connect to GND.
Positive power supply pin of A/D converter.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
Positive power supply pin.
GND pin. Connect both Vss pins to GND.

Connecting pin of crystal for
general purpose prescaler
oscillation circuit. (Mask opiton)

XTAL

EXTAL

Output

Input

Symbol I/O Description

– 8 –

CXP87132/87140

Pin When resetCircuit format

Port A
Port B

Port B

Port C

Port D

Hi-Z

Hi-Z

Hi-Z

Hi-Z

PA0/PPO000
/PPO100

to
PA7/PPO007
/PPO107

PB4/PPO012
/PPO112

to
PB5/PPO013
/PPO113

10 pins

PB0/PPO008

to
PB3/PPO011

PB6/PPO014

to
PB7/PPO015

6 pins

PC0/PPO016

to

PC2/PPO018
PC3/RTO3

to

PC7/RTO7

8 pins

PD0

to

PD7

8 pins

PPO0 data

Data bus

Output becomes active from high
impedance by data writing to port register.

Port A or Port B

RD

Input/Output Circuit Formats for Pins

PPO0 data
PPO1 data

Port A or Port B

Data bus

Output becomes active from high
impedance by data writing to port register.

RD

Data bus

PPO, RTO data

Port C data

Port C direction

Data bus

RD (Port C)

Port D data

Port D direction

(Every bit)

(Every 4 bits)

PD0 to PD3
PD4 to PD7

Input
protection
circuit

IP

IP

Large
current
12mA

RD (Port D)

– 9 –

CXP87132/87140

A

Port E

Port E

Port E

Port E

Hi-Z

Hi-Z

Hi-Z

High level

PE1/EC/INT2

1 pin

PE0/INT0
/XOUT

1 pin

PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1

4 pins

PE6/DAB0
PE7/DAB1

2 pins

Pin When resetCircuit format

Schmitt input

IP

Data bus

PS1

OSCO

Port E function
select register

RD (Port E)

DA gate output or
PWM output

Hi-Z control

Data bus

1/2

Port E data

Port E function
select register

MPX

RD (Port E)

MPX

Data bus

IP

To interruption
circuit

Data bus

DA gate output

Hi-Z control

Port E data

Port E function
select register

AA

RD (Port E)

RD (Port E)

MPX

– 10 –

CXP87132/87140

Port F

Port F

Port G

Hi-Z

Hi-Z

Hi-Z

Hi-Z

AN0

to

AN3

4 pins

PF0/AN4

to

PF3/AN7

4 pins

PF4/AN8

to

PF7/AN11

4 pins

PG0/CFG
PG1/DFG
PG2/DPG
PG3/PBCTL
PG4/SYNC0/PMI
PG5/SYNC1
PG6/EXI0
PG7/EXI1/PMSK

8 pins

Port H

Hi-Z

PH0

to

PH7

8 pins

IP

A/D converter

Input multiplexer

Pin When resetCircuit format

Input multiplexer

IP

RD (Port F)

A/D converter

Data bus

Port F data

Data bus

RD
(Port F)

Note) For PG4/SYNC0, PG5/SYNC1, CMOS schmitt input and TTL schmitt input
can be selected with the mask option.

Schmitt input

IP

Port/AD select

Input multiplexer

Pulse cycle measuring unit input
Servo input

Data bus

RD (Port G)

IP

A/D converter

Port H data

Data bus

RD (Port H)

Large current
12mA