Sony CXP832P40A Datasheet
CXP832P40A
CMOS 8-bit Single Chip Microcomputer
Description
The CXP832P40A is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, 32kHz timer/counter, capture timer counter,
LCD controller/driver, remote control reception
circuit and 14-bit PWM output besides the basic
configurations of 8-bit CPU, PROM, RAM, and I/O port.
Also the CXP832P40A provides sleep/stop function
which enables to lower power consumption.
The CXP832P40A is the PROM-incorporated
version of the CXP83240A with built-in mask ROM.
This provides the additional feature of being able to
write directry into the program. Thus, it is most
suitable for evaluation use during system
development and for small-quantity production.
100 pin QFP (Plastic) 100 pin LQFP (Plastic)
tructure
Silicon gate CMOS IC
Features
• Wide-range instruction system (213 instructions) to cover various types of data.
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle 400ns at 10MHz operation
8µs at 500kHz operation
122µs at 32kHz operation
• Incorporated PROM capacity 40K bytes
• Incorporated RAM capacity 1120 bytes (includes LCD display data area)
• Peripheral functions
— A/D converter 8-bit, 8-channel, successive approximation method
(Conversion time of 32µs/10MHz)
— Serial interface 8-bit, 8-stage FIFO incorporated
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit clock synchronized type, 1 channel
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,
16-bit capture timer/counter, 32kHz timer/counter
— LCD controller/driver Maximum 160 segment display possible (during 1/4 duty)
4 common output, 40 segment output
Display method static, 1/2, 1/3, 1/4 duty
Bias method 1/2, 1/3 bias
— Remote control reception circuit 8-bit pulse measurement counter with on-chip, 6-stage FIFO
— PWM output circuit 14 bits, 1 channel
• Interruption 15 factors, 15 vectors, multi-interruption possible
• Standby mode SLEEP/STOP
• Package 100-pin plastic QFP/LQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94X39-PP
CXP832P40A
V
SS
V
DD
RST
XTAL1
EXTAL1
XTAL2
EXTAL2
TX
TEX
PORT A
PB0 to PB7
8
PORT B
PA0 to PA7
8
CLOCK GEN/
SYSTEM CONTROL
SPC 700
CPU CORE
PC0 to PC7
8
PORT C
RAM
1120 BYTES
PROM
40K BYTES
PD0 to PD7
8
PE0 to PE4
5
PORT D
PE5 to PE6
2
PF0 to PF7
8
PORT E
32KHz
PRESCALER/
PG0 to PG7
8
PORT F
PORT GPORT H
TIMER/COUNTER
TIME BASE TIMER
PH0 to PH7
8
NMI/INT3
INT2
INT1
INT0
AV
REF
AV
SS
LCD
40
4
CONTROLLER/
A/D CONVERTER
8
VL
AN0 to AN7
COM0 to COM3
SEG0 to SEG39
DRIVER
VLC1
VLC2
VLC3
INTERRUPT CONTROLLER
2 2
FIFOREMOCON
14 BIT PWM GENERATOR
RMC
PWM
FIFO
UNIT 0
SERIAL
INTERFACE
SI0
CS0
SO0
SCK0
2
8 BIT TIMER 1
16 BIT CAPTURE
TIMER/COUNTER 2
8 BIT TIMER/COUNTER 0
SERIAL INTERFACE UNIT 1
SI1
SO1
SCK1
EC0
TO
EC1
CINT
2
ADJ
Block Diagram
– 2 –
Pin Assignment (Top View) (QFP package)
CXP832P40A
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5/PWM
PE6/TO/ADJ
PB0/CINT
PB1/ CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PA0/AN0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PE0/INT0/EC0
PE1/INT1/EC1
99
98
100
32
31
33
SEG37/PG5
SEG38/PG6
SEG39/PG7
96
97
35
36
34
SEG35/PG3
SEG36/PG4
95
94
37
38
93
TEX
39
92
TX
40
91
Vss
41
90
Vpp
42
89
DD
V
43
SEG33/PG1
SEG34/PG2
88
87
45
44
SEG31/PF7
SEG32/PG0
86
85
46
47
SEG29/PF5
SEG30/PF6
84
83
48
SEG28/PF4
81
82
49
50
SEG27/PF3
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG26/PF2
SEG25/PF1
SEG24/PF0
SEG23/PD7
SEG22/PD6
SEG21/PD5
SEG20/PD4
SEG19/PD3
SEG18/PD2
SEG17/PD1
SEG16/PD0
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
COM2
COM1
PA2/AN2
PA1/AN1
PA4/AN4
PA3/AN3
PA6/AN6
PA5/AN5
RST
PA7/AN7
XTAL1
EXTAL1
Vss
XTAL2
EXTAL2
REF
AV
AVss
Note) 1. Vpp (Pin 90) is always connected to VDD.
2. VSS (Pin 41 and 91) are both connected to GND.
– 3 –
L
V
LC3
V
LC2
V
LC1
V
COM0
Pin Assignment (Top View) (LQFP package)
CXP832P40A
PE4/RMC
PE5/PWM
PE6/TO/ADJ
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PH0
PH1
PH2
PH3
PH4
PH5
PE3/INT3/NMI
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PE1/INT1/EC1
PE2/INT2
99
98
SEG39/PG7
PE0/INT0/EC0
95
96
97
SEG36/PG4
SEG37/PG5
SEG38/PG6
93
94
TEX
SEG35/PG3
92
91
90
TX
89
Vss
88
Vpp
87
DD
SEG34/PG2
V
86
85
SEG31/PF7
SEG32/PG0
SEG33/PG1
84
82
83
SEG28/PF4
SEG29/PF5
SEG30/PF6
81
80
SEG26/PF2
SEG27/PF3
78
79
SEG24/PF0
SEG25/PF1
76
77
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG23/PD7
SEG22/PD6
SEG21/PD5
SEG20/PD4
SEG19/PD3
SEG18/PD2
SEG17/PD1
SEG16/PD0
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM3
26
PH6
27
28
PH7
30
29
PA1/AN1
PA0/AN0
32
31
PA3/AN3
PA2/AN2
33
34
PA5/AN5
PA4/AN4
36
PA7/AN7
PA6/AN6
37
RST
EXTAL1
38
39
Vss
XTAL1
40
41
XTAL2
EXTAL2
42
35
Note) 1. Vpp (Pin 88) is always connected to VDD.
2. VSS (Pin 39 and 89) are both connected to GND.
– 4 –
REF
AV
43
44
AVss
46
45
L
V
LC2
LC3
V
V
47
LC1
V
48
49
COM1
COM0
50
COM2
Pin Description
Symbol I/O Functions
(Port A)
8-bit I/O port. I/O can
PA0/AN0
to
PA7/AN7
I/O/Analog input
be set in a single bit
unit.
Incorporation of pull-up
resistor can be set
Analog inputs to A/D converter.
(8 pins)
through the software in
a unit of 4 bits. (8 pins)
CXP832P40A
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PE0/INT0/
EC0
PE1/INT1/
EC1
PE2/INT2
PE3/INT3/
NMI
PE4/RMC
I/O/Input
I/O/Input
I/O/I/O
I/O/Input
I/O/Output
I/O/I/O
I/O/input
I/O/Output
I/OPC0 to PC7
Input/Input/Input
Input/Input/Input
Input/Input
Input/Input/Input
Input/Input
External capture input to 16-bit timer/counter.
(Port B)
Chip select input for serial interface (CH0).
8-bit I/O port. I/O can
be set in a single bit
unit.
Serial clock I/O (CH0).
Serial data input (CH0).
Incorporation of pull-up
resistor can be set
through the software in
Serial data output (CH0).
Serial clock I/O (CH1).
a unit of 4 bits.
(8 pins)
Serial data input (CH1).
Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can be set in a single bit unit. Capable of driving 12mA
sync current. Incorporation of pull-up resistor can be set through the
software in a unit of 4 bits.
(8 pins)
External event inputs for
timer/counter.
(2 pins)
(Port E)
7-bit port. lower 5 bits
are for inputs; upper
2 bits are for outputs.
(7 pins)
External interruption request inputs.
(4 pins)
Non-maskable interruption request
input.
Remote control reception circuit input.
PE5/PWM
PE6/TO/
ADJ
PH0 to PH7
Output/Output
Output/Output/
Output
I/O
14-bit PWM output.
Rectangular wave output
for 16-bit timer/counter
(duty output 50%).
Output for 32kHz
oscillation
frequency division.
(Port H)
8-bit I/O port. I/O can be set in a single bit unit. Incorporation of pull-up
resistor can be set through the software in a unit of 4 bits.
(8 pins)
– 5 –
Symbol I/O Functions
PD0/SEG16
to
PD7/SEG23
Output/Output
(Port D)
8-bit output port.
(8 pins)
CXP832P40A
PF0/SEG24
to
PF7/SEG31
PG0/SEG32
to
PG7/SEG39
SEG0 to SEG15
COM0 to COM3
VLC1 to VLC3
VL
EXTAL1
XTAL1
EXTAL2
XTAL2
TEX
Output/Output
Output/Output
Output
Output
Output
Input
Input
Input
OutputTX
(Port F)
8-bit output port.
LCD segment signal output.
(8 pins)
(port G)
8-bit output port.
(8 pins)
LCD segment signal output.
LCD common signal output.
LCD bias power supply.
Control pin to cut off the current flowing to external LCD bias resistor
during standby.
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL1; opposite phase clock should be
input to XTAL1. System clock oscillation of EXTAL1 and XTAL1 is used
for normal operation mode (Max. 10MHz).
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL2; opposite phase clock should be
input to XTAL2. System clock oscillation of EXTAL2 and XTAL2 is used
for sub clock mode (Typ. 500kHz).
Crystal connectors for 32kHz timer/counter clock generation circuit.
Connect a 32.768kHz crystal oscillator between TEX and TX. For usage
as event input, connect clock oscillation source to TEX, and leave TX
open.
RST
Vpp
AVREF
AVSS
VDD
VSS
Input
Input
Low-level active system reset.
Positive power supply for built-in PROM writing.
Under normal operating conditions, connect to VDD.
Reference voltage input for A/D converter.
A/D converter GND.
Positive power supply.
GND. Two VSS are connected to GND.
– 6 –
I/O Circuit Format for Pins
CXP832P40A
Pin
PA0/AN0
to
PA7/AN7
8 pins
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Port A
Port B
Data bus
Data bus
Circuit format
Pull-up resistor
"0" when reset
Port A data
Port A direction
"0" when reset
RD (Port A)
Port A input selection
"0" when reset
Pull-up resistor
"0" when reset
Port B data
Port B direction
"0" when reset
A/D converter
Input multiplexer
Schmitt input
∗
IP
Input protection
circuit
∗
Pull-up transistors
approx. 100kΩ
∗
IP
When reset
Hi-Z
Hi-Z
4 pins
PB2/SCK0
PB5/SCK1
2 pins
Port B
Pull-up resistor
"0" when reset
Port B output selection
"0" when reset
Port B direction
"0" when reset
Data
bus
RD (Port B)
RD (Port B)
SCK OUT
Output enable
Port B data
SCK in
CINT
CS0
SI0
SI1
∗
Pull-up transistors
approx. 100kΩ
Schmitt input
∗ Pull-up transistors
approx. 100kΩ
∗
Hi-Z
IP
– 7 –
CXP832P40A
Pin
PB4/SO0
PB7/SO1
2 pins
Port B
Pull-up resistor
"0" when reset
Port B output selection
"0" when reset
Port B direction
"0" when reset
Data
bus
RD (Port B)
Port C
Output enable
Port B data
SO
Pull-up resistor
"0" when reset
Port C data
Circuit format
∗
Pull-up transistors
approx. 100kΩ
∗
2
When reset
∗
Hi-Z
IP
PC0 to PC7
8 pins
PE0/INT0/EC0
PE1/INT1/EC1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
5 pins
Port E
Data bus
Port C direction
"0" when reset
RD (Port C)
Schmitt input
IP
RD (Port E)
∗
1
IP
∗
1 Large currentt drive
of 12mA possible
∗
2 Pull-up transistors
approx. 100kΩ
INT0/EC0
INT1/EC1
INT2
INT3/NMI
RMC
Data bus
Hi-Z
Hi-Z
– 8 –
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