Sony CXP81960M, CXP81952M Datasheet

Description
The CXP81952M/81960M is a CMOS 8-bit micro­computer which consists of A/D converter, serial interface, timer/counter, time base timer, vector interruption, high precision timing pattern generation circuit, PWM generator, PWM for tuner, 32kHz timer/event counter, remote control reception circuit, and FRC capture unit, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip.
Also the CXP81952M/81960M provides sleep/stop functions which enable to lower power consumption and ultra-low speed instruction mode in 32kHz operation.
Features
A wide instruction set (213 instructions) which covers various types of data
— 16-bit operation/multiplication and division/Boolean bit operation instructions
Minimum instruction cycle 200ns at 20MHz operation (4.5 to 5.5V)
333ns at 12MHz operation (2.7 to 5.5V) 122µs at 32kHz operation
Incorporated ROM capacity 52K bytes (CXP81952M), 60K bytes (CXP81960M)
Incorporated RAM capacity 2048 bytes
Peripheral functions
— A/D converter 8 bits, 12 channels, successive approximation system
(Conversion time of 16µs at 20MHz)
— Serial Interface Incorporated buffer RAM (1 to 32 bytes auto transfer), 1 channel
Incorporated 8-bit and 8-stage FIFO (1 to 8 bytes auto transfer), 1 channel
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer,
32kHz timer/counter
— High precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable
RTG: 5 pins, 2 channels
— PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency of 78kHz at 20MHz)
DA gate pulse output: 13 bits, 4 channels — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14 bits, 1 channel — Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO
Interruption 20 factors, 15 vectors, multi-interruption possible
Standby mode Sleep/stop
Package 100-pin plastic QFP/LQFP
Piggyback/evaluator CXP81900M
– 1 –
CXP81952M/81960M
E95511A69-PS
CMOS 8-bit Single Chip Microcomputer
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
100 pin QFP (PIastic) 100 pin LQFP (PIastic)
Structure
Silicon gate CMOS IC
– 2 –
CXP81952M/81960M
PI6/SO1
PA0 to PA7
PB0 to PB7
PC0 to PC7
PD0 to PD7
PE0 to PE1
PE2 to PE7
PF0 to PF3
PF4 to PF7
PG0 to PG7
PI1 to PI7
PJ0 to PJ7
Vss V
DD
MP RST XTAL
EXTAL
CLOCK
GENERATOR/
SYSTEM CONTROL
RAM
2048 BYTES
SPC700
CPU CORE
ROM
52K/60K BYTES
INTERRUPT CONTROLLER
2
2
32kHz
TIMER/COUNTER
FIFO
FRC
CAPTURE UNIT
PROGRAMMABLE
PATTERN
GENERATOR
RAM
2
5
19
AVss
AV
REF
AV
DD
A/D CONVERTER
SERIAL
INTERFACE UNIT
(CH0)
RAM
8 BIT TIMER/COUNTER 0
8 BIT TIMER 1
14 BIT PWM GENERATOR
12 BIT PWM GENERATOR CH0
2
2
12 BIT PWM GENERATOR CH1
4
PE7/DAB1
PE5/DAA1
PE3/PWM1
PE6/DAB0
PE4/DAA0
PE2/PWM0
PI2/PWM
PI1/RMC
PG7/EXI1
PG6/EXI0
PI3/TO
PE1/EC
PI5/SCK1
PI7/SI1
SCK0
SO0
SI0
CS0
PF0/AN4
to
PF7/AN11
AN0 to AN3
REALTIME
PULSE
GENERATOR
PE1/INT2
PE0/INT0
PI4/INT1/NMI
12
8
PORT A
8
PORT B
8
PORT C
8
PORT D
6
PORT E
4
PORT F
8
PORT G
8
PORT H
7
PORT I
PH0 to PH7
TX TEX
NMI
PRESCALER/
TIME BASE TIMER
REMOCON INPUT
FIFO
SERIAL
INTERFACE UNIT
(CH1)
CH0
CH1
8
PORT J
PA0/PPO0
to
PC2/PPO18
PC3/RTO3
to
PC7/RTO7
FIFO
ADJ
2
4
Block Diagram
– 3 –
CXP81952M/81960M
Pin Assignment 1 (Top View) 100-pin QFP package
PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10
PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3
PC2/PPO18 PC1/PPO17 PC0/PPO16
PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1
PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
NC
V
DD
V
SS
TX
TEX
PI1/RMC
PI2/PWM
PI3/TO/ADJ
PI4/INT1/NMI
PI5/SCK1
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
MP
RST
V
SS
XTAL
EXTAL
CS0
SI0
SO0
SCK0
PF7/AN11
PF6/AN10
PF5/AN9
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70 69 68 67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
2 3 4
5 6 7 8 9
10
11 12 13 14 15 16 17
18 19
20
21
22
23
24
25
26
27
28 29 30
1
81
82
83
84
88
87
86
85
89
90
100
99
98
97
96
95
94
91
92
93
PI6/SO1 PI7/SI1 PE0/INT0 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0 PG1 PG2 PG3 PG4 PG5 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8
Note) 1. NC (Pin 90) is always connected to VDD.
2. Vss (Pins 41 and 88) are both connected to GND.
3. MP (Pin 39) is always connected to GND.
– 4 –
CXP81952M/81960M
Pin Assignment 2 (Top View) 100-pin LQFP package
PB3/PPO11 PB2/PPO10
PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4
PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16
PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1
PJ0 PD7 PD6 PD5 PD4 PD3
PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0 PG1 PG2 PG3 PG4 PG5 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AV
DD
AVREF
PB4/PPO12
PB5/PPO13
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
NC
V
DD
V
SS
TX
TEX
PI1/RMC
PI2/PWM
PI3/TO/ADJ
PI4/INT1/NMI
PI5/SCK1
PI6/SO1
PI7/SI1
PE0/INT0
PD2
PD1
PD0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
MP
RST
V
SS
XTAL
EXTAL
CS0
SI0
SO0
SCK0
PF7/AN11
PF6/AN10
PF5/AN9
PF4/AN8
AV
SS
2 3 4
5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1
76
77
78
79
80
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
81
82
83
84
88
87
86
85
89
90
100
99
98
97
96
95
94
91
92
93
51
52
53
54
55
56
57
58
59
60
70 69
68
67
63
64
65
66
61
62
71
72
73
74
75
Note) 1. NC (Pin 88) is always connected to VDD.
2. Vss (Pins 39 and 86) are both connected to GND.
3. MP (Pin 37) is always connected to GND.
– 5 –
CXP81952M/81960M
Output/ Real-time output
Output/ Real-time output
I/O/ Real-time output
I/O/ Real-time output
I/O
Input/Input
Input/Input/Input
Output/Output Output/Output Output/Output Output/Output Output/Output Output/Output Input
Input/Input
Output/Input
I/O Ouput Input Input
(Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins)
(Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins)
(Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins)
(Port D) 8-bit I/O port. I/O can be set in a unit of 4bits. Can drive 12mA sink current. (8 pins)
(Port E) 8-bit port. Lower 2 bits are for input; upper 6 bits are for output. (8 pins)
Analog input pins to A/D converter. (12 pins)
(Port F) 8-bit port. Lower 4 bits are for input; upper 4 bits are for output. Lower 4 bits also serve as standby release input pin. (8 pins)
Serial clock (CH0) I/O pin. Serial data (CH0) output pin. Serial data (CH0) input pin. Serial chip select (CH0) input pin.
External event input pin for timer/counter.
Input pin to request external interruption. Active at the falling edge.
Input pin to request external interruption. Active at the falling edge.
PWM output pins. (2 pins)
DA gate pulse output pins. (4 pins)
Programmable pattern generator (PPG) output. Functions as high precision real-time pulse output port. (19 pins)
Real-time pulse generator (RTG) output. Functions as high precision real-time pulse output port. (5 pins)
Symbol I/O Description
PA0/PPO0
to
PA7/PPO7
PB0/PPO8
to
PB7/PPO15
PC0/PPO16
to
PC2/PPO18 PC3/RTO3
to
PC7/RTO7
PD0 to PD7
PE0/INT0
PE1/EC/INT2
PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4
to
PF3/AN7 PF4/AN8
to
PF7/AN11 SCK0 SO0 SI0 CS0
Pin Description
– 6 –
CXP81952M/81960M
PG0 to PG4 PG5 PG6/EXI0 PG7/EXI1
PH0 to PH7
PI1/RMC PI2/PWM
PI3/TO/ADJ PI4/INT1/
NMI PI5/SCK1 PI6/SO1 PI7/SI1
PJ0 to PJ7
EXTAL XTAL TEX TX
RST MP AVDD AVREF AVss VDD Vss
Input
Output
I/O/Input I/O/Output
I/O/Output/Output
I/O/Input/Input I/O/I/O
I/O/Output I/O/Input
I/O
Input Output Input Output
Input Input
Input
External input pin to FRC capture unit.
(Port G) 8-bit input port. (8 pins)
(Port H) 8-bit output port; N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins)
Remote control reception circuit input pin. 14-bit PWM output pin. Timer/counter, 32kHz oscillation adjustment output
pin. Input pin to request external interruption and
non-maskable interruption. Active at the falling edge. Serial clock (CH1) I/O pin. Serial data (CH1) output pin. Serial data (CH1) input pin.
(Port I) 7-bit I/O port. I/O port can be set in a unit of single bits. (7 pins)
(Port J) 8-bit I/O port. I/O and standby release input can be set in a unit of single bits.
Connects a crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin.
Connects a crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (Feedback resistor is not removed.)
System reset pin; active at Low level. Microprocessor mode input pin. Always connect to GND. Positive power supply pin of A/D converter. Reference voltage input pin of A/D converter. GND pin of A/D converter. Positive power supply pin. GND pin. Connect both Vss pins to GND.
Symbol I/O Description
– 7 –
CXP81952M/81960M
16 pins
Hi-Z
Hi-Z
When reset
PA0/PPO0
to
PA7/PPO7 PB0/PPO8
to
PB7/PPO15
PC0/PPO16
to
PC2/PPO18 PC3/RTO3
to
PC7/RTO7
Hi-Z
PD0 to PD7
PPO data
Data bus
Output becomes active from high impedance by data writing to port register.
Port A or Port B
RD (Port A or Port B)
Input/Output Circuit Formats for Pins
Port A Port B
Pin
Circuit format
8 pins
8 pins
Port C
Port D
Data bus
PPO, RTO data
Port C data
Port C direction
(Every bit)
IP
Input protection circuit
Data bus
RD (Port C)
Port D data
Port D direction
RD (Port D)
(Every 4 bits)
PD0 to 3 PD4 to 7
IP
Large current 12mA
– 8 –
CXP81952M/81960M
1 pin
Hi-Z
Hi-Z
When reset
PE0/INT0
PE1/EC/INT2
PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1
Hi-Z
High level
RD (Port E)
IP
Data bus
Input protection circuit
Interruption circuit
Port E
Port E
Pin
Circuit format
1 pin
Data bus
RD (Port E)
A
A
DA gate output or PWM output
Hi-Z control
MPX
Port E data
Port/DA output selection
Data bus
RD (Port E)
A
DA gate output
Hi-Z control
MPX
Port E data
Port/DA output selection
Port E
4 pins
PE6/DAB0 PE7/DAB1
2 pins
Port E
Interruption circuit/ event counter
Data bus
RD (Port E)
A
IP
Input protection circuit
A
AA
– 9 –
CXP81952M/81960M
4 pins
Hi-Z
Hi-Z
When reset
AN0 to AN3
PF0/AN4
to
PF3/AN7
PF4/AN8
to
PF7/AN11
Hi-Z
Hi-Z
IP
A/D converter
Input multiplexer
Port F
Pin
Circuit format
4 pins
A/D converter
Data bus
RD (Port F)
Port/AD selection
IP
Port F data
Input multiplexer
IP
RD (Port G)
Data bus
Schmitt input
Port F
4 pins
PG0 to PG5
8 pins
Port G
Hi-Z
IP
RD (Port G)
Data bus
Schmitt input
FRC capture unit
6 pins
PG6/EXI0 PG7/EXI1
Port G
Hi-Z
Data bus
RD (Port H)
Port H data
Large current 12mA
Medium drive voltage 12V
2 pins
PH0 to PH7
Port H
Input multiplexer
IP
RD (Port F)
A/D converter
Data bus
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