The CXP81952/81960 is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, vector
interruption, high precision timing pattern generation
circuit, PWM generator, PWM for tuner, 32kHz
timer/event counter, remote control receiving circuit,
general purpose prescaler, and external signal, as
well as basic configurations like 8-bit CPU, ROM,
RAM and I/O port. They are integrated into a single
chip.
Also the CXP81952/81960 provides sleep/stop
function which enables to lower power consumption
and ultra-low speed instruction mode in 32kHz
operation.
100 pin QFP (PIastic)100 pin LQFP (PIastic)
Structure
Silicon gate CMOS IC
Features
• A wide instruction set (213 instructions) which cover various types of data
— 16-bit operation/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle250ns at 16MHz operation
122µs at 32kHz operation
• Incorporated ROM capacity52K bytes (CXP81952), 60K bytes (CXP81960)
• Incorporated RAM capacity2048 bytes
• Peripheral functions
— A/D converter8-bit, 12-channel, successive approximation system
(Conversion time 20.0µs/16MHz)
— Serial InterfaceIncorporated buffer RAM (1 to 32 bytes auto transfer) 1-channel
Incorporated 8-bit and 8-stage FIFO for data
(1 to 8 bytes auto transfer) 1-channel
— Timer8-bit timer, 8-bit timer/counter, 19-bit time base timer,
32kHz timer/counter
— High precision timing pattern generatorPPG 19-pin 32-stage programmable
RTG 5-pin 2-channel
— PWM/DA gate outputPWM 12-bit, 2-channel (Repetitive frequency 62kHz/16MHz)
DA gate pulse output 13-bit, 4-channel
— FRC capture unitIncorporated 26-bit and 8-stage FIFO
— PWM output 14-bit, 1-channel
— Remote control receiving circuit8-bit pulse measurement counter with on-chip, 6-stage FIFO
— General purpose prescaler7-bit (PG5 input frequency divided, FRC capture possible)
• Interruption20 factors, 15 vectors, multi-interruption possible
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Input pin to request external interruption and
non-maskable interruption. Active when falling edge.
Serial clock (CH1) I/O pin.
Serial data (CH1) output pin.
Serial data (CH1) input pin.
(Port J)
8-bit I/O port. Function as standby release input can be specified by bit
unit. I/O can be specified by bit unit.
Connecting pin of crystal oscillator for system clock. When supplying
the external clock, input the external clock to EXTAL pin and input
opposite phase clock to XTAL pin.
Connecting pin of crystal oscillator for 32kHz timer clock. When used
as event counter, input to TEX pin and leave TX pin open. (Feedback
resistor is not removed.)
System reset pin of active "L" level.
Microprocessor mode input pin. Always connect to GND.
Positive power supply pin of A/D converter.
Reference voltage input pin of A/D converter.
GND pin of A/D converter.
Positive power supply pin.
GND pin. Connect both Vss pins to GND.
– 6 –
Input/Output Circuit Formats for Pins
CXP81952/81960
Pin
PA0/PPO0
to
PA7/PPO7
PB0/PPO8
to
PB7/PPO15
16 pins
PC0/PPO16
to
PC2/PPO18
PC3/RTO3
to
PC7/RTO7
Port A
Port B
Data bus
Port C
PPO data
Port A or Port B
RD
PPO, RTO data
Port C data
Port C direction
Circuit format
Output becomes active from high
impedance by data writing to port register.
(Every bit)
IP
Input
protection
circuit
When reset
Hi-Z
Hi-Z
8 pins
PD0 to PD7
8 pins
Data bus
Port D
Data bus
RD (Port C)
Port D data
Port D direction
RD (Port D)
(Every 4 bits)
PD0 to 3
PD4 to 7
IP
High
current
12mA
Hi-Z
– 7 –
CXP81952/81960
A
Pin
PE0/INT0
1 pin
PE1/EC/INT2
1 pin
PE2/PWM0
PE3/PWM1
PE4/DAA0
PE5/DAA1
Port E
Data bus
Port E
Data bus
Interruption circuit/
event counter
Port E
DA gate output
or PWM output
Hi-Z control
RD
Port E data
Circuit format
Interruption circuit
RD (Port E)
MPX
IP
Input protection circuit
IP
Input protection circuit
When reset
Hi-Z
Hi-Z
Hi-Z
4 pins
PE6/DAB0
PE7/DAB1
2 pins
Data bus
Port E
Data bus
Port/DA output
select
RD (Port E)
DA gate output
Hi-Z control
Port E data
Port/DA output
select
RD (Port E)
MPX
A
H level
– 8 –
CXP81952/81960
AAA
Pin
AN0 to AN3
4 pins
PF0/AN4
to
PF3/AN7
4 pins
PF4/AN8
to
PF7/AN11
4 pins
Port F
Port F
Data bus
Port F data
RD
(Port F)
Circuit format
Input multiplexer
IP
Input multiplexer
IP
Port/AD select
RD (Port F)
A/D converter
A/D converter
Data bus
IP
Input multiplexer
A/D
converter
When reset
Hi-Z
Hi-Z
Hi-Z
PG0 to PG4
PG5/PCK
6 pins
PG6/EXI0
PG7/EXI1
2 pins
PH0 to PH7
8 pins
Port G
Port G
Port H
Data bus
Port H data
RD (Port H)
Schmitt input
IP
Schmitt input
IP
RD (Port G)
RD (Port G)
Data bus
PG5: To general
purpose prescaler
FRC capture unit
Data bus
Medium withstand
voltage 12V
Large current
12mA
Hi-Z
Hi-Z
Hi-Z
– 9 –
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