Sony CXP81124, CXP81120 Datasheet
CXP81120/81124
CMOS 8-bit Single Chip Microcomputer
Description
The CXP81120/81124 is a CMOS 8-bit microcomputer which consists of A/D converter, serial
interface, timer/counter, time base timer, PWM
output, as well as basic configurations like 8-bit
CPU, ROM, RAM and I/O port. They are integrated
into a single chip.
Also the CXP81120/81124 provides power-on reset
function, sleep/stop function which enables to lower
power consumption.
Features
• A wide instruction set (213 instructions) which covers various types of data
— 16-bit operation/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V)
333ns at 12MHz operation (3.0 to 5.5V)
• Incorporated ROM capacity 20K bytes (CXP81120)
24K bytes (CXP81124)
• Incorporated RAM capacity 832 bytes
• Peripheral functions
— A/D converter 8-bit, 8-channel, successive approximation system
(Conversion time: 20µs at 16MHz)
— Serial interface Incorporated buffer RAM (1 to 32 bytes auto transfer), 1 channel
Incorporated 8-bit and 8-stage FIFO
(1 to 8 bytes auto transfer), 1 channel
— Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer
— PWM output 12 bits, 2 channels
• Interruption 10 factors, 10 vectors, multi-interruption possible
• Standby mode Sleep/stop
• Package 64-pin plastic QFP/LQFP
• Piggyback/evaluator CXP81100 64-pin ceramic PQFP
64 pin LQFP (Plastic)64 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94414A69-PS
CXP81120/81124
Vss
V
DD
MP
RST
XTAL
EXTAL
PA0 to PA7
8
PORT A
CLOCK
GENERATOR/
SYSTEM CONTROL
SPC700
CPU CORE
PB0 to PB7
8
PORT B
PC0 to PC7
8
PORT C
RAM
832 BYTES
ROM
20K/24K BYTES
PD0 to PD7
PE0 to PE1
2
8
PORT D
PE2 to PE3
PF0 to PF3
4
2
PORT E
PF4 to PF7
PG3 to PG4
PG5 to PG7
2
4
PORT F
PRESCALER/
3
PORT G
TIME BASE TIMER
REF
DD
INT2
INT1
INT0
AVss
AV
AV
RAM
BUFFER
A/D CONVERTER
8
AN0 to AN7
(CH0)
SERIAL
INTERFACE UNIT
SI0
CS0
SO0
FIFO
SERIAL
INTERFACE UNIT
SI1
SO1
SCK0
INTERRUPT CONTROLLER
2
(CH1)
SCK1
8BIT TIMER 1
8BIT TIMER/COUNTER 0
EC
TO
12BIT PWM GENERATOR CH1
12BIT PWM GENERATOR CH0
PWM1
PWM0
Block Diagram
– 2 –
Pin Configuration (Top View) 64-pin QFP
PA2
PA0
PA1
PA3
SS
V
DD
V
NC
PA4
PA5
PA6
PA7
PG3/TO
PG4
CXP81120/81124
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
PD6
PD5
10
11
12
13
14
15
16
17
18
19
61
60
63
62
64
1
2
3
4
5
6
7
8
9
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PG5/SCK1
PG6/SO1
PG7/SI1/INT1
PE0/INT0
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PF0/AN0
PF1/AN1
PF2/AN2
PF3/AN3
PF4/AN4
PF5/AN5
PF6/AN6
PF7/AN7
AV
DD
AVREF
AV
SS
SCK0
20
PD4
21
PD3
22
PD2
23
24
PD1
PD0
25
MP
26
XTAL
27
EXTAL
28
SS
V
29
30
RST
CS0
SI0
32
31
Note) 1. NC (Pin 58) is always connected to VDD.
2. Vss (Pins 28 and 60) are both connected to GND.
3. MP (Pin 25) is always connected to GND.
SO0
– 3 –
Pin Configuration (Top View) 64-pin LQFP
PB7
PB6
PA0
PA1
PA2
PA3
SS
V
DD
V
NC
PA4
PA5
PA6
PA7
PG3/TO
PG4
CXP81120/81124
PG5/SCK1
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
PD6
10
11
12
13
14
15
16
62
19
61
20
PD3
60
21
PD2
59
22
PD1
63
64
1
2
3
4
5
6
7
8
9
18
17
PD4
PD5
PD0
58
23
MP
57
24
56
25
XTAL
EXTAL
55
26
SS
V
54
27
53
28
RST
52
29
CS0
SI0
51
30
50
31
SO0
49
32
SCK0
SS
AV
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PG6/SO1
PG7/SI1/INT1
PE0/INT0
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
PF0/AN0
PF1/AN1
PF2/AN2
PF3/AN3
PF4/AN4
PF5/AN5
PF6/AN6
PF7/AN7
AV
DD
AVREF
Note) 1. NC (Pin 56) is always connected to VDD.
2. Vss (Pins 26 and 58) are both connected to GND.
3. MP (Pin 23) is always connected to GND.
– 4 –
Pin Description
CXP81120/81124
Symbol
PA0 to PA7
PB0 to PB7
PC0 to PC7
PD0 to PD7
PE0/INT0
PE1/EC/INT2
PE2/PWM0
PE3/PWM1
I/O Description
(Port A)
Output
8-bit output port.
(8 pins)
(Port B)
Output
8-bit output port.
(8 pins)
(Port C)
I/O
8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)
(Port D)
I/O
8-bit I/O port. I/O and function as standby release input can be set in a unit of
single bits.
(8 pins)
Input/Input
Input/Input/
Input
Output/Output
(Port E)
4-bit port. Lower 2 bits
are for input; upper 2 bits
are for output.
(4 pins)
Input to request external interruption.
Active at the falling edge. (2 pins)
External event
input for
timer/counter.
12-bit PWM output. (2 pins)
Output/Output
PF0/AN0
to
PF3/AN3
PF4/AN4
to
PF7/AN7
SCK0
SO0
SI0
CS0
PG3/TO
PG4
PG5/SCK1
PG6/SO1
PG7/SI1/INT1
EXTAL
XTAL
Input/Input
Output/Input
I/O
Output
Input
Input
Output/Output
Output
I/O/I/O
I/O/Output
I/O/Input
Input
Input
Output
(Port F)
8-bit port. Lower 4 bits are for input; upper
4 bits are for output.
Lower 4 bits also serve as standby release
input.
Analog input to A/D
converter.
(8 pins)
(8 pins)
Serial clock (CH0) I/O.
Serial data (CH0) output.
Serial data (CH0) input.
Serial interface (CH0) chip select input.
Timer/counter rectangular wave output.
(Port G)
5-bit port. Lower 2 bits
are for output; upper
3 bits are for I/O.
I/O can be set in a unit
of single bits.
(5 pins)
Serial clock (CH1) I/O.
Serial data (CH1) output.
Serial data (CH1)
input.
Input to request external
interruption. Active at the
falling edge.
Connects a crystal oscillator for system clock. When supplying the external
clock, input the external clock to EXTAL pin and input opposite phase
clock to XTAL pin.
RST
I/O
System reset; active at Low level. RST pin is I/O pin, which outputs “Low”
level by incorporated power-on reset function when power turns on.
(Mask option)
– 5 –
CXP81120/81124
Symbol
NC
MP
AVDD
AVREF
AVSS
VDD
VSS
I/O Description
NC pin.
Connect to VDD for normal operation.
Input
Test mode pin.
Always connect to GND.
Positive power supply of A/D converter.
Input
Reference voltage input of A/D converter.
GND of A/D converter.
Positive power supply.
GND. Connect both Vss pins to GND.
– 6 –
Input/Output Circuit Formats for Pins
CXP81120/81124
Pin
PA0 to PA7
PB0 to PB7
16 pins
PC0 to PC7
8 pins
Port A
Port B
Data bus
Port C
Data bus
Ports A, B data
RD (Ports A, B)
Port C data
Port C direction
“0” when reset
RD (Port C)
Circuit format When reset
Hi-Z
Output becomes active from high impedance
by data writing to port register.
Input
protection
circuit
IP
Hi-Z
PD0 to PD7
8 pins
PE0/INT0
1 pin
PE1/EC/INT2
Port D
Port E
Port E
Port D data
Port D direction
“0” when reset
Data bus
RD (Port D)
Standby release
Edge detection
Schmitt input
IP
Schmitt input
IP
Hi-Z
IP
EC/INT2
Hi-Z
Data bus
RD (Port E)
INT0
Hi-Z
Data bus
1 pin
RD (Port E)
– 7 –
CXP81120/81124
A
A
AAA
Pin
PE2/PWM0
PE3/PWM1
2 pins
PF0/AN0
to
PF3/AN3
4 pins
Port E
Hi-Z control
Port E function selecton
“0” when reset
Data bus
RD (Port E)
Port F
PWM
Port E data
Circuit format When reset
input multiplexer
IP
A
MPX
A
RD (Port F)
Edge detection
Hi-Z
A/D converter
Hi-Z
Data bus
Standby release
PF4/AN4
to
PF7/AN7
4 pins
PG3/TO
1 pin
Port F
Data bus
Port G
Port F data
RD (Port F)
Port G function
selection
“0” when reset
Timer/counter
Port G data
“1” when reset
Port F function
selection
“0” when reset
MPX
Input multiplexer
IP
A/D converter
Hi-Z
High level
– 8 –
A
CXP81120/81124
Pin
PG4
1 pin
PG5/SCK1
PG6/SO1
2 pins
Port G
Port G
Serial clock 1/data 1
output enable
Port G data
Port G direction
“0” when reset
Data bus
Port G data
“1” when reset
Port G function
selection
“0” when reset
SCK1 out, SO1
RD (Port G)
Circuit format When reset
MPX
A
SCK1 in
MPX
∗
1
PG6 is not Schmitt input
IP
∗1
H level
Hi-Z
PG7/SI1/INT1
1 pin
CS0
SI0
2 pins
SO0
1 pin
Port G
Data bus
Serial data 0
output enable
Port G data
Port G direction
“0” when reset
RD (Port G)
INT1
SI1
IP
SO0
Schmitt input
Schmitt input
CS0
SI0
IP
Hi-Z
Hi-Z
Hi-Z
– 9 –
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