Sony CXL5005P, CXL5005M Datasheet

CMOS-CCD 1H Delay Line for NTSC with PLL

Description

The CXL5005M/P are general-purpose CCD delay

line ICs which provide 1H delay time of NTSC.

Features

• Low power consumption 90mW (Typ.)

• Small size package (14-pin SOP, DIP)

• Low differential gain DG = 3% (Typ.)

• Input signal ampiitude 180 IRE (= 1.28Vp-p, max.)

• Low input clock amplitude operation 200mVp-p (Min.)

• Built-in triple PLL circuit

• Built-in peripheral circuits (clock driver, timing

generator, auto-bias and output circuits)

Functions

• 680-bit CCD register

• Clock drivers

• Autobias circuit

• Sync tip clamp circuit

• Sample-and-hold circuit

• PLL (triple)

Structure

CMOS-CCD

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VDD 11 V

• Supply voltage VCL 6V

•Operating temperature Topr –10 to +60 °C

• Storage temperature Tstg –55 to +150 °C

• Allowable power dissipation PD

CXL5005M 400 mW
CXL5005P 800 mW

Recommended Operating Conditions

Supply voltage VDD 9 ± 5% V

VCL 5 ± 5% V

Recommended Clock Conditions

• Input clock amplitude VCLK 200mVp-p to 1.0Vp-p

(300mVp-p typ.)

• Clock frequency fCLK 3.579545MHz

– 1 –

E88Z40A79-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXL5005M/P

CXL5005M

14 pin SOP (Plastic)

CXL5005P

14 pin DIP (Plastic)

– 2 –

CXL5005M/P

Blook Diagram and Pin configuration

φ2

φ1

10

NC

11

OUT

13

AUTO

14

IN

V

CL

8

9

CLK

NC

6

VCO

OUT

7

VCO

IN

3

4

V

DD

2

V

CL

V

SS

1

Clamp circuit

VCO

Auto-bias
circuit

1/3 counter

680 bit shift
register

Output & S/H

(1 BIT)

Phase
comparator

12

FEED

Clock driver

5

PC

OUT

Pin Description

Pin No. Symbol Description Impedance [Ω]

1
2
3
4
5
6
7
8

9
10
11
12
13
14

VSS
VCL
VCOIN
VDD
PCOUT
NC
VCOOUT
VCL
CLK
NC
OUT
FEED
AUTO
IN

GND
5V power supply
VCO input
9V power supply
Phase comparator output

VCO output
5V power supply
Clock input

Signal output
Feedback DC output
Autobias DC output
Signal input

> 100k

≈ 5k

≈ 5k

≈ 5k

600 to 1k
> 100k
≈ 10k
> 100k

– 3 –

CXL5005M/P

Electrical Characteristics

(Ta = 25°C, VDD = 9.0V, VCL = 5.0V, fCLK = 3.58MHz, VCLK = 300mVp-p sine wave,

See "Electrical Characteristics Test Circuit")

Item Symbol Test condition

SW condition

Measuring
point

Min. Typ. Max. Unit

1

2

mA
mA

dB

dB

%

deg

Vp-p

dB

V
V
V
V

5.0

12.0

3.0

—

5.0

5.0

1.28

—

6.5

6.5

3.3

3.7

4.0

9.0

0.0

–2.1

3.0

3.0

—

60

5.0

5.0

2.3

2.7

—
—

–3.0

–3.0

—
—

—

55

3.5

3.5

1.3

1.7

A1
A2

V1

V1

S

—

V2

V3
V4
V5
V6

a

a

b

a

—

a

a

a

a

a

a

b, c

e

—

f

d

d

a

250kHz, 1.28Vp-p,
sine wave input

250kHz, 1.28Vp-p,
sine wave input
IG = 20 log (Output
voltage [Vp-p] /

1.28 [Vp-p])
Dissipation at 3.58MHz

in relation to 250kHz
fG = 20 log (V3.58MHz/
V250kHz) (Note 1)

5-staircase wave input
Y = 140 IRE (= 1.0Vp-p)
Measure with
vector scope (Note 2)

S: Input = 250kHz,

1.0Vp-p
output (Vp-p)

N: Input = DC GND

output (Vrms)

250kHz, 1.28Vp-p,
sine wave input

IDD
ICL

IG

fG

DG

DP

VIN-AC

S/N

VIN-DC
VAUTO-DC
VFEED-DC
VOUT-DC

Supply current

Insertion gain

Frequency
response

Differential gain

Differential phase
Allowable input

amplitude

Noise

DC output
voltage