Sony CXL5003P, CXL5003M Datasheet

CMOS-CCD 1H Delay Line for PAL

Description

The CXL5003M/P are general-purpose CMOS-CCD

delay line ICs that provide 1H delay time for PAL.

Features

• Low power consumption 110mW (Typ.)

• Small size package (8-pin SOP, DIP)

• Low differential gain DG = 3% (Typ.)

• Input signal amplitude 180 IRE (= 1.28Vp-p, Max.)

• Low input clock amplitude operation 150mVp-p (Min.)

• Built-in peripheral circuits (clock driver, timing

generator, autobias, and output circuits)

Functions

• 848-bit CCD register

• Clock drivers

• Autobias circuit

• Sync tip clamp circuit

• Sample and hold circuit

Structure

CMOS-CCD

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VDD 11 V

• Supply voltage VCL 6V

•Operating temperature Topr –10 to +60 °C

• Storage temperature Tstg –55 to +150 °C

• Allowable power dissipation PD

CXL5003M 350 mW
CXL5003P 480 mW

Recommended Operating Conditions

Supply voltage VDD 9 ± 5% V

VCL 5 ± 5% V

Recommended Clock Conditions

• Input clock amplitude VCLK 150mVp-p to 1.0Vp-p

(250mVp-p typ.)

• Clock frequency fCLK 13.300856MHz

– 1 –

E51215B79-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXL5003M/P

CXL5003M

8 pin SOP (Plastic)

CXL5003P

8 pin DIP (Plastic)

– 2 –

CXL5003M/P

Blook Diagram

IN

AUTO

FEED

5

848-BIT SHIFT REGISTER

φ1

φ2

AUTO BIAS CIRCUIT

CLAMP CIRCUIT

OUT

AMP S/H AMP AMP

6

7

8

2

V

SS

V

CL

CLK

4

DUTY CONTROL
CIRCUIT

1

CLOCK DRIVERS

3

V

DD

ref.

(1 BIT)

φ

2φ1

Pin Description

Pin No. Symbol Description Impedance [Ω]

1
2
3
4

VSS
VCL
CLK
VDD

GND
5V power supply
Clock input
9V power supply

> 100k

Pin No. Symbol Description Impedance [Ω]

5
6
7
8

OUT
FEED
AUTO
IN

Signal output
Feedback DC output
Autobias DC output
Signal input

600 to 1k
> 100k
10k
> 100k

– 3 –

CXL5003M/P

Electrical Characteristics

(Ta = 25°C, VDD = 9.0V, VCL = 5.0V, fCLK = 13.3MHz, VCLK = 250mVp-p sine wave,

See "Electrical characteristics test circuit")

Item Symbol Measuring condition

SW conditions

Measuring
point

Min. Typ. Max. Unit

1

2

mA
mA

dB

dB

%

deg

Vp-p

dB

V
V
V
V

5

16

3

—

5
5

1.28

—

6.5

6.5

3.3

3.7

4

14

0

–2.1

3
3

—

60

5.0

5.0

2.3

2.7

—
—

–3

–3.0

—
—

—

55

3.5

3.5

1.3

1.7

A1
A2

V1

V1

S

—

V2

V2
V3

V4
V5
V6

a

a

b

a

—

a

a

a

a

a

a

b, c

e

—

f

d

d

a

250kHz, 1.28Vp-p,
sine wave input

250kHz, 1.28Vp-p,
sine wave input
IG = 20 log (Output
voltage [Vp-p] /

1.28 [Vp-p])
Dissipation at 4.43MHz

in relation to 250kHz
fG = 20 log (V4.43MHz/
V250kHz) (Note 1)

5-staircase wave input
Y = 140 IRE (= 1.0Vp-p)
Measure S point with
vector scope (Note 2)

S: Input = 250kHz,

1.0Vp-p
output (Vp-p)

N: Input = DC ground

output (mVrms)

250kHz, 1.28Vp-p,
sine wave input

IDD
ICL

IG

fG

DG

DP

VIN-AC

S/N

VIN-AC
VAUTO-DC
VFEED-DC
VOUT-DC

Supply current

Insertion gain

Frequency
response

Differential gain

Differential phase
Allowable input

amplitude

Noise

Output DC
voltage