Sony CXL1510M Datasheet
CXL1510M
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CCD Delay Line for Multi System
Description
The CXL1510M is an IC developed for use in
conjunction with Y/C signal processing ICs for multi
systems. This CCD delay line provides the comb
filter output for eliminating the chrominance signal
cross talk and 1H delay output for luminance signals.
Features
• Single power supply (5V)
• Built-in quadruple progression PLL circuit
• Comb filter characteristics selectable
• Delay time for 1H delay output selectable
• Built-in peripheral circuits
• Positive phase signal input, positive phase signal output
Functions
• Comb filter output
• 1H delay output for luminance signal
• Clock driver
• Autobias circuit
• Input clamp circuit (for luminance signals)
• Center bias circuit (for chrominance signals)
• Sample-and-hold circuit
• Quadruple progression PLL circuit
• Luminance signal delay time/comb filter characteristics selection circuit
• Clock buffer output circuit
24 pin SOP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD +6 V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation PD 500 mW
Recommended Operating Voltage (Ta = 25°C)
VDD 5V ± 5%
Structure
CMOS-CCD
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94804-ST
Recommended Clock Conditions (Ta = 25*C)
• Input clock amplitude VCLK 0.3Vp-p to 1.0Vp-p (0.5Vp-p Typ.)
• Clock frequency fCLK 3.579545MHz
• Input clock waveform sine wave
Input Signal Amplitude
Vsig 350mVp-p (Typ.), 575mVp-p (Max.)
Block Diagram and Pin Configuration (Top View)
CXL1510M
Vss
24
Autobias
circuit (C)
1
Vss
C-OUT
23
Selector 1
Bias circuit Bias circuit Selector 2 Clamp circuit 1H
2
C-IN1
CONT1
22
1H/2H + D
3
DD
V
AB-C
21
4
C-IN2
fsc
20
fsc buffer
D
5
(NC)
AB-P
19
6
CONT2
(NC)
18
Output
circuit (S/H)
7
Y-IN
(NC)
17
8
(NC)
(NC)
16
Driver
Autobias
circuit (Y)
9
Y-OUT
PCOUT
Timing
φ1 φ2
10
(NC)
VCOIN
1415
PLL
Driver
11
(NC)
Vss
13
Output
circuit (S/H)
12
CLK
– 2 –
SOP 24pin
CXL1510M
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
VSS
C-IN1
VDD
C-IN2
(NC)
CONT2
Y-IN
(NC)
Y-OUT
(NC)
(NC)
CLK
VSS
VCOIN
PCOUT
(NC)
I/O
GND
—
Chrominance signal input 1
I
Power supply
—
Chrominance signal input 2
I
Description
—
Control 2 input
I
Luminance signal input
I
—
Luminance signal output
O
—
—
Clock input
I
GND
—
VCO input
I
Phase comparator output
O
—
—
—
—
—
—
17
18
19
20
21
22
23
24
(NC)
(NC)
AB-P
fsc
AB-C
CONT1
C-OUT
VSS
—
—
Autobias output (P)
O
fsc buffer output
O
Autobias output (C)
O
Control 1 input
I
Chrominance signal output
O
GND
—
—
—
– 3 –
CXL1510M
Description of Functions
The CXL1510M enables the chrominance comb filter characteristics and luminance signal delay time to be
selected using the control 1 and control 2 statuses.
CONT1
L
L
H
H
CONT2
L
H
L
H
Mode (typical example)
PAL/GBI
PAL/M
—
NTSC/M
Chrominance comb filter
characteristics
2H + 12 (1832bit)
2H (1820bit)
—
1H (910bit)
Luminance signal delay time
(number of CCD bits)
1H + 6 (914bit)
1H (908bit)
—
1H (908bit)
CONT1/CONT2 Input Level
L/H
L
Min.
—
Typ.
0
Max.
0.5
Unit
V
H
2.0
5.0
6.0
• fsc Output Pin
The buffer output of the clock input from the CLK pin is provided at the fsc output pin. Since a pull-up resistor
is contained inside the IC, the supply voltage is produced during open, and the output is stopped. Connect a
2.2kΩ pull-down resistor when the fsc output is to be used.
<When in use> <When not in use>
fsc
2.2k
fsc
VDD
– 4 –
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p sine wave)
See Electrical Characteristics Measurement Circuit
CXL1510M
Item Symbol
IDD1
Supply
current
IDD2
IDD3
Measurement
condition
—
1234567
bbbaaa—
bbbaba—
bbbbba—
SW condition
Chrominance Signal Characteristics (No signals input to Y-IN)
Item Symbol
Low
frequency
gain
Frequency
response
Linearity
GLC1
GLC2
GLC3
FC1
FC2
FC3
LIC1
LIC2
LIC3
Measurement
condition
(See Note 2)
(See Note 3)
(See Note 4)
1234567
aabaa—a
a
a
a
a
a
a
a
a
SW condition
abab—a
abbb—a
abaa—a
abab—a
abbb—a
a
baa—
a
abab—a
abbb—
a
Min. Typ. Max. Unit Note
8
—
—
35 50 mA
—
Min. Typ. Max. Unit Note
8
b
b
–2
02dB
b
b
–2.7
–1.7
0
b
–2
–1 0
b
b
b
–0.3
0 0.3 dB
b
dB
1
2
3
4
Comb
depth min.
gain
SN ratio
Coupling
level
Delay
time
CCD1
CCD2
CCD3
SNC1
SNC2
SNC3
CPC1
CPC2
CPC3
DC
(See Note 5)
50% white
video signal
(See Note 7)
(See Note 8)
a
abaa—a
a
abab—a
a
abbb—a
a
abaa—a
a
abab—a
a
abbb—a
b
bbaa—a
b
bbab—a
b
bbbb—a
a
b
b
—
——
a
b
b
b
d
d
d
b
b
b
a
52
—
–40 –25 dB
56 dB
10 50
230
—
mVrms
ns
5
6
7
8
– 5 –
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