Sony CXL1506N, CXL1506M Datasheet
CMOS-CCD 1H/2H Delay Line for PAL
Description
The CXL1506M/N is a CMOS-CCD delay line
developed for video signal processing. Usage in
conjunction with an external low pass filter provides
1H and 2H delay signals simultaneously (For PAL
signals).
Features
• Single power supply (5V)
• Low power consumption
• Built-in peripheral circuits
• Built-in tripling PLL circuit
• For PAL signals
• 1 input and 2 outputs
(Outputs for both 1H and 2H delays)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD 6V
•Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD CXL1506M 400 mW
CXL1506N 300 mW
Recommended Operating Voltage (Ta = 25°C)
VDD 5 ± 0.25 V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.)
• Input clock frequency fCLK 4.433619 MHz
• Input clock waveform sine wave
Input Signal Amplitude
VSIG 575 (Max.) mVp-p (at internal clamp condition)
– 1 –
E89X22C78-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXL1506M/N
CXL1506M
16 pin SOP (Plastic)
CXL1506N
20 pin SSOP (Plastic)
Blook Diagram CXL1506M
CXL1506N
Autobias circuit
Driver
Bias
circuit
PLL
Timing
CCD (1698bits)
Clamp circuit
Output circuit
S/H 1bit
14
12
13
10
11
2
5
6
7
1
VSS
VDD
VCO
IN
PC
OUT
V
SS
IN
VG1
VG2
OUT1
(1H)
V
SS
OUT2
(2H)
8
CLK
V
SS
(VCO OUT)
15
16
AB
V
DD
VSS
Output circuit
S/H 1bit
9
4
847bits
1698bits
3
Autobias circuit
Driver
Bias
circuit
PLL
Timing
CCD (1698bits)
Clamp circuit
Output circuit
S/H 1bit
14
12
13
10
11
2
5
6
7
1
VSS
NC V
DD
VCO
IN
PC
OUT
V
SS
IN
VG1
VG2
OUT1
(1H)
V
SS
OUT2
(2H)
8
CLK
V
SS
(VCO OUT)
NC
15
16
17
18
19
20
AB
V
DD
NC NC
V
SS
Output circuit
S/H 1bit
9
4
847bits 1698bits
3
For the availability of this product, please contact the sales office.
– 2 –
CXL1506M/N
Pin Description (CXL1506M)
Pin No. Symbol I/O Description Impedance [Ω]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IN
VG1
VG2
OUT1
VSS
OUT2
VSS (VCO OUT)
VSS
VDD
CLK
VSS
PC OUT
VCO IN
VDD
AB
VSS
I
O
I
O
—
O
(O)
—
—
I
—
O
I
—
O
—
Signal input
(Non-inverted signal)
Gate bias 1 DC output
Gate bias 2 DC input
1H signal output
(Inverted signal)
GND
2H signal output
(Inverted signal)
GND or VCO output (3fsc)
GND
Power supply (5V)
Clock input (fsc)
GND
Phase comparator output
VCO input
Power supply (5V)
Autobias DC output
GND
> 10kΩ (at no clamp)
40 to 500Ω
40 to 500Ω
> 10kΩ
600 to 200kΩ
Note) Description of VG2
Control of input signal clamp condition
0V … Sync tip clamp condition
5V … Center bias condition
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ ).
In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is
at 200mVp-p.
(Note)
– 3 –
CXL1506M/N
Pin Description (CXL1506N)
Pin No. Symbol I/O Description Impedance [Ω]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
NC
IN
VG1
VG2
OUT1
VSS
OUT2
NC
VSS (VCO OUT)
VSS
VDD
CLK
NC
VSS
PC OUT
VCO IN
VDD
AB
NC
VSS
—
I
O
I
O
—
O
—
(O)
—
—
I
—
—
O
I
—
O
—
—
—
Signal input
(Non-inverted signal)
Gate bias 1 DC output
Gate bias 2 DC input
1H signal output
(Inverted signal)
GND
2H signal output
(Inverted signal)
—
GND or VCO output (3fsc)
GND
Power supply (5V)
Clock input (fsc)
—
GND
Phase comparator output
VCO input
Power supply (5V)
Autobias DC output
—
GND
> 10kΩ (at no clamp)
40 to 500Ω
40 to 500Ω
> 10kΩ
600 to 200kΩ
Note) Description of VG2
Control of input signal clamp condition
0V … Sync tip clamp condition
5V … Center bias condition
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ ).
In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is
at 200mVp-p.
(Note)
– 4 –
CXL1506M/N
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 400mVp-p sine wave)
See Electrical Characteristics Test Circuit.
Item Symbol
Test conditions
(Note 1)
SW conditions
Min. Typ. Max. Unit
Note
1
2 3 4
2
3
4
5
5
6
7
mA
dB
dB
%
degree
dB
mVp-p
37
2
2
–0.7
–0.8
7
7
7
7
—
—
350
350
27
0
0
–1.7
–1.8
5
5
5
5
56
56
—
—
17
–2
–2
–2.7
–2.8
—
—
—
—
52
52
—
—
a
b
b
b
b
c
c
c
c
d
d
a
a
a
a
b
a
b
a
b
a
b
a
b
a
b
b
b
b
a
a
b
b
b
b
b
b
b
b
a
a
a
b ←→ c
b ←→ c
d
d
d
d
e
e
e
e
—
200kHz
500mVp-p sine wave
200kHz ←→ 4.434MHz
150mVp-p sine wave
5 staircase wave
5 staircase wave
No signal input
No signal input
IDD
GL1
GL2
fR1
fR2
DG1
DG2
DP1
DP2
SN1
SN2
CP1
CP2
Supply current
Low frequency
gain
Frequency
response
Differential gain
Differential phase
S/N ratio
S/H pulse coupling
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