Sony CXL1502M Datasheet

CMOS-CCD Signal Processor

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Description

The CXL1502M is a CMOS-CCD signal processor designed for 8-mm video signal processing. In combination with the 8-mm video Y/C signal processing IC CXA1200Q, this IC configures a comb filter for Y/C separation in recording an image, elimination of line crawling and crosstalk in playing back.

CXL1502M

30 pin SOP (Plastic)

Features

• Single power supply 5V

• Low power consumption

• Built-in peripheral circuits

• Completely adjustment free

• Built-in triple progression PLL circuit

• For PAL signals

Functions

• 1H comb filter, 2H comb filter output

• Dropout compensation

• PLL circuit (triple progression)

• Clock driver

• Autobias circuit

• Sync tip clamp circuit

• Sample and hold circuit

• Delay time matching through output (THR)

Structure

CMOS-CCD

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VDD 6V

•Operating temperature Topr –10 to +60 °C

• Storage temperature Tstg –55 to +150 °C

• Allowable power dissipation PD 500 mW

Recommended Operating Conditions (Ta = 25°C)

Supply voltage VDD 5 ± 5% V

Recommended Clock Conditions (Ta = 25°C)

• Input clock amplitude VCLK 0.3 to 1.0 Vp-p

(0.4Vp-p Typ.)

• Clock frequency fCLK 4.433619 MHz

• Input clock waveform sine wave

Input Signal Amplitude

VSIG 575 mVp-p

(Max.)

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E80334-PS

CXL1502M

Y-YD

16

V

SS

17

DD

V

18

YD

19

ADJY

20

SS

V

21

VCO OUT

22

V

SS

23

V

SS

24

CLK

25

Phase

comparator

Bias circuit (A)

Output circuit, S/H circuit

2H + D

φ1

φ2

Bias circuit (B)

Output circuit, S/H circuit

D

V

SS

C-CD

14 15

GG

V

B

13

V

GG

A

12

TH

11

ABN

Output circuit, S/H circuit

D

10

9

8

7

6

SS

DD

NC

V

NC

Block Diagram

DD

V

PC OUT

VCO IN

ABP

CCD3

2627

28

29

30

1/3 divider

VCO

Clock driver

– 2 –

Autobias

circuit (P)

Autobias

circuit (N)

CCD1

5

ADJC

4

SS

CCD2-C

CCDY

V

3

2

1

Pin Description

CXL1502M

Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

Symbol VSS CCDY CCD2-C ADJC CCD1 NC VDD VSS NC ABN TH VGGA VGGB C-CD VSS Y-YD

I/O

GND

—

Signal input 4 (Reverse phase signal)

I

Signal input 2 (Reverse phase signal)

I

Forward CCD bias DC output

O

Signal input 1 (Reverse phase signal)

I

Description

—

5V power supply

—

GND

— —

Reverse phase autobias DC output

O

THR signal output (Forward phase signal)

O

Gate bias (A) DC output

O

Gate bias (B) DC output

O

2H comb filter signal output

O

GND

—

1H comb filter signal output

O

Impedance (Ω)

> 100k (at no clamp) > 100k (at no clamp) 600 to 2k > 100k (at no clamp)

2k to 200k 40 to 500 2k to 10k 2k to 10k 40 to 500

40 to 500 17 18 19 20 21 22 23 24 25 26 27 28 29 30

VSS VDD YD ADJY VSS VCO OUT VSS VSS CLK VDD PC OUT VCO IN ABP CCD3

GND

—

5V power supply

—

DOC signal output (Reverse phase signal)

O

Reverse phase CCD bias DC output

O

GND

—

VCO output

O

GND

—

GND

—

Clock input

I

5V power supply

—

Phase comparator output

O

VCO input

I

Forward phase autobias DC output

O

Signal input 3 (Forward phase signal)

I

40 to 500

600 to 2k

4k to 40k

2k to 5k

> 100k

2k to 200k

> 100k (at no clamp)

– 3 –

CXL1502M

3

∗

∗4

∗5

∗6

∗7

dB

–1.0

–3.0

–5.0

—

b

c

b

a

c

d a

b

a

b

a

b

a

b

a

a c

a

11 10

9 8 7 6 5 4 3 2 1

mA

70

60

50

4

—

3

—

2

—

1

—

— —

a a a a a a a a a

Unit Note

Max.

Typ.

Min.

VBIAS

(V)

2

∗

See the Electrical Characteristics Test Circuit.

VBIAS

DD = 5V, fCLK = 4.433619MHz, VCLK = 400mVp-p sine wave)

Bias conditions

BIAS

V

(Ta = 25°C, V

SW conditions

∗1

VIT

VIC

VIY

VID

b b b b b b a a a a

c

dB

–3.0

–5.0

–7.0

–0.25

+0.25

b a b b b b a a a a c

dB

–1.0

–2.0

–3.0

VIT

–0.25

VIC

–0.25

VIY

–0.25

VID

+0.25

b

c

d b b b b a a a a c

b

a

d

b

a

b←→c

deg

7

3

0

—

c

b

a

d

a

h

deg

7

3

0

—

c

b

a

d

a

h

—

Test conditions

Symbol

IDD

Item

Electrical Characteristics

Supply current

203.126kHz

500mVp-p

sine wave

GLC

GLY

GLD

Low frequency

gain

GLT

4.437525MHz

150mVp-p

sine wave

GHC

GHY

GHD

High frequency

gain

– 4 –

203.126kHz

←→

GHTfcfY

Frequency

4.437525MHz

150mVp-p

sine wave

fD

fT

DGC

response

7

∗

5-staircase

wave

DGY

DGD

DGT

Differential

gain

5-staircase

DPC

DPY

Differential

∗7

wave

DPD

phase

DPT

CXL1502M

Unit Note

Max.

Typ.

Min.

4

VBIAS

(V)

2

∗

3

VBIAS

2

VBIAS

Bias conditions

1

BIAS

V

d

11

c

10 9

a

8

a

7

a

6

a

5

b

SW conditions

4

b b

3 2

b

1

—

∗1

d b a a a a b b b b

—

8

∗

dB

–52

–56

—

d a a a a a b b b b

—

d d a a a a b b b b

—

a c a a a b b b b b

—

∗9

mVp-p

350

—

VID

a b a a a b b b b b

—

+0.5

a a a a a b b b b b

—

a d a a a b b b b b

—

dB

–24

—

VIT

VIC

VIY

VID

b c b b b b a a a a

d←→e

∗10

–0.3

+0.3

∗11

dB

–15

—

VIT

VIC

VIY

VID

b b b b b b a a a a

f←→g

–0.3

+0.3

SNC

No-signal

SNY

Test conditions

Symbol

Item

S/N ratio

∗8

input

SND

SNT

VPC

No-signal input

VPY

VPD

VPT

S/H pulse

coupling

4.437525MHz

←→

4.441431MHz

200mVp-p

sine wave

CCD

Chroma comb

depth min. gain

– 5 –

2.000011MHz

←→

1.992198MHz

200mVp-p

sine wave

YCD

Y-comb

depth min. gain