Sony CXG1030N Datasheet
Power Amplifier for PHS
Description
The CXG1030N is a power amplifier for PHS. This
IC is designed using the Sony’s GaAs J-FET process
and operates at a single power supply.
Features
• Output power 21 dBm
• Positive power supply 3.0 V
• Low current consumption 170 mA
• High power gain 39 dB Typ.
• Small mold package 16-pin SSOP
Structure
GaAs J-FET MMIC
CXG1030N
16 pin SSOP (Plastic)
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage VDD 6V
•Voltage between gate and source
Vgs0 1.5 V
• Drain current IDD 500 mA
• Power dissipation PD 3W
•Channel temperature Tch 175 °C
• Operating temperature Top –35 to +85 °C
• Storage temperature Tstg –65 to +150 °C
Electrical Characteristics
VDD=3.0 V, VCTL=2.0 V, f=1.90 GHz (Ta=25 °C)
Item Symbol Min. Typ. Max. Unit
∗1
Current consumption
∗1
Gate voltage adjustment value
Output power
∗2
Power gain
∗2
Adjacent channel leak power ratio
(600 kHz ±100 kHz)
∗1Values where VGG1 and VGG2 are adjusted so that IDD becomes 170 mA when 21.0 dBm is output.
∗2When 21.0 dBm is output.
IDD 170 mA
VGG2 0 0.4 0.8 V
POUT 21 dBm
GP 36 39 dB
ACPR600 –59 –54 dBc
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E96706-TE
CXG1030N
Block Diagram
RFIN
Gate Bias Circuit
Gate adjustment pin
VDD1VDD2VDD3
VGG1VCTL VGG2
1kΩ
RF
OUT
VGG2
V
GG1
Pin Configuration
1
GND
RFIN
GND
DD1
V
GND
DD2
V
GND
DD3 GND
V
16
GND
GG1
V
CTL
V
GND
VGG2
GND
RF
OUT
Recommended Current Adjustment Method
(1) VGG2/PIN separate adjustment
(VGG2 adjustment 1) (PIN adjustment 1) (VGG2 adjustment 2) (PIN adjustment 2)
When the RF input
(PIN) is off, the current
consumption (IDD) is
adjusted to 170 mA.
Variation of IDD and
POUT due to adjustment
The output power
(POUT) is adjusted
to 21.0 dBm.
IDD=170±20 mA
POUT=21.0 dBm
The current
consumption (IDD)
is finely adjusted to
170 mA.
IDD=170 mA
POUT=21.0±0.2 dBm
The output power
(POUT) is finely
adjusted to 21.0 dBm.
IDD=170±5 mA
POUT=21.0 dBm
(2) Simple adjustment
(IDD read) (VGG2 setting) (PIN adjustment)
When the RF input (PIN)
is off, the gate voltage
(VGG2) is set to 0.4 V
and IDD is read.
Variation of IDD and POUT
due to adjustment
The formula∗1where
VGG2=f (IDD: VGG2=0.4 V)
is used to set VGG2.
∗
1
e.g. VGG2=a-b × IDD IDD=170±5 mA
The output power (POUT)
is adjusted to 21.0 dBm.
POUT=21.0 dBm
—2—
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