Sony CXD3000R Datasheet
Description
The CXD3000R is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter and 1-bit DAC.
Features
• All digital signal processing during playback is
performed with a single chip
• Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular
Velocity)
• Frame jitter free
• 0.5× to 16× continuous playback possible with a
low external clock
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports 1× to 16× playback by switching the built-
in VCO
• The bit clock, which strobes the EFM signal, is
generated by the digital PLL
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error
correction
C1: double correction, C2: quadruple correction
Supported during 16× playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo (built-in oversampling filter)
• 16-bit traverse counter
• Asymmetry compensation circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high
accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo
control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment function
• Surf jump function supporting micro two-axis
Digital Filter and DAC Blocks
• Digital de-emphasis
• Digital attenuation
• 4Fs oversampling filter
• Adoption of a secondary ∆∑ noise shaper
• Supports double-speed playback
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage VDD –0.3 to +4.6 V
• Input voltage VI –0.3 to +4.6 V
(VSS – 0.3V to VDD + 0.3V)
• Output voltage VO –0.3 to +4.6 V
• Storage temperature Tstg –40 to +125 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Recommended Operating Conditions
• Supply voltage VDD
∗
3.0 to 3.6 V
• Operating temperature
Topr –20 to +75 °C
∗
The VDD (min.) for the CXD3000R varies
according to the playback speed and built-in VCO
selection. The VDD (min.) for the CXD3000R under
various conditions are as shown on the following
page.
– 1 –
CXD3000R
E96742A88
CD Digital Signal Processor with Built-in Digital Servo and DAC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
144 pin LQFP (Plastic)
For the availability of this product, please contact the sales office.
– 2 –
CXD3000R
The maximum operating speed graph shows the playback speed VDD (min.) at various temperatures.
The playback conditions are high-speed VCO selected in CAV-W mode with DSPB = 1.
Maximum Operating Speed
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
[V]
[Multiple]
20
19
18
17
16
15
14
13
12
11
10
: +75°C
: +55°C
: +25°C
– 3 –
CXD3000R
Block Diagram
Error
corrector
Noise
Shaper
Peak
detector
OpAmp
AnaSw
A/D
CONVERTER
32K RAM
Serial/parallel
processor
Digital PLL
Vari-Pitch
double speed
MUX
∗
CLV
processor
18-times
oversampling
filter
MIRR
Servo
Interface
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING PWM
GENERATOR
SLED PWM
GENERATOR
Clock
Generator
Subcode
P to W
processor
Timing
Generator1
Subcode Q
processor
Servo
auto
sequencer
CPU interface
4fs Digital Filter
+
1 bit DAC
EFM
Demodulator
Sync
protector
Priority
encoder
D/A data
processor
Digital out
Register
Address
generator
Timing
Generator 2
SERVO DSP
FOCUS SERVO
TRACKING SERVO
SLED SERVO
8
DFCT
FOK
AO1R
AO2F
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
SENS
PSSL
DA01
to DA16
MUTE
COUT
MIRR
DFCT
FOK
DATA
CLOK
XLAT
DOUT
MD2
AO1F
AO2R
XTLO
XTLI
VPCO1
XWO
DAS0
PCMDI
BCKI
LRCKI
DTS1
DTS2
DAS1
VPCO2
XTSL
DAC Block
Signal Processor Block
Servo Block
TEST
TES2
TES3
DV
DD
1
AV
DD
1
AV
DD
2
AV
DD
3
AV
DD
4
AV
DD
5
DV
SS
0
DV
SS
1
AV
SS
1
AV
SS
2
AV
SS
3
XRST
ADIO
DV
DD
0
AV
SS
4
AV
SS
5
49 to 44,
42 to 31,
29, 27
MCKO
V16M
FSTO
C4M
C16M
VCTL
PDO
VCOI
VCOO
PCO
FILI
FILO
CLTV
RFAC
ASYI
ASYO
ASYE
WFCK
SCOR
MON
FSW
MDP
MDS
EXCK
SBSO
SQCK
SQSO
RFDC
TE
SE
FE
VC
CE
PWMI
VCKI
101
103
104
105
106
112
113
114
115
116
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
138
139
140
141
142
3
4
5
6
7
8
9
10
11
12
13
14
16
17
18
20
21
22
23
26
28
30
51
52
55
56
57
59
60
70
69
67
63
64
65
66
61
62
82
83
75
77
78
87
86
79
100
99
95
91
92
OSC
– 4 –
CXD3000R
Pin Configuration
36
35
34
313233
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27 28
29
30
1
40
39
38
37
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
97
96
95
94
91
92
93
100
99
98
101
102
103
104
105
106
107
108
73
74
81
82
83
84
75
76
77
78
88
87
86
85
79
80
89
90
111
109
110
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
FSTO
NC
FSTI
MCKO
XTSL
DV
SS2
DA01
DA02
DA04
DA05
DA06
DV
DD2
DA07
DA08
DA09
DA10
NC
NC
SQCK
SQSO
EXCK
SBSO
SCOR
WFCK
MUTE
DOUT
MD2
DV
DD3
C16M
C4M
NC
DTS2
XRST
SCSY
NC
DA03
NC
NC
DFCT
MIRR
COUT
DV
SS
4
XLAT
DATA
XWO
ATSK
SCLK
DIRC
SENS
DV
DD
4
AV
DD
3
AO1R
AV
SS
3
AV
SS
5
XTLI
XTLO
AV
DD
5
AV
DD
4
AO2F
AO2R
DV
SS
3
DAS1
DAS0
DTS0
DTS1
NC
FOK
CLOK
AO1F
NC
AV
SS
4
NC
PWMI
FSW
MON
MDP
MDS
LOCK
SSTP
DV
SS5
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
DV
DD5
NC
VCOO
VCOI
TEST
TES2
TES3
PDO
VCKI
V16M
AV
DD2
IGEN
AV
SS2
ADIO
RFDC
CE
TE
NC
NC
TESTA
NC
NC
NC
NC
SE
VPCO2
VCTL
FILO
FILI
PCO
CLTV
AV
SS
1
RFAC
BIAS
ASYI
ASYO
AV
DD
1
NC
DV
DD
1
DV
SS
1
ASYE
PSSL
WDCK
LRCK
LRCKI
DA16
PCMDI
DA15
DA14
DA13
DA12
DA11
NC
NC
VC
VPCO1
FE
BCKI
– 5 –
CXD3000R
Pin Description
Pin
No.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
39
40
I
I
I
O
O
I
O
I
O
I
I
I
I
O
I
I
O
O
I
O
I
O
I
O
O
O
O
O
O
1, Z, 0
1, Z, 0
Analog
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Sled error signal input.
Focus error signal input.
Center voltage input.
Wide-band EFM PLL VCO2 charge pump output.
Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $E
command FCSW.
Wide-band EFM PLL VCO2 control voltage input.
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
Master PLL charge pump output.
Multiplier VCO control voltage input.
Analog GND.
EFM signal input.
Asymmetry circuit constant current input.
Asymmetry comparator voltage input.
EFM full-swing output (low = VSS, high = VDD).
Analog power supply.
Digital power supply.
Digital GND.
Asymmetry circuit on/off (low = off, high = on).
Audio data output mode switching input (low: serial, high: parallel).
D/A interface for 48-bit slot. Word clock f = 2Fs.
D/A interface for 48-bit slot. LR clock f = Fs.
LR clock input to DAC (48-bit slot).
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's
complement, MSB first) when PSSL = 0.
Audio data input to DAC (48-bit slot).
DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.
Bit clock input to DAC (48-bit slot).
DA14 output when PSSL = 1, 64-bit slot serial data output (two's
complement, LSB first) when PSSL = 0.
DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0.
DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0.
DA11 output when PSSL = 1, GTOP output when PSSL = 0.
DA10 output when PSSL = 1, XUGF output when PSSL = 0.
DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
SE
FE
VC
VPCO1
VPCO2
VCTL
FILO
FILI
PCO
CLTV
AVSS1
RFAC
BIAS
ASYI
ASYO
AVDD1
DVDD1
DVSS1
ASYE
PSSL
WDCK
LRCK
LRCKI
DA16
PCMDI
DA15
BCKI
DA14
DA13
DA12
DA11
DA10
DA09
Symbol I/O Description
– 6 –
CXD3000R
41
42
43
44
45
46
47
48
49
50
51
52
53
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
75
76
77
78
79
80
81
82
O
O
O
O
O
O
O
O
I
O
I
O
O
O
I
O
I
O
O
O
I
O
I
I
I
I
I
I
I
I
I
O
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, Z, 0
DA08 output when PSSL = 1, GFS output when PSSL = 0.
DA07 output when PSSL = 1, RFCK output when PSSL = 0.
Digital power supply.
DA06 output when PSSL = 1, C2PO output when PSSL = 0.
DA05 output when PSSL = 1, XRAOF output when PSSL = 0.
DA04 output when PSSL = 1, MNT3 output when PSSL = 0.
DA03 output when PSSL = 1, MNT2 output when PSSL = 0.
DA02 output when PSSL = 1, MNT1 output when PSSL = 0.
DA01 output when PSSL = 1, MNT0 output when PSSL = 0.
Digital GND.
Crystal selection input.
Clock output. Inverted output of XTLI.
2/3 frequency division input for XTLI pin.
2/3 frequency division output for XTLI pin. Does not change with variable pitch.
1/4 frequency division output for XTLI pin. Changes with variable pitch.
16.9344MHz output. Changes simultaneously with variable pitch.
Digital power supply.
Digital Out on/off control (low = off, high = on).
Digital Out output.
Mute (low: off, high: on).
WFCK (Write Frame Clock) output.
Outputs a high signal when either subcode sync S0 or S1 is detected.
Sub P to W serial output.
SBSO readout clock input.
Sub Q 80-bit and PCM peak and level data 16-bit output.
SQSO readout clock input.
GRSCOR re-synchronization input.
System reset. Reset when low.
DAC test pin. Normally fixed to high.
DAC test pin. Normally fixed to high.
DAC test pin. Normally fixed to low.
DAC sync window open input. Normally high, window open when low.
DAC test pin. Normally fixed to high.
DAC test pin. Normally fixed to low.
Digital GND.
Analog GND.
Channel 2 DAC PWM output (reversed phase).
DA08
DA07
DVDD2
DA06
DA05
DA04
DA03
DA02
DA01
DVSS2
XTSL
MCKO
FSTI
FSTO
C4M
C16M
DVDD3
MD2
DOUT
MUTE
WFCK
SCOR
SBSO
EXCK
SQSO
SQCK
SCSY
XRST
DTS2
DTS1
DTS0
XWO
DAS0
DAS1
DVSS3
AVSS4
AO2R
Pin
No.
Symbol I/O Description
– 7 –
CXD3000R
83
84
85
86
87
88
89
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
111
112
113
114
115
116
117
118
119
120
121
122
O
O
I
O
O
O
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I
O
O
O
O
I/O
I
O
O
O
1, Z, 0
1, 0
1, Z, 0
1, Z, 0
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Channel 2 DAC PWM output (forward phase).
Analog power supply.
Master clock power supply.
Master clock crystal oscillation circuit output.
Master clock crystal oscillation circuit input.
Master clock GND.
Analog GND.
Channel 1 DAC PWM output (forward phase).
Channel 1 DAC PWM output (reversed phase).
Analog power supply.
Digital power supply.
SENS output to CPU.
Used during 1-track jumps.
SENS serial data readout clock input.
Anti-shock pin.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
Digital GND.
Track count signal I/O.
Mirror signal I/O.
Defect signal I/O.
Focus OK signal I/O.
Test pin. Leave this open.
Spindle motor external pin input.
Spindle motor output filter switching output.
GRSCOR output when $8 command SCOR SEL = high.
Spindle motor on/off control output.
Spindle motor servo control output.
Spindle motor servo control output.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low. Input when
LKIN = high.
Disc innermost track detection signal input.
Digital GND.
Sled drive output.
Sled drive output.
Tracking drive output.
AO2F
AVDD4
AVDD5
XTLO
XTLI
AVSS5
AVSS3
AO1F
AO1R
AVDD3
AVDD4
SENS
DIRC
SCLK
ATSK
DATA
XLAT
CLOK
DVSS4
COUT
MIRR
DFCT
FOK
TESTA
PWMI
FSW
MON
MDP
MDS
LOCK
SSTP
DVSS5
SFDR
SRDR
TFDR
Pin
No.
Symbol I/O Description
– 8 –
CXD3000R
∗
In the CXD3000R, the following pins are NC.
Pins 1, 2, 19, 35, 36, 37, 38, 54, 71, 72, 73, 74, 90, 107, 108, 109, 110, 127, 143 and 144
Notes) • The 64-bit slot is an LSB first, two's complement output. The 48-bit slot is an MSB first, two's
complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before
sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
123
124
125
126
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
O
O
O
O
I
I
I
I
O
I
O
I
O
I
I
I
1, 0
1, 0
1, 0
1, 0
1, Z, 0
1, Z, 0
Tracking drive output.
Focus drive output.
Focus drive output.
Digital power supply.
Analog EFM PLL oscillation circuit output.
Analog EFM PLL oscillation circuit input. flock = 8.6436MHz
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Analog EFM PLL charge pump output.
Variable pitch clock input from the external VCO. fcenter = 16.9344MHz
Set VCKI to low when the external clock is not input to this pin.
Wide-band EFM PLL VCO2 oscillation output.
Analog power supply.
Connects the operational amplifier current source reference resistance connection.
Analog GND.
Operational amplifier output.
RF signal input.
Center servo analog input.
Tracking error signal input.
TRDR
FFDR
FRDR
DVDD5
VCOO
VCOI
TEST
TES2
TES3
PDO
VCKI
V16M
AVDD2
IGEN
AVSS2
ADIO
RFDC
CE
TE
Pin
No.
Symbol I/O Description
– 9 –
CXD3000R
Electrical Characteristics
1. DC Characteristics (VDD = AVDD = 3.3V ± 10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Input leak current (1)
Input leak current (2)
Tri-state pin
output leak current
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
Input voltage
Input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Input voltage (1)
Input voltage (2)
Input voltage (3)
Input voltage (4)
Input voltage (5)
Input voltage (6)
Output voltage (1)
Output voltage (2)
Output voltage (3)
Output voltage (4)
Output voltage (5)
VIH (1)
VIL (1)
VIH (2)
VIL (2)
VIH (3)
VIL (3)
VIH (4)
VIL (4)
VIN (5)
VIN (6)
VOH (1)
VOL (1)
VOH (2)
VOL (2)
VOH (3)
VOL (3)
VOL (4)
VOH (5)
VOL (5)
ILI (1)
ILI (2)
ILO
0.7VDD
0.7VDD
0.7VDD
0.7VDD
VSS
VSS
VDD – 0.4
0
VDD – 0.4
0
VDD – 0.2
0
0
VDD – 0.5
0
–10
–20
–5
0.2VDD
0.2VDD
0.2VDD
0.2VDD
VDD
VDD
VDD
0.4
VDD
0.4
VDD
0.4
0.4
VDD
0.4
10
20
5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
Conditions Min. Typ. Max. Unit
Applicable pins
Applicable pins
∗1
BCKI, DTS0, DTS1, DTS2, LRCKI, PCMDI, TES2, TES3, TEST
∗2
ASYE, FSTI, VCKI
∗3
ATSK, DATA, DIRC, MD2, PWMI, SSTP, XLAT, XTSL, XWO
∗4
CLOK, EXCK, MUTE, SCLK, SCSY, SQCK, XRST
∗5
ASYI, BIAS, CLTV, FILI, IGEN, RFAC, VCTL
∗6
CE, FE, SE, TE, VC, RFDC
∗7
ASYO, C16M, C4M, DA01 to DA16, DAS0, DAS1, DOUT, FFDR, FRDR, FSTO, LRCK, MON, PSSL,
SBSO, SCOR, SFDR, SQSO, SRDR, TFDR, TRDR, WDCK, WFCK
∗8
FSW
∗9
MCKO
∗10
AO1F, AO1R, AO2F, AO2R, MDP, MDS, PCO, PDO, SENS, V16M, VPCO1, VPCO2
∗11
FILO
∗12
COUT, DFCT, FOK, LOCK, MIRR
Schmitt input
VI ≤ 5.5V
VI ≤ 5.5V
Schmitt input
Analog input
Analog input
IOH = –8mA
IOL = 8mA
IOH = –4mA
IOL = 4mA
IOH = –2mA
IOL = 4mA
IOL = 4mA
IOH = –0.28mA
IOH = 0.36mA
VI = 0 to 5.5V
VI = 0.25VDD
to 0.75VDD
VO = 0 to 3.6V
∗1, ∗12
∗2
∗3
∗4
∗5
∗6
∗9
∗7, ∗10
∗12
∗7, ∗10
∗12
∗8
∗11
∗3, ∗4, ∗5
∗6
∗10
2. AC Characteristics
(1) XTLI pin, VCOI pin
(a) When using self-excited oscillation
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ±10%)
(b) When inputting pulses to XTLI and VCOI pins
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ±10%)
(c) When inputting sine waves to XTLI and VCOI pins via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ±10%)
– 10 –
CXD3000R
Oscillation
frequency
fMAX 7
34
MHz
Item Symbol Min. Typ. Max.
Unit
High level pulse
width
tWHX
13 500
ns
Low level pulse
width
tWLX
13 500
ns
Pulse cycle
tCX
26 1000
ns
Input high level VIHX VDD – 1.0
V
Input low level VILX 0.8
V
Rise time,
fall time
tR, tF
10
ns
Item Symbol Min. Typ. Max. Unit
Input amplitude VI 2.0 VDD + 0.3 Vp-p
Item Symbol Min. Typ. Max. unit
tR tF
tWHX
tWLX
tCX
VILX
VIHX × 0.1
V
IHX × 0.9
V
IHX
XTLI
V
DD/2
– 11 –
CXD3000R
(2) CLOK, DATA, XLAT, SQCK and EXCK pins
(VDD = AVDD = 3.3V ±10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK SQCK frequency
EXCK SQCK pulse width
fCK
tWCK
tSU
tH
tD
tWL
fT
tWT
30
30
30
30
750
750
16
0.65
MHz
ns
ns
ns
ns
ns
MHz
ns
Item Symbol Min. Typ. Max. Unit
tWCK tWCK
1/fCK
tH
tSU
tWL
tD
1/fT
tWT tWT
tH
tSU
CLOK
DATA
XLAT
EXCK
SQCK
SBSO
SQSO
– 12 –
CXD3000R
(4) COUT, MIRR and DFCT pins
Operating frequency
(VDD = AVDD = 3.3V ±10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
COUT maximum operating frequency
MIRR maximum operating frequency
DFCT maximum operating frequency
fCOUT
fMIRR
fDFCTH
40
40
5
kHz
kHz
kHz
∗1
∗2
∗3
Item Symbol Min. Typ. Max. Unit
Conditions
∗
1
When using a high-speed traverse TZC.
∗
2
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.11VDD to 0.23VDD
• ≤ 25%
∗
3
During complete RF signal omission.
When settings related to DFCT signal generation are Typ.
(3) SCLK pin
SCLK frequency
SCLK pulse width
Delay time
fSCLK
tSPW
tDLS
31.3
15
16 MHz
ns
µs
Item Symbol Min. Typ. Max. Unit
tSPWtDLS
1/fSCLK
MSB LSB•••
•••
XLAT
SCLK
Serial Read Out Data
(SENS)
A
B
B
A + B
– 13 –
CXD3000R
(5) BCKI, LRCKI and PCMDI pins (VDD = 3.3V ±10%, Topr = –20 to +75°C)
Input BCKI frequency
Input BCKI pulse width
Input data setup time
Input data hold time
Input LRCK setup time
Input LRCK hold time
tBCK
tWIB
tIDS
tIDH
tILRH
tILRS
100
10
15
10
15
4.5 MHz
ns
Item Symbol Min. Typ. Max. Unit
tILRH
tWIB tWIB
tIDHtIDS
tILRS
50%
BCKI
PCMDI
LRCKI
– 14 –
CXD3000R
DAC Analog Characteristics
Measurement conditions
(Ta = 25°C, VDD = 3.3V, Fs = 44.1kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, master clock = 768Fs)
S/N ratio
THD + N
Dynamic range
Channel separation
Output level
Difference in gain between channels
93
0.015
91
91
1.7028
0.1
dB
%
dB
dB
V (rms)
dB
Item
Typ.
Unit
(EIAJ)
∗
1
(EIAJ)
(EIAJ)
∗
1, ∗2
(EIAJ)
Remarks
CXD3000R
AO1F
AO1R
3.9k
130k
3.9k
3.9k
130k
3.9k
47p
47p
4.7k
4.7k
4.7k
820p
4.7k
820p
4.7k 4.7k
0.015
4.7k
1800p 82p
12k
100
22
OUTPUT
∗1
Using "A" weighting filter
∗2
–60 dB, 1kHz input
The analog characteristics measurement circuit is shown below.
AO1R
AO2F
AO2R
AO1F
TEST DISK
DATA
Audio Circuit
Analog
1ch
2ch
Audio Analyzer
SHIBASOKU (AM51A)768fs
CXD3000R
Block diagram of analog characteristics measurement
– 15 –
CXD3000R
Contents
[1] CPU Interface
§1-1. CPU Interface Timing ........................................................................................................................16
§1-2. CPU Interface Command Table ........................................................................................................ 16
§1-3. CPU Command Presets ....................................................................................................................26
§1-4. Description of SENS Signals ............................................................................................................. 31
[2] Subcode Interface
§2-1. P to W Subcode Readout .................................................................................................................. 60
§2-2. 80-bit Sub Q Readout ........................................................................................................................ 60
[3] Description of Modes
§3-1. CLV-N Mode ...................................................................................................................................... 66
§3-2. CLV-W Mode ..................................................................................................................................... 66
§3-3. CAV-W Mode ..................................................................................................................................... 66
[4] Description of Other Functions
§4-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 68
§4-2. Frame Sync Protection ...................................................................................................................... 70
§4-3. Error Correction ................................................................................................................................. 70
§4-4. DA Interface ....................................................................................................................................... 71
§4-5. Digital Out .......................................................................................................................................... 74
§4-6. Servo Auto Sequence ....................................................................................................................... 75
§4-7. Digital CLV ......................................................................................................................................... 83
§4-8. Playback Speed ................................................................................................................................ 84
§4-9. DAC Block Playback Speed .............................................................................................................. 85
§4-10. DAC Block Input Timing .................................................................................................................... 85
§4-11. Asymmetry Compensation ................................................................................................................ 86
§4-12. CXD3000 Clock System .................................................................................................................... 87
[5] Description of Servo Signal Processing System Functions and Commands
§5-1. General Description of the Servo Signal Processing System ............................................................ 88
§5-2. Digital Servo Block Master Clock (MCK) ........................................................................................... 89
§5-3. AVRG Measurement and Compensation .......................................................................................... 89
§5-4. E:F Balance Adjustment Function ..................................................................................................... 91
§5-5. FCS Bias Adjustment Function .......................................................................................................... 91
§5-6. AGCNTL Function ............................................................................................................................. 93
§5-7. FCS Servo and FCS Search ............................................................................................................. 95
§5-8. TRK and SLD Servo Control ............................................................................................................. 96
§5-9. MIRR and DFCT Signal Generation .................................................................................................. 97
§5-10. DFCT Countermeasure Circuit .......................................................................................................... 98
§5-11. Anti-Shock Circuit .............................................................................................................................. 98
§5-12. Brake Circuit ...................................................................................................................................... 99
§5-13. COUT Signal ................................................................................................................................... 100
§5-14. Serial Readout Circuit ...................................................................................................................... 100
§5-15. Writing to the Coefficient RAM ........................................................................................................ 101
§5-16. PWM Output .................................................................................................................................... 101
§5-17. DIRC Input Pin ................................................................................................................................. 103
§5-18. Servo Status Changes Produced by the LOCK Signal ................................................................... 104
§5-19. Description of Commands and Data Sets ....................................................................................... 104
§5-20. List of Servo Filter Coefficients ........................................................................................................ 117
§5-21. Filter Composition ............................................................................................................................ 119
§5-22. TRACKING and FOCUS Frequency Response .............................................................................. 126
[6] Application Circuit .................................................................................................................................. 127
Explanation of abbreviations AVRG: Average
AGCNTL: Auto gain control
FCS: Focus
TRK: Tracking
SLD: Sled
DFCT: Defect
– 16 –
CXD3000R
[1] CPU Interface
§1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
• The internal registers are initialized by a reset when XRST = 0.
§1-2. CPU Interface Command Table
Total bit length for each register
Register
0 to 2
3
4 to 6
7
8
9
A
B
C to D
E
8 bit
8 to 24 bit
16 bit
20 bit
24 bit
20 bit
28 bit
20 bit
16 bit
20 bit
Total bit length
30ns or more
D18 D19 D20 D21 D22 D23
750ns or more
Valid
CLOK
DATA
XLAT
Registers
D0 D1
– 17 –
CXD3000R
FOCUS SERVO ON
(FOCUS GAIN
NORMAL)
FOCUS SERVO ON
(FOCUS GAIN
DOWN)
FOCUS SERVO OFF,
0V OUT
FOCUS SERVO OFF,
FOCUS SEARCH
VOLTAGE OUT
FOCUS SEARCH
VOLTAGE DOWN
FOCUS SEACH
VOLTAGE UP
ANTI SHOCK ON
ANTI SHOCK OFF
BRAKE ON
BRAKE OFF
TRACKING GAIN
NORMAL
TRACKING GAIN UP
TRACKING GAIN UP
FILTER SELECT 1
TRACKING GAIN UP
FILTER SELECT 2
1
1
0
0
0
0
1
0
—
—
—
—
—
—
0
1
—
—
—
—
0
—
1
0
—
—
—
—
—
—
0
1
1
1
—
—
—
—
0
1
—
—
—
—
—
—
0
1
—
—
—
—
—
—
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0 0 0 0
0 0 0 1
FOCUS
CONTROL
TRACKING
CONTROL
Register
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Command Table ($0X to 1X)
—: Don’t care
– 18 –
CXD3000R
TRACKING SERVO OFF
TRACKING SERVO ON
FORWARD TRACK JUMP
REVERSE TRACK JUMP
SLED SERVO OFF
SLED SERVO ON
FORWARD SLED MOVE
REVERSE SLED MOVE
SLED KICK LEVEL
(±1 × basic value) (Default)
SLED KICK LEVEL
(±2
×
basic value)
SLED KICK LEVEL
(±3
×
basic value)
SLED KICK LEVEL
(±4
×
basic value)
0
0
1
1
—
—
—
—
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0
1
—
—
—
—
—
—
—
—
0
0
1
1
—
—
—
—
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
3
0 0 1 0
0 0 1 1
TRACKING
MODE
SELECT
Register
Command
Address
D23 to D20
Register
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
—: Don’t care
Command Table ($2X to 3X)
– 19 –
CXD3000R
KRAM DATA (K00)
SLED INPUT GAIN
KRAM DATA (K01)
SLED LOW BOOST FILTER A-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K05)
SLED OUTPUT GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K07)
SLED AUTO GAIN
KRAM DATA (K08)
FOCUS HIGH CUT FILTER A
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0C)
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 0 0SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($340X)
– 20 –
CXD3000R
KRAM DATA (K10)
FOCUS PHASE COMPENSATE FILTER B
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K14)
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
KRAM DATA (K18)
FIX
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K1A)
TRACKING HIGH CUT FILTER A
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 0 1SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($341X)
– 21 –
CXD3000R
KRAM DATA (K20)
TRACKING PHASE COMPENSATE FILTER A
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 1 0SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($342X)
– 22 –
CXD3000R
KRAM DATA (K30)
FIX
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K32)
NOT USED
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KRAM DATA (K3F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 1 1SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($343X)
– 23 –
CXD3000R
KRAM DATA (K40)
TRACKING HOLD FILTER INPUT GAIN
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K46)
NOT USED
KRAM DATA (K47)
NOT USED
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 1 0 0SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($344X)
– 24 –
CXD3000R
0 0 1 1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
FOCUS BIAS LIMIT
FOCUS BIAS DATA
TRVSC DATA
FOCUS SEARCH SPEED/
VOLTAGE/AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE/AUTO GAIN
FZSL/SLED MOVE/
Voltage/AUTO GAIN
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
SERIAL DATA READ
MODE/SELECT
FOCUS BIAS
Operation for MIRR/
DFCT/FOK
TZC/COUT
BOTTOM/MIRR
Filter
Others
3
0 0 1 1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
FBL9
FB9
TV9
FBL8
FB8
TV8
FBL7
FB7
TV7
FBL6
FB6
TV6
FBL5
FB5
TV5
FBL4
FB4
TV4
FBL3
FB3
TV3
FBL2
FB2
TV2
FBL1
FB1
TV1
—
—
TV0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
FT1
TDZC
FZSH
VCLM
DAC
0
SFO2
FT0
DTZC
FZSL
VCLC
SD6
FBON
SFO1
FS5
TJ5
SM5
FLM
SD5
FBSS
SDF2
FS4
TJ4
SM4
FLC0
SD4
FBUP
SDF1
FS3
TJ3
SM3
RFLM
SD3
FBV1
MAX2
FS2
TJ2
SM2
RFLC
SD2
FBV0
MAX1
FS1
TJ1
SM1
AGF
SD1
0
SFOX
FS0
TJ0
SM0
AGT
SD0
TJD0
BTF
FTZ
SFJP
AGS
DFSW
0
FPS1
D2V2
FG6
TG6
AGJ
LKSW
0
FPS0
D2V1
FG5
TG5
AGGF
TBLM
0
TPS1
D1V2
FG4
TG4
AGGT
TCLM
0
TPS0
D1V1
FG3
TG3
AGV1
FLC1
0
0
RINT
FG2
TG2
AGV2
TLC2
0
SJHD
0
FG1
TG1
AGHS
TLC1
0
INBK
0
FG0
TG0
AGHT
TLC0
0
MTI0
0
1
1
1
1
1
1
1
1
0
1
F1NM
0
F1DM
AGG4
F3NM
XT4D
F3DM
XT2D
T1NM
0
T1UM
DRR2
T3NM
DRR1
T3UM
DRR0
DFIS
0
TLCD
ASFG
0
0
LKIN
LPAS
COIN
SRO1
MDFI
SRO0
MIRI
AGHF
XT1D
0
1
1
0
0
0
1
COSS
0
COTS
0
CETZ
0
CETF
0
COT2
0
COT1
0
MOT2
0
0
0
BTS1
0
BTS0
0
MRC1
0
MRC0
0
0
0
0
0
0
0
0
0
SELECT
Register
Command
Address 1
D23 to D20 D19 D18 D17 D16
Address 2
D15 D14 D13 D12
Data 1
D11 D10 D9 D8
Data 2
D7 D6 D5 D4
Data 3
D3 D2 D1 D0
Address
D23 to D20 D19 D18 D17 D16
Data 1
D15 D14 D13 D12
Data 2
D11 D10 D9 D8
Data 3
D7 D6 D5 D4
Data 4
D3 D2 D1 D0
Command Table ($34FX to 3FX)
—: Don’t care
– 25 –
CXD3000R
Auto sequence
Blind (A, E),
Brake (B),
Overflow (C, G)
Sled KICK,
BRAKE (D),
KICK (F)
Auto sequence
(N)
track jump
count setting
MODE
specification
Function
specification
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD mode
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
AS3
TR3
SD3
32768
CD-
ROM
DCLV
ON/OFF
0
32768
Gain
MDP1
DCLV
PWM MD
CM3
AS2
TR2
SD2
16384
DOUT
Mute
DSPB
ON/OFF
0
16384
Gain
MDP0
TB
CM2
AS1
TR1
SD1
8192
DOUT
Mute-F
ASEQ
ON/OFF
Mute
8192
Gain
MDS1
TP
CM1
AS0
TR0
SD0
4096
WSEL
DPLL
ON/OFF
ATT
4096
Gain
MDS0
CLVS
Gain
CM0
MT3
0
KF3
2048
VCO
SEL
BiliGL
MAIN
PCT1
2048
Gain
DCLV1
VP7
EPWM
MT2
0
KF2
1024
ASHS
BiliGL
SUB
PCT2
1024
Gain
DCLV0
VP6
SPDC
MT1
0
KF1
512
SOCT
FLFC
DADS
512
PCC1
VP5
ICAP
MT0
0
KF0
256
VCO
SEL2
0
SOC2
256
PCC0
VP4
SFSL
LSSL
0
0
128
KSL3
DAC
EMP
AT1D7
128
0
VP3
VC2C
0
0
0
64
KSL2
DAC
ATT
AT1D6
64
0
VP2
HIFC
0
0
0
32
KSL1
0
AT1D5
32
0
VP1
LPWR
0
0
0
16
KSL0
0
AT1D4
16
0
VP0
VPON
—
—
—
8
VC01
CS1
PLM3
AT1D3
8
—
—
Gain
CAV1
—
—
—
4
VCO1
CS0
PLM2
AT1D2
4
—
—
Gain
CAV0
—
—
—
2
VCO2
THRU
PLM1
AT1D1
2
—
—
FCSW
—
—
—
1
0
PLM0
AT1D0
1
—
—
0
4
5
6
7
8
9
A
B
C
D
E
Register
Command
Address
D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
Data 1 Data 2 Data 3 Data 4
Command Table ($4X to EX)
—: Don’t care
MODE
specification
1 0 0 0 ERC4
SCOR
SEL
SCSY — — — — —8
Audio CTRL
1 0 1 0 AT2D7 AT2D6 AT2D5 AT2D4 AT2D3 AT2D2 AT2D1 AT2D0A
Register
Command
Address Data 1 Data 2 Data 3 Data 4
D7 D6 D5 D4 D3 D2 D1 D0
Data 5 Data 6
– 26 –
CXD3000R
FOCUS SERVO OFF,
0V OUT
TRACKING GAIN UP
FILTER SELECT 1
TRACKING SERVO OFF
SLED SERVO OFF
SLED KICK LEVEL
(±1 × basic value) (Default)
KRAM DATA
($3400XX to $344fXX)
0
0
0
0
0
0
0
0
0
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
2
0 0 0 0
0 0 0 1
0 0 1 0
FOCUS
CONTROL
TRACKING
CONTROL
TRACKING
MODE
Register
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Register
Command
3 SELECT
Address
D23 to D20
0 0 1 1
0 0 1 1 0 1 0 0 0 See "Coefficient ROM Preset Values Table".
0 0 0 0 — — — — — — — —
—
— — — — — — —
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D0 D0
Address 1
D23 to D20 D19 D18 D17 D16
Address 2
D15 D14 D13 D12
Address 3
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D0 D0
§1-3. CPU Command Presets
Command Preset Table ($0X to 34X)
—: Don’t care
– 27 –
CXD3000R
0 0 1 1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
FOCUS BIAS LIMIT
FOCUS BIAS DATA
TRVSC DATA
FOCUS SEARCH SPEED/
VOLTAGE AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE AUTO GAIN
FZSL/SLED MOVE/
Voltage/AUTO GAIN
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
SERIAL DATA READ
MODE/SELECT
FOCUS BIAS
Operation for MIRR/
DFCT/FOK
3
0 0 1 1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Filter
Others
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELECT
Register
Command
Address 1
D23 to D20 D19 D18 D17 D16
Address 2
D15 D14 D13 D12
Data 1
D11 D10 D9 D8
Data 2
D7 D6 D5 D4
Data 3
D3 D2 D1 D0
Address
D23 to D20 D19 D18 D17 D16
Data 1
D15 D14 D13 D12
Data 2
D11 D10 D9 D8
Data 3
D7 D6 D5 D4
Data 4
D3 D2 D1 D0
Command Preset Table ($34FX to 3FX)
—: Don’t care
– 28 –
CXD3000R
Auto sequence
Blind (A, E),
Brake (B),
Overflow (C, G)
Sled KICK,
BRAKE (D),
KICK (F)
Auto sequence
(N)
track jump
count setting
MODE
specification
Function
specification
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD mode
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
—
—
—
0
0
1
1
0
—
—
0
—
—
—
0
0
0
1
0
—
—
0
—
—
—
0
0
0
1
0
—
—
0
—
—
—
0
0
1
1
0
—
—
0
4
5
6
7
8
9
A
B
C
D
E
Register
Command
Address
D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8
Data 1 Data 2 Data 3 Data 4
Command Preset Table ($4X to EX)
—: Don’t care
MODE
specification
1 0 0 0 0 0 0 — — — — —8
Audio CTRL
1 0 1 0 1 1 1 1 1 1 1 1A
Register
Command
Address Data 1 Data 2 Data 3 Data 4
D7 D6 D5 D4 D3 D2 D1 D0
Data 5 Data 6
– 29 –
CXD3000R
<Coefficient ROM Preset Values Table (1)>
ADDRESS
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix
∗
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
DATA CONTENTS
– 30 –
CXD3000R
<Coefficient ROM Preset Values Table (2)>
ADDRESS
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
Fix
∗
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
DATA CONTENTS
∗
Fix indicates that normal preset values should be used.
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