Sony CXD2728Q Datasheet

Single-Chip Dolby Pro Logic Surround Decoder

Description

The CXD2728Q is a CMOS LSI developed for Dolby Pro Logic Surround. A SRAM for short delay and AD/DA converters are built in, and all functions necessary for Dolby Pro Logic Surround such as an adaptive matrix, a passive decoder including Modified Dolby B-type NR, auto input balance, a noise sequencer and center channel mode control are contained on a single chip. Further, this LSI also supports Dolby 3 Stereo and Virtual Dolby Surround.

Features

• Dolby Pro Logic Surround decoding with a single

chip

• 2-channel 1-bit AD converter and decimation filter

• 4-channel 1-bit DA converter and oversampling filter

• 32K-bit SRAM for short delay

• No separation or other variance for digital

processing

• External parts reduced due to the built-in AD/DA

converters

Functions

• Adaptive matrix

• Center channel mode control

(Normal/Phantom/Wide)

• Dolby 3 Stereo

• Auto input balance control (ON/OFF)

• Noise sequencer

• Variable delay time (0 to 46.4ms)

• 7kHz low-pass filter (12dB/Oct)

• Modified Dolby B-type NR

• Simple SFC function

• Virtual Dolby Surround

• SFC mode Absolute Maximum Ratings (Ta = 25°C, VSS = 0V)

• Supply voltage VDD VSS – 0.5 to +4.6 V

AVDD ∗1AVss – 0.5 to + 4.6 V

• Input voltage VID VSS – 0.5 to VDD + 0.5 V

∗2

Vss – 0.5 to 5 to Min (VDD + 4.6, 7.0)

VIA ∗3AVss – 0.5 to AVD + 0.5 V

• Output voltage VOD VSS – 0.5 to VDD + 0.5 V

∗4

Vss – 0.5 to Min (VDD + 4.6, 7.0)

VOA ∗3AVss – 0.5 to AVDD + 0.5

• Storage temperature

Tstg –55 to +150 °C

∗1

Analog power supply including AVDX

∗2

Pins 28, 31, 32 and 76

∗3

Analog input/output pin

∗4

Pin 29

Recommended Operating Conditions

• Supply voltage VDD 3.0 to 3.6 (3.3 typ.) V

AVDD 3.1 to 3.5 (3.3 typ.) V

Note) Use this IC under the following condition

during the normal operation except for the power on.

• Supply voltage differenceVDD ≤ AVDD + 0.3 V VSS ≤ AVSS – 0.3 V

• Operating temperature

Ta –20 to +75 °C

Input/Output Capacitance (VDD = VI = 0V, f = 1MHz)

• Input capacitance CIN 9 (max.) pF

• Output capacitance COUT 11 (max.) pF

• Input/output capacitance

CI/O 11 (max.) pF

Maximum Current Consumption

(Ta = 25°C, VDD = 3.6V)

• Digital/analog block total: 75.8mA

Dolby level

• During analog input: 200 to 300mVrms

• During digital input: –20dBFS

Analog Characteristics

Conditions: Pro Logic ON

Measurement at Dolby level = 300mVrms

• S/N: L, Rch = 72dB, C, Sch = 70dB

• THD + N: L, Rch = 0.03%, C, Sch = 0.03%

∗

All values typ.

Structure

Silicon gate CMOS

Applications

Equipment having Dolby Pro Logic Surround function such as AV amplifiers, receivers and compact music systems

– 1 –

E98Z02-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD2728Q

80 pin QFP (Plastic)

This device is available only to parties obtaining the license from Dolby Laboratories Licensing Corporation. "Dolby", the double-D symbol and "Pro Logic" are trademarks of Dolby Laboratories Licensing Corporation.

– 2 –

CXD2728Q

Block Diagram

AO1N

RIN

AO1P

LIN

DAC1

DAC2

DAC3

DAC4

ADC2

ADC1

DSP

32K bit DELAY RAM

CLOCK GENERATOR

/TIMING CIRCUIT

MICROCOMPUTER I/F

SERIAL DATA I/F

XTLI

XTLO

BFOT

XMST

BCK

REDY

XLAT

SCK

RVDT

LRCK

AO2N AO2P

AO3N AO3P

AO4N AO4P

4 5

8 9

16 17

20 21

Pin Configuration

AVS6

RREF

AVD2

AVD4

AO2N

AO2P

AVS4

AO4N

AO4P

AVD6

AVDX

XTLO

XTLI

AVSX

AVD5

AO3N

AO3P

AVS5

AVS3

AO1N

AO1P

AVD3

AVD1

LREF

T.P

XMST

LRCK

LIN

AVS1

SS0

SCK

REDY

T.P

XLAT

RVDT

DD1

XS24

BFOT

T.P

BCK

SS1

T.P

6364

66 67 68

69 70

71 72 73 74 75 76

77 78

79 80

RIN

AVS2

SS5

T.P

XRST

T.P

DD0

T.P

SS4

– 3 –

CXD2728Q

Pin Description Notations in parentheses indicate the fixed pin connection status.

(OPEN): Open, (VDD): +3.3V digital power supply, (AVDD): +3.3V analog power supply (Vss): Digital GND, (AVss): Analog GND

Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

29 30

31 32 33

Symbol RREF AVD2 AVD4 AO2N AO2P AVS4 AVS6 AO4N AO4P AVD6 AVDX XTLO XTLI AVSX AVD5 AO3N AO3P AVS5 AVS3 AO1N AO1P AVD3 AVD1 LREF LIN AVS1 VSS0 SCK

REDY T.P

XLAT RVDT VDD1

I/O

O — —

I — —

O — —

I — —

O O

I —

Description R-ch AD converter reference. R-ch AD converter power supply. (AVDD) R-ch DA converter power supply. (AVDD) R-ch DA converter opposite phase PWM output. R-ch DA converter forward phase PWM output. R-ch DA converter GND. (AVSS) S-ch DA converter GND. (AVSS) S-ch DA converter opposite phase PWM output. S-ch DA converter forward phase PWM output. S-ch DA converter power supply. (AVDD) Oscillator analog power supply. (AVDD) Oscillator output. Oscillator input. Oscillator analog GND. (AVSS) C-ch DA converter power supply. (AVDD) C-ch DA converter opposite phase PWM output. C-ch DA converter forward phase PWM output. C-ch DA converter GND. (AVSS) L-ch DA converter GND. (AVSS) L-ch DA converter opposite phase PWM output. L-ch DA converter forward phase PWM output. L-ch DA converter power supply. (AVDD) L-ch AD converter power supply. (AVDD) L-ch AD converter reference. L-ch AD converter analog input L-ch AD converter GND. (AVSS) Digital GND. (VSS) Shift clock input for microcomputer interface. Transfer enabling signal output for microcomputer interface. Transfer prohibited

when Low. Test monitor. Normally outputs Hi-Z. (OPEN) Latch input for microcomputer interface. Data input for microcomputer interface. Digital power supply. (VDD)

– 4 –

CXD2728Q

Notations in parentheses indicate the fixed pin connection status.

(OPEN): Open, (VDD): +3.3V digital power supply, (AVDD): +3.3V analog power supply (Vss): Digital GND, (AVss): Analog GND

∗

The CXD2728Q has 3 digital and 7 analog power supplies and the order of turning them on is not specified.

34 35 36 37 38 39 40 41 42

43 to 45

47 to 50

52 to 56

58 to 64

66 to 70

72 to 75

76 77 78 79 80

XS24 BFOT T.P SI T.P BCK VSS1 LRCK XMST T.P VSS2 T.P VDD2 T.P VSS3 T.P VSS4 T.P VDD0 T.P XRST T.P VSS5 AVS2 RIN

I O O

I/O

—

I/O

—

— —

Serial data 24-/32-bit slot selection. 24-bit slot when Low. [valid for slave mode] Clock frequency-division output. (384/768/256/512fs) Test output. Normally outputs Low. (OPEN) 1-sampling 2-channel serial data input. Test input. Normally inputs Low. (VSS) Serial bit transfer clock for serial input data SI. Digital GND. (VSS) Sampling frequency clock for serial input data SI. BCK and LRCK master/slave mode switching input. Master mode when Low. Test input. Normally inputs Low. (VSS) Digital GND. (VSS) Test input. Normally inputs Low. (VSS) Digital power supply. (VDD) Test input. Normally inputs Low. (VSS) Digital GND. (VSS) Test input. Normally inputs Low. (VSS) Digital GND. (VSS) Test input. Normally inputs Low. (VSS) Digital power supply. (VDD) Test input. Normally inputs Low. (VSS) System reset input. Reset when Low. Test input. Normally inputs High. (VDD) Digital GND. (VSS) R-ch AD converter GND. (AVSS) R-ch AD converter analog input.

Pin No. Symbol I/O Description

– 5 –

CXD2728Q

DC Characteristics

(VDD0 to 2 = 3.0 to 3.6V, AVD1 to 6 = AVDX = 3.1 to 3.5V, AVS1 to 6 = AVSX = VSS0 to 5 = 0V, Ta = –20 to +75°C)

Item

Symbol

Conditions Min. Max. Unit Applicable pinsTyp.

V V V V V V V V V V V

V µA µA µA

Ω

∗1, ∗2, ∗6, ∗7 ∗1, ∗2, ∗6, ∗7 ∗5 ∗5 ∗3 ∗3 ∗4 ∗8, ∗9, ∗13 ∗8, ∗9, ∗13 ∗11 ∗11 ∗10 ∗1, ∗7 ∗2, ∗3, ∗5, ∗6 ∗9, ∗10

Resistance between ∗7and

∗11

High level Low level High level Low level High level Low level

High level Low level High level Low level Low level

Input voltage (1)

Input voltage (2)

Input voltage (3)

Input voltage (4) Output voltage

(1) Output voltage

(2) Output voltage (3)

Input leak current (1) Input leak current (2) Output leak current Feedback resistance

VIH VIL VIH VIL VIH VIL VIN VOH VOL VOH VOL VOL II II IOZ RFB

CMOS input

Schmitt input

LVTTL input

Analog input IOH = –4.0mA IOL = 4.0mA IOH = –12.0mA IOL = 12.0mA IOL = 4.0mA VIH = VDD, VSS VIH = VDD, VSS VIH = VDD, VSS

0.7VDD

0.8VDD

2.0

VSS

VDD – 0.4

VDD/2

–10 –40 –40

250k 1M

0.3VDD

0.2VDD

0.8

VDD

0.4

VDD/2

0.4 10 40 40

2.5M

∗1

TST0 to TST4, XMST

∗2

XS24, SI

∗3

SCK, XLAT, RVDT

∗4

LIN, RIN

∗5

XRST

∗6

During input to bidirectional pins BCK, LRCK

∗7

XTLI

∗8

During output from bidirectional pins BCK, LRCK

∗9

BFOT

∗10

REDY

∗11

XTLO

∗12

LREF, RREF

∗13

AO1P, AO1N, AO2P, AO2N, AO3P, AO3N, AO4P, AO4N

– 6 –

CXD2728Q

AC Characteristics

(VDD0 to 2 = 3.0 to 3.6V, AVD1 to 6 = AVDX = 3.1 to 3.5V, AVS1 to 6 = AVDX = VSS0 to 5 = 0V, Ta = –20 to +75°C)

Input Timing from Power-on to Input Pin

· · · · ·

VDD

XTLI

XRST

Input pins

0.7V

0.2VDD

1/fs or more

Determined by the crystal and other external circuit conditions

Stable (clock applied correctly)

2.0V

0.8V

0.95VDD

First input

BCK

LRCK

HLR tSLR

0.7VDD

0.2VDD

0.7VDD

0.2VDD

tSSI tHSI

0.7VDD

0.2VDD

BCK

LRCK

DLR

Serial Audio Interface Timing [Slave mode]

[Master mode]

Item SI setup time SI hold time LRCK setup time LRCK hold time LRCK delay time

Symbol

tSSI tHSI

tSLR tHLR tDLR

Conditions Slave mode Slave mode Slave mode Slave mode Master mode, CL = 120pF

Min.

20 40 20 40

Max.

Unit

ns ns ns ns ns

– 7 –

CXD2728Q

Microcomputer Interface Timing

Transfer timing for address section, transfer mode section and data section LSB

Transfer timing from data section MSB to address section and transfer mode section

Notes) 1. t is the cycle of 2/3 the clock frequency applied to the XTLI pin. (512fs)

2. The REDY pin is the value for CL = 60pF.

Item RVDT data setup time relative to SCK rise RVDT data hold time from SCK rise SCK Low level width SCK High level width XLAT Low level width XLAT High level width SCK rise preceding time relative to XLAT rise SCK rise wait time relative to XLAT rise Delay time to REDY fall relative to SCK rise REDY fall preceding time relative to SCK rise REDY rise preceding time relative to XLAT rise REDY rise preceding time relative to SCK fall XLAT fall wait time relative to SCK rise XLAT fall delay time relative to REDY fall SCK rise wait time for next transfer

Symbol

tDS tDH

tSWL

tSWH

tLWL

tLWH

tSLP tLSD tSBD tBSP tRLP

tRSDP

tSLD tLDR

tSS

Min.

20 1t + 20 1t + 20 1t + 20 1t + 20 1t + 20

20 3t + 20

20 2t + 40

Max.

4t + 50

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

RVDT

SCK

SWL tSWH tDS tDH

Address LSB Mode MSB

0.8V

2.0V

0.8V

2.0V

tSLP tLSD

tLWL

0.8V

2.0V

XLAT

REDY

Data LSB Data MSB

RVDT

SCK

XLAT

REDY

Mode MSB

0.8V

2.0V

Address LSBData MSB

tSS

tLDR

tSBD

tSLD

tBSP

0.8V

2.0V

tRLP

0.8V

2.0V

– 8 –

CXD2728Q

Analog Characteristics

(AVD0 to 6 = VDD0 to 2 = AVDX = 3.3V, AVS0 to 6 = VSS0 to 5 = AVSX = 0V, fs = 44.1kHz, Ta = 25°C)

When Pro Logic mode is on, the input signal level while measuring the center (C) and surround (S) channels should be –3dB smaller than the input level while measuring the left (L) and right (R) channels. At this time, for the C channel, the signal is input in-phase, and for the S channel, the signal is input at reversed phase to each L and R channel. The input level is the same for all measurement items when Pro Logic mode is off.

1. ADC + DAC Connection Total Characteristics

These are the total characteristics for the ADC and DAC. Use the analog I/O circuits in the Application Circuit for the measurement circuit.

1-1. When Pro Logic Mode is on

Unless otherwise specified, the measurement conditions are as given below.

• VIN (L, R measurement) = 300mVrms (0dB), VIN (C, S measurement) = 212mVrms (–3dB)

• FIN = 1kHz

• Sampling frequency = 44.1kHz

• Measured bands = 10Hz to 20kHz

∗1

When VIN = 200mVrms (= –3.52dB = –20dBFS), the S/N ratio is 3.52dB smaller than the values noted in the table above.

∗2

VIN (L, R) = 2.0Vrms, VIN (C, S) = 1.414Vrms

∗3

VIN (L, R) = 300mVrms, VIN (C, S) = 212mVrms

∗4

VIN (L, R) = 200mVrms, VIN (C, S) = 141mVrms

∗5

When the L and R channel gain deviation is 0.1dB or less in the prefilter output.

∗6

Including amplification by the external amplifier (L/Rch: 11.35dB, C/Sch: 14.42dB)

Channels

L, R

C, S

L, R

C, S

L, R

C, S

L, R

C, S

L, R

C, S

L, R

C, S

L, R

C, S

(all) (all)

L, R

C S

Min.

65.5

25 25

Typ.

72 70 57 52

0.006

0.03

0.045

0.23

0.32

16.5 53 45

300

±0.2

17.2

43.1 24 –9 30

Max.

1.00

Unit

Item

S/N ratio

∗1

(THD + N)/S

Head room

Matrix rejection

∗5

Output level Level difference between channels

Current consumption

Power supply fluctuation elimination ratio

∗6

Measurement conditions

CCIR/ARM filter

Measured bands: 70Hz to 300kHz

16.5dB

∗2

0dB

∗3

–3.52dB

∗4

Measured bands: 70Hz to 300kHz

(THD + N)/S = 1%

Analog system (including oscillator circuit)

Digital system

100mVrms, 100Hz sine wave

– 9 –

CXD2728Q

1-1. When Pro Logic Mode is off

Unless otherwise specified, the measurement conditions are as given below.

• VIN (L, R, C, S) = 2Vrms (0dB), 1kHz

• Sampling frequency = 44.1kHz

• Measured bands = 10Hz to 20kHz

Channels

(all) (all) (all)

(all) (all)

Min. Typ.

0.006 90

506

2.00 –6

Max. Unit

mVrms

Vrms

Item S/N ratio (THD + N)/S

∗1

Dynamic range

∗2

ADC maximum input level

∗3

Output level

∗4

Power supply fluctuation elimination ratio

∗5

Measurement conditions "A" weighting filter 0dB "A" weighting filter

100mVrms, 100Hz sine wave

∗1

See Graph 1: ADC Characteristics.

∗2

S/(THD + N) during –60dB input

∗3

The ADC maximum input level depends on the supply voltage (AVDn), so when the supply voltage (AVDn) contains deviation, calculate the maximum input level from the formula below and adjust the level so that the waveform is not clipped at the minimum voltage.

Maximum input level [Vrms] = 0.506 [Vrms] ×

∗4

Like the ADC, the DAC conversion gain also varies according to the supply voltage (AVDn). However, the DAC has the reverse characteristics of the ADC, so the total gain between the ADC and DAC is constant.

∗5

Including amplification by the external amplifier (L/Rch: 11.35dB, C/Sch: 14.42dB)

Minimum supply voltage [V]

3.3 [V]

0.001

GEN VOLT [Vrms]

THD + N CH1 [%]

0.002

0.005

0.010

0.020

0.050

0.100

0.200

0.500

3m 5m 10m 20m 50m 0.1 0.2 0.5 1 2

Graph 1. ADC Characteristics

– 10 –

CXD2728Q

2. DAC Characteristics

Use the digital input and analog output circuits in the Application Circuit for the measurement circuit.

2-1. When Pro Logic mode is on

Unless otherwise specified, the measurement conditions are as given below.

• Input data = 16.5dBFS (= 0dB), 1kHz, 16 bits

• Sampling frequency = 44.1kHz

• Measured bands = 10Hz to 20kHz

Channels

L, R

S L, R C, S L, R

S L, R

(all)

L, R

(all)

Min. Typ.

76 74 73 57 52

0.017

0.022

0.024

0.23

0.32

0.33

–16.5

300

51 70 56

±0.2

Max. Unit

dBFS

mVrms

Item

S/N ratio

(THD + N)/S

Dolby level Output level

∗1

Matrix rejection

Level difference between channels

Measurement conditions

CCIR/ARM filter

Measured bands: 70Hz to 300kHz

∗1

The output level depends on the supply voltage (AVDn) as shown in the formula below.

Output level [Vrms] = 300 [mVrms] ×

AVDn [V]

3.3 [V]

– 11 –

CXD2728Q

2-2. When Pro Logic mode is off

Unless otherwise specified, the measurement conditions are as given below.

• Input data = 0dBFS (= 0dB), 1kHz, 16 bits

• Sampling frequency = 44.1kHz

• Measured bands = 10Hz to 20kHz

Channels

L, R

S L, R

C, S L, R

S (all)

Min. Typ.

98 97 95

0.005

0.003 97 96 94

2.01

Max. Unit

Vrms

Item

S/N ratio

(THD + N)/S

∗1

Dynamic range

∗2

Output level

∗3

Measurement conditions

"A" weighting filter

∗1

See Graphs 2 and 3.

∗2

S/(THD + N) during –60dB input

∗3

The output level depends on the supply voltage (AVDn) as shown in the formula below.

Output level [Vrms] = 2.01 [Vrms] ×

AVDn [V]

3.3 [V]

–60 –50 –40 –30 –20 –10 0

0.001

0.002

GEN VOLT [dBFS]

THD + N CH1 [%]

0.005

0.010

0.020

0.050

0.100

0.200

0.500

–60 –50 –40 –30 –20 –10 0

0.001

0.002

GEN VOLT [dBFS]

THD + N CH1 [%]

0.005

0.010

0.020

0.050

0.100

0.200

0.500

Graph 2. DAC Characteristics (L, Rch) Graph 3. DAC Characteristics (C, Sch)

– 12 –

CXD2728Q

Description of Functions

1. Master/Slave Modes

[Relevant pins] XMST, LRCK, BCK

When using the CXD2728Q alone without digital input, set the CXD2728Q to master mode. When using digital input, the CXD2728Q may be set to either master mode or slave mode. The clock applied to LRCK and BCK in slave mode must be synchronized to either the crystal oscillator clock of the XTLI and XTLO pins or the external clock input from the XTLI pin.

Table 1-1. LRCK, BCK Mode Setting

XMST

Mode

Slave mode

Master mode

LRCK, BCK I/O

Input

Output

SQC05

0 0 1 1

SQC04

0 1 0 1

BFOT

384fs 256fs 512fs 768fs

2. Master Clock System

[Relevant pins] XTLI, XTLO, BFOT

768fs (fs = 32 to 48kHz) is assumed for the master clock system, and the connection is as shown below. BFOT outputs the clock obtained by frequency dividing the master clock. The frequency division ratio can be changed by the setup register (SQC04, SQC05). (See "6. Setup Register".)

(1) Master

(2) Slave

Frequency divider

Setup Register

512fs

XTLI

XTLO

768fs

BFOT 256fs/384fs/512fs/768fs

512fs

XTLI

XTLO

768fs

OPEN

Frequency divider

Fig. 2-1.

Note) Oscillation circuits may differ according to peripheral circuit and substrate. Consult with crystal oscillator

manufacturers about the selecting oscillation circuits.

– 13 –

CXD2728Q

3. Reset Circuit

[Relevant pins] XRST, XTLI, XTLO

This LSI must be reset after the power is turned on. Reset is done by setting the XRST pin Low for 1/fs or more after the supply voltage satisfies the recommended operating condition, and the crystal oscillator clock of the XTLI and XTLO pins or the external clock input from the XTLI pin is correctly applied. (See "AC Characteristics".)

4. Serial Audio Interface (SIF)

[Relevant pins] SI, BCK, LRCK, XS24, XMST

Serial data is used for the external communication of the digital audio data. The CXD2728Q has only one input system, and 2 channels of data are input for each sampling cycle. Either the 32-bit clock mode or the 24-bit clock mode can be selected. In master mode, the mode is fixed to the 32-bit clock mode.

(1) Pin Configuration (The pins shown in the table below are assigned to the SIF.)

Serial input; taken with synchronized to BCK. BCK I/O; either 32-bit clock mode (64fs) or 24-bit clock mode (48fs). BCK output supports

32-bit clock mode only. LRCK I/O (1fs). SIO slot number (24/32) selection input. Low: 24-bit slot; High: 32-bit slot.

Valid only in slave mode. Set High in master mode. Do not switch between High and Low during DSP operation.

BCK, LRCK master mode/slave mode switching input. Low: master mode; High: slave mode.

Symbol

SI BCK LRCK

XS24

XMST

I/O

Function

I I/O I/O

"0": normal, "1": IIS "0": Lch "H", "1": Lch "L"

"0": edge ↓, "1" : edge ↑

Setup register SQC15 SQC14

SQC13

Function

Contents LRCK format LRCK polarity selection BCK polarity selection relative to LRCK edge.

Valid only in slave mode. Fix to "0" in master mode.

Table 4-1. Pin Configuration

Table 4-2. LRCK/BCK Mode Setting

(2) Operation Modes

The LRCK/BCK mode can be selected by the setup register settings as follows. (See "6. Setup Register".)

LRCK/BCK Mode Setting

– 14 –

CXD2728Q

Table 4-3. Setup Register Settings

(3) SIF Format

The serial audio interface has only one input system, and except for the slot number, the following formats can be set by setting the setup register. The serial audio interface can also support IIS format to enable connection to Philips and other company's devices. The timing charts for each data format are given on the following page.

SQC12

0 0 1 1

SQC11

0 1 0 1

Data arrangement/Frontward or rearward truncation/Data word length

MSB first/Frontward truncation/24 bits

MSB first/Rearward truncation/16 bits MSB first/Rearward truncation/18 bits MSB first/Rearward truncation/20 bits

∗

All formats support either the 24- or 32-bit slot in slave mode.

– 15 –

CXD2728Q

23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 0017 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 0017 16

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 0017 1619 18 19 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 0017 1618

LRCK

BCK

23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

• MSB first 24 bits frontward truncation (SQC12, 11 = 0, 0)

• MSB first 16 bits rearward truncation (SQC12, 11 = 0, 1)

• MSB first 18 bits rearward truncation (SQC12, 11 = 1, 0)

• MSB first 20 bits rearward truncation (SQC12, 11 = 1, 1)

Lch

Rch

LSB MSBInvalid LSB Invalid

MSBInvalid LSB MSBInvalid LSB

LSB MSBInvalid LSB

MSB

Invalid

MSBMSB

23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

LRCK

BCK

LSB MSB LSB

MSB LSB MSBInvalid LSB

LSB MSBInvalid LSB

MSB

Invalid

Lch

Rch

MSB

• MSB first 24 bits (SQC12, 11 = 0, 0)

• MSB first 16 bits rearward truncation (SQC12, 11 = 0, 1)

• MSB first 18 bits rearward truncation (SQC12, 11 = 1, 0)

• MSB first 20 bits rearward truncation (SQC12, 11 = 1, 1)

Digital Audio Data Input Timing (with polarities: SQC15 = 0, SQC14 = 0, SQC13 = 0)

32-bit slot

24-bit slot

– 16 –

CXD2728Q

5. Microcomputer Interface

[Relevant pins] RVDT, SCK, XLAT, REDY

The CXD2728Q performs the serial audio interface format setting and the coefficient settings such as volume and filter by serial data from the microcomputer.

(1) Pin Configuration

The four external pins indicated in the table below are assigned to the microcomputer interface.

Serial data input from microcomputer. Shift clock for serial data. Input data from RVDT is taken according to the SCK rise. Interprets the 8 bits of RVDT before this signal rises as transfer mode data, and the

bits before that as address data. Transfer prohibited while at Low level. Transfer enabled at High. This pin is an open

drain, and must be pulled up externally.

Symbol RVDT SCK

XLAT

REDY

I/O

Function I I

Table 5-1. Microcomputer Interface External Pins

(2) Description of Communication Formats

The internal data transfer timing from the microcomputer interface to the coefficient RAM and setup register is called the SV cycle, and is generated once per 1 LRCK. The SV cycle is generated immediately preceding the signal processing program, so it has absolutely no effect on signal processing, and there is no risk of the sound being cut.

Address section + Mode section + Data section

act as one package of data to transfer data from the microcomputer to the CXD2728Q.

A0 A7 M0 M7 D0 D15

Address section (8 bits) Mode section (8 bits)

RVDT

SCK

XLAT

REDY

Data section (16 bits)

Fig. 5-1. Example of Communication

– 17 –

CXD2728Q

(3) Data Structure

The data structure is classified into three types, as shown in the table below. All data communication is done with LSB first.

Coefficient RAM and setup register are both 16 bits

Symbol A0 to A7 M0 to M7 D0 to D15/SQ00 to SQ15

Bit length

Remarks 8 8

Contents

Address section

Transfer mode section

Data section

Table 5-2. Data Structure

(3)-1. Transfer Mode Section

The transfer mode section is 8 bits and has the following functions.

Normally fixed to "0" SU1 SU0

0 0 Field A 0 1 Field B (Not used) 1 0 Field C 1 1 Field D

VS1 VS0

0 0 Setup register 1 0 Coefficient RAM

Normally fixed to "0"

Bit

M5 M4

M3 M2 M1 M0

Symbol

Function

SU1

SU0 VS1

VS0

Reserve

Setup Reg. type

Data type

Reserve

Table 5-3. Transfer Mode Section

(3)-2. Address Section

The coefficient RAM has a 256-word structure, so the address section is 8 bits. The setup register has a 4word structure and the field (address) is specified by the mode section, so the address section data may be optional.

(3)-3. Data Section

The coefficient RAM and setup register both have a 16-bit structure, so 16 SCK are required.

– 18 –

CXD2728Q

(4) Details of Communication Methods

The definitions of signal timing required for control from the microcomputer are given below.

(4)-1. Signal Timing

First, address section data and mode section data are sent from the microcomputer, synchronized to SCK, to the RVDT pin. The address section data is 8 bits for both the coefficient RAM and setup register, and the setup register has a length of one word, so optional data can be transferred. Address section data is sent with LSB first. Mode section data is fixed at 8 bits regardless of the transfer contents.

The phase relationship between SCK and RV data (data applied to the RVDT pin) has the following restrictions:

• RV data must be established before SCK rises (tDS ≥ 20ns).

• RV data must be held for 1t + 20ns or more after SCK rises (tDH).

SCK itself has the following restrictions:

• SCK Low level must be 1t + 20ns or more (tSWL).

• SCK High level must be 1t + 20ns or more (tSWH).

After the SCK rise which corresponds to the mode section final data, XLAT rises (tSLP ≥ 20ns). The XLAT Low level width must be maintained at 1t + 20ns or more (tLWL). The fall timing is restricted in that even if REDY falls due to SCK during the preceding transfer, 3t + 20ns or more (tSLD) is required from the SCK rise which corresponds to the data section final data. Further, if preceding transfers have been performed and REDY = Low, XLAT must rise after REDY = High.

A0 A7 M0 M7 SQ00 SQ15RVDT

SCK

XLAT

REDY

A0 M7

tDHtDS

tSWHtSWL

tSLD or tLWH tLWL

tRLPtLDR

tLSDtSLP tBSP tSLP

tLDR tRLP

tSS

tSLD

tSBD

D0/SQ00 D15/SQ15

Fig. 5-2. Write Timing

∗

t is the cycle of 2/3 the clock frequency applied to the XTLI pin. (512fs)

– 19 –

CXD2728Q

Data section write begins after XLAT rises, and here also transfer must be performed with LSB first, with tDS and tDH restrictions. In addition, after XLAT rises at the starting point for sending the data section, wait for 3t + 20ns or more for the first SCK rise (tLSD).

When 16 bits of this write is repeated, REDY goes Low within 4t + 50ns, and the microcomputer is informed of waiting status for the SV cycle, which is the dedicated data rewrite cycle, by the microcomputer interface (tSBD). When REDY goes High again, the corresponding data is written.

The next communication can be restarted by using the REDY signal as follows.

• When REDY = Low, the SCK for the next transfer can rise (tBSP ≥ 20ns).

• In the same way, when REDY = Low, the XLAT for the next transfer can fall (tLDR ≥ 20ns).

REDY will fall due to this communication, but it is prohibited for XLAT to rise for the next transfer before REDY rises. Make sure that the next XLAT rises after REDY rises (tRLP ≥ 20ns).

In order to restart the next transfer without using the REDY signal, the following conditions must be observed:

• There should be 2t + 40ns or more left between the SCK rise for the final data section and the SCK rise for the next transfer (tSS).

• In the same way, the XLAT for the next transfer can fall after waiting for 3t + 20ns or more after the final data section SCK rise (tSLD).

The tSS and tSLD here are shorter times than tSBD ≤ 4t + 50ns, so these are rather loose restrictions. However, even in this case the XLAT rise for the next transfer must come after REDY rises (tRLP ≥ 20ns).

Further, the restriction for the XLAT fall at the starting point of this transfer from tSLD can be:

tSLD ≥ 3t + 20ns

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