Sony CXD2598Q Datasheet

CXD2598Q

CD Digital Signal Processor with Built-in Digital Servo and DAC

Description

The CXD2598Q is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, 1-bit DAC and analog low-pass filter on a single chip.

Features

• All digital signal processing during playback is

performed with a single chip

• Highly integrated mounting possible due to a built-

in RAM Digital Signal Processor (DSP) Block

• Playback mode supporting CAV (Constant Angular

Velocity)

• Frame jitter free

• 0.5× to 4× continuous playback possible

• Allows relative rotational velocity readout

• Wide capture range playback mode

• Spindle rotational velocity following method

• Supports normal-speed to 4× speed playback

• Supports variable pitch playback

• The bit clock, which strobes the EFM signal, is

generated by the digital PLL.

• EFM data demodulation

• Enhanced EFM frame sync signal protection

• Refined super strategy-based powerful error correction

C1: double correction, C2: quadruple correction

Supported during 4× speed playback

• Noise reduction during track jumps

• Auto zero-cross mute

• Subcode demodulation and Sub-Q data error detection

• Digital spindle servo

• 16-bit traverse counter

• Asymmetry correction circuit

• CPU interface on serial bus

• Error correction monitor signal, etc. output from a

new CPU interface

• Servo auto sequencer

• Fine search performs track jumps with high accuracy

• Digital audio interface outputs

• Digital level meter, peak meter

• Bilingual compatible

• VCO control mode

• CD TEXT data demodulation

Digital Servo (DSSP) Block

• Microcomputer software-based flexible servo control

• Offset cancel function for servo error signal

• Auto gain control function for servo loop

• E:F balance, focus bias adjustment functions

• Surf jump function supporting micro two-axis

• Tracking filter: 6 stages

Focus filter: 5 stages Digital Filter, DAC and Analog Low-Pass Filter Blocks

• DBB (digital bass boost) function

• Digital de-emphasis

• Digital attenuation

• 8fs oversampling digital filter

• Adoption of tertiary ∆∑ noise shaper

• S/N: 100dB or more (master clock: 384Fs, typ.) Logical value: 109dB

• THD + N: 0.007% or less (master clock: 384Fs, typ.)

• Rejection band attenuation: –60dB or less

• Double-speed playback supported

Applications

CD players

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings

• Supply voltage VDD –0.3 to +7.0 V

• Input voltage VI –0.3 to +7.0 V

(Vss – 0.3V to VDD + 0.3V)

• Output voltage VO –0.3 to +7.0 V

(Vss – 0.3V to VDD + 0.3V)

• Storage temperature Tstg –40 to +125 °C

• Supply voltage difference

VSS – AVSS –0.3 to +0.3 V VDD – AVDD –0.3 to +0.3 V

Note) AVDD includes XVDD and AVSS includes XVSS. Recommended Operating Conditions

• Supply voltage VDD 2.7 to 5.5 V

• Operating temperature Topr –20 to +75 °C

Note) The VDD for the CXD2598Q varies according

to the playback speed selection.

I/O Pin Capacitance

• Input capacitance CI 11 (Max.) pF

• Output capacitance CO 11 (Max.) pF

• I/O capacitance CI/O 11 (Max.) pF

Note) Measurement conditions VDD = VI = 0V

fM = 1MHz

– 1 –

E97Y14-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

100 pin QFP (Plastic)

Playback speed

CD-DSP block

DAC block

4×

4.75 to 5.25

2×

3.0 to 5.5 4.5 to 5.5

1×

2.7 to 5.5 2.7 to 5.5

VDD[V]

– 2 –

CXD2598Q

Block Diagram

PWM PWM

AOUT1

AIN1 LOUT1 AOUT2

AIN2 LOUT2

3rd-Order

Noise Shaper

Over Sampling

Digital Filter

Serial-In Interface

LMUT

RMUT

XTAO

XTAI

Timing

Logic

XRST

TEST

TES1

D/A

Interface

DOUT

EFM

demodulator

Error

Corrector

32K

RAM

Digital

OUT

Sub Code Processor

Clock

Generator

Asymmetry

Corrector

Digital

PLL

CPU

Interface

Servo

Auto

Sequencer

Signal Processor Block

DAC Block

PCMDI

BCK

PCMD

LRCK

C2PO

WFCK

EMPH

GFS

XUGF

XTSL

RFAC

ASYI

ASYO

BIAS

FSTIO

FILO

FILI

PCO

CLTV

MDP

PWMI

SENS DATA

XLAT

CLOK

SCOR

SBSO EXCK

Servo Block

SERVO

Interface

SCLK COUT SSTP ATSK

MIRR DFCT

FOK

MIRR DFCT FOK

SERVO DSP

FOCUS SERVO

TRACKING

SERVO

SLED SERVO

PWM GENERATOR

FOCUS PWM GENERATOR

TRACKING PWM

GENERATOR

SLED PWM

GENERATOR

FFDR FRDR TFDR TRDR SFDR SRDR

RFDC

CE

TE

SE

FE

VC

IGEN

OPAmp

Analog SW

A/D

Converter

ADIO

BCKI

SYSM

LRCKI

EMPHI

WDCK

VPCO

V16M

VCTL

XPCK

C4M

SQSO

SQCK

LOCK

Digital

CLV

ASYE

SCSY

XOLT

SOCK

SOUT

MD2

– 3 –

CXD2598Q

Pin Configuration

V

DD

V

SS

SOUT

SOCK

XOLT

SQSO

SQCK

SCSY

SBSO

EXCK

XRST

SYSM

DATA

XLAT

CLOK

SENS

SCLK

ATSK

WFCK

XUGF

XPCK

GFS

C2PO

SCOR

C4M

WDCK

COUT

MIRR

V

SS

V

DD

PCMDI

PCMD

LRCKI

LRCK

VDDASYE

DOUT

MD2

V

SS

VPCO

V16M

VCTL

BIAS

AV

DD

3

PCO

FILI

FILO

CLTV

AV

SS

3

RFAC

ASYI

ASYO

AV

DD

0

IGEN

AV

SS

0

ADIO

RFDC

CE

TE

SE

FE VC XTSL TES1 TEST VSS VDD FRDR FFDR TRDR TFDR SRDR SFDR FSTIO SSTP MDP LOCK PWMI FOK DFCT

40

39

38 37 36 35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70

69

68

67

63

64

65

66

61

62

71

72

73

74

75

76

77

78

79

80

2

3

4

5

6

7

8

9

10

11

12

13

14 15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

1

81 82 83 84

88

87

86

85

89 90

100

99

98

97

96

95

94

91 92

93

BCK

BCKI

EMPH

EMPHI

XV

DD

XTAI

XTAO

XV

SS

AVDD1

AOUT1

AIN1

LOUT1

AVSS1 AVSS2

LOUT2

AIN2

AOUT2

AVDD2

RMUT

LMUT

– 4 –

CXD2598Q

Pin Description

No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

25 26

27 28 29 30 31 32 33

34

— —

O O O O

I I

O

I I I I I I

O

I

I/O

O O O O O O

O

O I/O I/O

—

— I/O I/O

I

I/O

—

— 1, 0 1, 0 1, 0 1, 0

1, 0

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

1, 0 1, 0

—

— 1, 0 1, 0

1, 0

Digital power supply. Digital GND. Servo block internal serial data output. Servo block internal serial data readout clock output. Servo block internal serial data latch output. Sub-Q 80-bit, PCM peak and level data outputs. CD TEXT data output. SQSO readout clock input. GRSCOR resynchronization input. Sub P to W serial output. SBSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS output to CPU. SENS serial data readout clock input. Anti-shock input/output. WFCK output. XUGF output. MNT0 or RFCK is output by switching with the command. XPCK output. MNT1 is output by switching with the command. GFS output. MNT2 or XROF is output by switching with the command. C2PO output. MNT3 or GTOP is output by switching with the command. Outputs a high signal when either subcode sync S0 or S1 is detected.

4.2336MHz output. In CAV-W mode and variable pitch mode, the 1/4 frequency division of V16M is output.

Word clock output f = 2Fs. GRSCOR is output by switching with the command. Track count signal input/output. Mirror signal input/output. Digital GND. Digital power supply. Defect signal input/output. Focus OK signal input/output. Spindle motor external control input. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS

is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1.

VDD VSS SOUT SOCK XOLT SQSO SQCK SCSY SBSO EXCK XRST SYSM DATA XLAT CLOK SENS SCLK ATSK WFCK XUGF XPCK GFS C2PO SCOR

C4M WDCK

COUT MIRR VSS VDD DFCT FOK PWMI

LOCK

Symbol I/O Description

– 5 –

CXD2598Q

35 36 37 38 39 40 41 42 43 44 45 46 47

48 49

50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

O

I

I/O

O O O O O

O — —

I I

I I I I I

O —

I

—

O

I I

—

I

O

I

O —

I I

1, Z, 0

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

— —

Analog

—

1, 0

—

Analog

1, Z, 0

—

Spindle motor servo control output. Disc innermost track detection signal input. Input/output of 2/3 frequency division for the XTAI pin. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Digital power supply. Digital GND. Test pin. Normally, GND. Test pin. Normally, GND. Crystal selection input. Low when the crystal is 16.9344MHz; high when the

crystal is 33.8688MHz. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center servo analog input. RF signal input. Test pin. Do not connect anything. Analog GND. Operational amplifier constant current input. Analog power supply. EFM full-swing output (low = VSS, high = VDD). Asymmetry comparator voltage input. EFM signal input. Analog GND. Multiplier VCO1 control voltage input. Master PLL filter output (slave = digital PLL). Master PLL filter input. Master PLL charge pump output. Analog power supply. Asymmetry circuit constant current input. Wide-band EFM PLL VCO2 control voltage input.

MDP SSTP FSTIO SFDR SRDR TFDR TRDR FFDR FRDR VDD VSS TEST TES1

XTSL VC

FE SE TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO ASYI RFAC AVSS3 CLTV FILO FILI PCO AVDD3 BIAS VCTL

Pin No.

Symbol I/O Description

– 6 –

CXD2598Q

70 71

72 73 74 75 76 77 78 79 80 81 82

83

84 85

86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

I/O

O

—

I

O

I

—

O

I

O

I

O

I

O

I

O

—

O

I

O

— —

O

I

O

—

O O

1, 0

1, Z, 0

—

1, 0

—

1, 0

—

— —

— 1, 0 1, 0

Wide-band EFM PLL VCO2 oscillation output. Wide-band EFM PLL clock input by switching with the command.

Wide-band EFM PLL charge pump output. Digital GND. Digital Out on/off control (low = off, high = on). Digital Out output. Asymmetry circuit on/off (low = off, high = on). Digital power supply. D/A interface. LR clock output f = Fs. D/A interface. LR clock input. D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Serial data input. (two's complement, MSB first) D/A interface. Bit clock output. D/A interface. Bit clock input. Outputs a high signal when the playback disc has emphasis, and a low

signal when there is no emphasis. Inputs a high signal when emphasis is on, and a low signal when emphasis

is off. Master clock power supply. Crystal oscillation circuit input. Master clock is externally input from this pin. Crystal oscillation circuit output. Master clock GND. Analog power supply. Left channel analog output. Left channel operational amplifier input. Left channel LINE output. Analog GND. Analog GND. Right channel LINE output. Right channel operational amplifier input. Right channel analog output. Analog power supply. Right channel zero detection flag. Left channel zero detection flag.

V16M VPCO

VSS MD2 DOUT ASYE VDD LRCK LRCKI PCMD PCMDI BCK BCKI

EMPH

EMPHI XVDD

XTAI XTAO XVSS AVDD1 AOUT1 AIN1 LOUT1 AVSS1 AVSS2 LOUT2 AIN2 AOUT2 AVDD2 RMUT LMUT

Pin No.

Symbol I/O Description

– 7 –

CXD2598Q

Notes) • PCMD is a MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window opens.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before

sync protection.

• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion protection timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.

• C2PO represents the data error status.

• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.

Monitor Pin Output Combinations

Command bit

Output data

MTSL1

MTSL0

XUGF

XPCK

GFS

C2PO

MNT0

MNT1

MNT2

MNT3

RFCK

XPCK

XROF

GTOP

0 0 1

0 1 0

– 8 –

CXD2598Q

Electrical Characteristics

1. DC Characteristics (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item

Input voltage (1)

Input voltage (2)

Input voltage (3)

Input voltage (4) Output voltage

(1) Output voltage

(2) Output voltage

(3) Output voltage

(4)

Input leak current (1)

Input leak current (2) Input leak current (3)

Input leak current (4)

∗1, ∗11

∗2, ∗12

∗3

∗4, ∗9, ∗10

∗5

∗6

∗7

∗1, ∗2

∗3, ∗11, ∗12 ∗9

∗10

∗8

Schmitt input

Analog input IOH = –2mA IOL = 4mA IOH = –4mA IOL = 8mA IOH = –6mA IOL = 4mA IOH = –0.28mA IOL = 0.36mA VIN = VSS

or VDD VIN = VSS

or VDD VI = 1.5 to 3.5V VI = 0 to 5.0V

High level input voltage Low level input voltage High level input voltage Low level input voltage High level input voltage Low level input voltage Input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltage

VIH (1) VIL (1) VIH (2) VIL (2) VIH (3) VIL (3) VIN (4) VOH (1) VOL (1) VOH (2) VOL (2) VOH (3) VOL (3) VOH (4) VOL (4)

ILI (1)

ILI (2) ILI (3)

ILI (4)

0.7VDD

0.8VDD

Vss

VDD – 0.8

Vss

VDD – 0.8

Vss

VDD – 0.8

Vss

VDD – 0.5

Vss –10

–40 –20

–40

0.3VDD

0.2VDD

0.2VDD VDD VDD

0.4

VDD

0.4

VDD

0.4

VDD

0.4 10

40 20

600

V V V V V V V V V V V V V V V

µA

µA µA

µA

Conditions Min. Typ. Max. Unit

Applicable pins

∗1

SYSM, DATA, XLAT, PWMI, SSTP, XTSL, TEST, TES1, MD2, SCSY

∗2

SQCK, XRST, CLOK, ASYE

∗3

LRCKI, PCMDI, BCKI, EMPHI

∗4

ASYI, RFAC, CLTV, FILI, VCTL

∗5

SQSO, SBSO, SENS, ATSK, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK, COUT, MIRR, DFCT, FOK, LOCK, FSTIO, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, EMPH, RMUT, LMUT, SOUT, SOCK, XOLT

∗6

V16M

∗7

MDP, PCO, VPCO

∗8

FILO

∗9

VC, FE, SE, TE, CE

∗10

RFDC

∗11

EXCK, ATSK, COUT, MIRR, DFCT, FOK, LOCK, PWMI, V16M, FSTIO

∗12

SCLK

– 9 –

CXD2598Q

2. AC Characteristics

(1) XTAI pin

(a) When using self-excited oscillation

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

(b) When inputting pulses to XTAI pin

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

(c) When inputting sine waves to XTAI pin via a capacitor

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

Oscillation frequency fMAX 7 34 MHz

Item Symbol Min. Typ. Max. Unit

High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time

tWHX

13

500

ns

tWLX

13 500

ns

tCX

26 1000

ns

VIHX

VDD – 1.0

V

VILX 0.8

V

tR, tF

10

ns

Item Symbol Min. Typ. Max. Unit

Input amplitude VI 2.0 VDD + 0.3 Vp-p

Item Symbol Min. Typ. Max. Unit

tR tF

tWHX

tWLX

tCX

VILX

VIHX × 0.1

V

IHX × 0.9

V

IHX

XTAI

V

DD/2

– 10 –

CXD2598Q

(2) CLOK, DATA, XLAT, SQCK and EXCK pins

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width COUT frequency (during input)

∗

COUT pulse width (during input)

∗

fCK

tWCK tSU tH tD tWL

fT

tWT

fT

tWT

750 300 300 300 750

750

7.5

0.65

65

MHz

ns ns ns ns ns

MHz

ns

kHz

µs

Item Symbol Min. Typ. Max. Unit

tWCK tWCK

1/fCK

tH

tSU

tWL

tD

1/fT

tWT tWT

tH

tSU

CLOK

DATA

XLAT

EXCK SQCK COUT

SBSO SQSO

∗

Only when $44 and $45 are executed.

– 11 –

CXD2598Q

(3) BCKI, LRCKI and PCMDI pins

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

BCK pulse width PCMDI setup time PCMDI hold time LRCK setup time

tW tSU tH tSU

ns ns ns ns

Item Symbol

Conditions

Typ. 94 18 18 18

Min.

Max. Unit

VDD/2 VDD/2

tW(BCKI) tW(BCKI)

tSU

(PCMDI)

t

H

(PCMDI)

tSU

(LRCKI)

BCKI

PCMDI

LRCKI

(4) SCLK pin

SCLK frequency SCLK pulse width Delay time

fSCLK

tSPW tDLS

31.3 15

16 MHz

ns µs

Item Symbol Min. Typ. Max. Unit

tSPWtDLS

1/fSCLK

MSB LSB· · ·

· · ·

XLAT

SCLK

Serial Read Out Data

(SENS)

– 12 –

CXD2598Q

(5) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency

fCOUT fMIRR fDFCTH

40 40

5

kHz kHz kHz

∗1 ∗2 ∗3

Item Symbol Min. Typ. Max. Max.

Conditions

∗1

When using a high-speed traverse TZC.

∗2

When the RF signal continuously satisfies the following conditions during the above traverse.

• A = 0.12VDD to 0.26VDD

• ≤ 25%

∗3

During complete RF signal omission. When settings related to DFCT signal generation are Typ.

A

B

A + B

– 13 –

CXD2598Q

1-bit DAC and LPF Block Analog Characteristics

Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)

Item

Total harmonic distortion

Signal-to-noise ratio

Symbol

THD

S/N

Conditions

1kHz, 0dB data

Crystal

1kHz, 0dB data (Using A-weighting filter)

384Fs 768Fs 384Fs 768Fs

96 96

0.0050

0.0045 100 100

0.0070

0.0065

Min.

Typ.

Max.

Unit

%

dB

Audio Analyzer

SHIBASOKU (AM51A)

100k

22µ

680p

12k

150p

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Audio Analyzer

CXD2598Q

Rch A

Lch B

DATA RF

TEST DISC

768Fs/384Fs

(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Output voltage Load resistance

VOUT RL

∗1 ∗1

Vrms

kΩ

Item Symbol

8

Min.

Max.

1.12

Typ.

Applicable pinsUnit

∗

Measurement is conducted for the above circuit diagrams with the sine wave output of 1kHz and 0dB.

Applicable pins

∗1

LOUT1, LOUT2

Block diagram of analog characteristics measurement

LPF external circuit diagram

Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.

– 14 –

CXD2598Q

Contents

§1. CPU Interface

§1-1. CPU Interface Timing ..........................................................................................................................15

§1-2. CPU Interface Command Table ..........................................................................................................15

§1-3. CPU Command Presets ......................................................................................................................26

§1-4. Description of SENS Signals...............................................................................................................32

§1-5. Description of Commands ...................................................................................................................34

§2. Subcode Interface

§2-1. P to W Subcode Readout....................................................................................................................62

§2-2. 80-bit Sub-Q Readout..........................................................................................................................62

§3. Description of Modes

§3-1. CLV-N Mode........................................................................................................................................69

§3-2. CLV-W Mode.......................................................................................................................................69

§3-3. CAV-W Mode.......................................................................................................................................69

§3-4. VCO-C mode.......................................................................................................................................70

§4. Description of Other Functions

§4-1. Channel Clock Recovery by Digital PLL Circuit...................................................................................73

§4-2. Frame Sync Protection........................................................................................................................75

§4-3. Error Correction...................................................................................................................................75

§4-4. DA Interface.........................................................................................................................................76

§4-5. Digital Out............................................................................................................................................78

§4-6. Servo Auto Sequence..........................................................................................................................82

§4-7. Digital CLV...........................................................................................................................................90

§4-8. CD-DSP Block Playback Speed..........................................................................................................91

§4-9. DAC Block Playback Speed ................................................................................................................91

§4-10. DAC Block Input Timing ....................................................................................................................92

§4-11. Description of DAC Block Functions..................................................................................................92

§4-12. LPF Block ..........................................................................................................................................97

§4-13. Asymmetry Correction.......................................................................................................................98

§4-14. CD TEXT Data Demodulation ...........................................................................................................99

§5. Description of Servo Signal Processing System Functions and Commands

§5-1. General Description of Servo Signal Processing System..................................................................101

§5-2. Digital Servo Block Master Clock (MCK)...........................................................................................102

§5-3. DC Offset Cancel [AVRG Measurement and Compensation] ...........................................................103

§5-4. E:F Balance Adjustment Function .....................................................................................................104

§5-5. FCS Bias Adjustment Function..........................................................................................................104

§5-6. AGCNTL Function .............................................................................................................................106

§5-7. FCS Servo and FCS Search .............................................................................................................108

§5-8. TRK and SLD Servo Control .............................................................................................................109

§5-9. MIRR and DFCT Signal Generation..................................................................................................110

§5-10. DFCT Countermeasure Circuit........................................................................................................111

§5-11. Anti-Shock Circuit............................................................................................................................111

§5-12. Brake Circuit....................................................................................................................................112

§5-13. COUT Signal ...................................................................................................................................113

§5-14. Serial Readout Circuit......................................................................................................................113

§5-15. Writing to Coefficient RAM ..............................................................................................................114

§5-16. PWM Output....................................................................................................................................114

§5-17. Servo Status Changes Produced by LOCK Signal ........................................................................115

§5-18. Description of Commands and Data Sets .......................................................................................115

§5-19. List of Servo Filter Coefficients........................................................................................................137

§5-20. Filter Composition............................................................................................................................139

§5-21. TRACKING and FOCUS Frequency Response ..............................................................................145

§6. Application Circuit...................................................................................................................................146

Explanation of abbreviations

AVRG: Average TRK: Tracking AGCNTL: Auto gain control SLD: Sled FCS: Focus DFCT: Defect

– 15 –

CXD2598Q

§1. CPU Interface

§1-1. CPU Interface Timing

• CPU interface

This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below.

• The internal registers are initialized by a reset when XRST = 0.

§1-2. CPU Interface Command Table

Total bit length for each register

Register

0 to 2

3

4 to 6

7 8 9 A

B C D E

8 bits

8 to 24 bits

16 bits 20 bits 32 bits 32 bits 28 bits 24 bits 28 bits 20 bits 20 bits

Total bit length

750ns or more

D18 D19 D20 D21 D22 D23

750ns or more

Valid

CLOK

DATA

XLAT

Registers

D0 D1

– 16 –

CXD2598Q

FOCUS SERVO ON

(FOCUS GAIN

NORMAL)

FOCUS SERVO ON

(FOCUS GAIN

DOWN)

FOCUS SERVO OFF,

0V OUT

FOCUS SERVO OFF,

FOCUS SEARCH

VOLTAGE OUT

FOCUS SEARCH

VOLTAGE DOWN

FOCUS SEACH

VOLTAGE UP

ANTI SHOCK ON

ANTI SHOCK OFF

BRAKE ON

BRAKE OFF

TRACKING GAIN

NORMAL

TRACKING GAIN UP

FILTER SELECT 1

TRACKING GAIN UP

FILTER SELECT 2

1

0

1

0

—

0

1

—

0

—

1

0

—

0

1

—

0

1

—

0

1

—

1

0

—

0

1

0 0 0 0

0 0 0 1

FOCUS

CONTROL

TRACKING

CONTROL

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Command Table ($0X to 1X)

—: Don’t care

– 17 –

CXD2598Q

TRACKING SERVO OFF

TRACKING SERVO ON

FORWARD TRACK JUMP

REVERSE TRACK JUMP

SLED SERVO OFF

SLED SERVO ON

FORWARD SLED MOVE

REVERSE SLED MOVE

SLED KICK LEVEL

(±1 × basic value) (Default)

SLED KICK LEVEL

(±2 × basic value)

SLED KICK LEVEL

(±3 × basic value)

SLED KICK LEVEL

(±4 × basic value)

0

1

—

0

1

0

1

0

1

—

0

1

0

1

—

0

1

—

0

1

0

1

—

2

3

0 0 1 0

0 0 1 1

TRACKING

MODE

SELECT

Register

Command

Address

D23 to D20

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

—: Don’t care

Command Table ($2X to 3X)

– 18 –

CXD2598Q

KRAM DATA (K00)

SLED INPUT GAIN

KRAM DATA (K01)

SLED LOW BOOST FILTER A-H

KRAM DATA (K02)

SLED LOW BOOST FILTER A-L

KRAM DATA (K03)

SLED LOW BOOST FILTER B-H

KRAM DATA (K04)

SLED LOW BOOST FILTER B-L

KRAM DATA (K05)

SLED OUTPUT GAIN

KRAM DATA (K06)

FOCUS INPUT GAIN

KRAM DATA (K07)

SLED AUTO GAIN

KRAM DATA (K08)

FOCUS HIGH CUT FILTER A

KRAM DATA (K09)

FOCUS HIGH CUT FILTER B

KRAM DATA (K0A)

FOCUS LOW BOOST FILTER A-H

KRAM DATA (K0B)

FOCUS LOW BOOST FILTER A-L

KRAM DATA (K0C)

FOCUS LOW BOOST FILTER B-H

KRAM DATA (K0D)

FOCUS LOW BOOST FILTER B-L

KRAM DATA (K0E)

FOCUS PHASE COMPENSATE FILTER A

KRAM DATA (K0F)

FOCUS DEFECT HOLD GAIN

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($340X)

– 19 –

CXD2598Q

KRAM DATA (K10)

FOCUS PHASE COMPENSATE FILTER B

KRAM DATA (K11)

FOCUS OUTPUT GAIN

KRAM DATA (K12)

ANTI SHOCK INPUT GAIN

KRAM DATA (K13)

FOCUS AUTO GAIN

KRAM DATA (K14)

HPTZC / AUTO GAIN HIGH PASS FILTER A

KRAM DATA (K15)

HPTZC / AUTO GAIN HIGH PASS FILTER B

KRAM DATA (K16)

ANTI SHOCK HIGH PASS FILTER A

KRAM DATA (K17)

HPTZC / AUTO GAIN LOW PASS FILTER B

KRAM DATA (K18)

FIX

KRAM DATA (K19)

TRACKING INPUT GAIN

KRAM DATA (K1A)

TRACKING HIGH CUT FILTER A

KRAM DATA (K1B)

TRACKING HIGH CUT FILTER B

KRAM DATA (K1C)

TRACKING LOW BOOST FILTER A-H

KRAM DATA (K1D)

TRACKING LOW BOOST FILTER A-L

KRAM DATA (K1E)

TRACKING LOW BOOST FILTER B-H

KRAM DATA (K1F)

TRACKING LOW BOOST FILTER B-L

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 1SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($341X)

– 20 –

CXD2598Q

KRAM DATA (K20)

TRACKING PHASE COMPENSATE FILTER A

KRAM DATA (K21)

TRACKING PHASE COMPENSATE FILTER B

KRAM DATA (K22)

TRACKING OUTPUT GAIN

KRAM DATA (K23)

TRACKING AUTO GAIN

KRAM DATA (K24)

FOCUS GAIN DOWN HIGH CUT FILTER A

KRAM DATA (K25)

FOCUS GAIN DOWN HIGH CUT FILTER B

KRAM DATA (K26)

FOCUS GAIN DOWN LOW BOOST FILTER A-H

KRAM DATA (K27)

FOCUS GAIN DOWN LOW BOOST FILTER A-L

KRAM DATA (K28)

FOCUS GAIN DOWN LOW BOOST FILTER B-H

KRAM DATA (K29)

FOCUS GAIN DOWN LOW BOOST FILTER B-L

KRAM DATA (K2A)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER A

KRAM DATA (K2B)

FOCUS GAIN DOWN DEFECT HOLD GAIN

KRAM DATA (K2C)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER B

KRAM DATA (K2D)

FOCUS GAIN DOWN OUTPUT GAIN

KRAM DATA (K2E)

NOT USED

KRAM DATA (K2F)

NOT USED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($342X)

– 21 –

CXD2598Q

KRAM DATA (K30)

SLED INPUT GAIN (when SFSK = 1 TGup2)

KRAM DATA (K31)

ANTI SHOCK LOW PASS FILTER B

KRAM DATA (K32)

NOT USED

KRAM DATA (K33)

ANTI SHOCK HIGH PASS FILTER B-H

KRAM DATA (K34)

ANTI SHOCK HIGH PASS FILTER B-L

KRAM DATA (K35)

ANTI SHOCK FILTER COMPARATE GAIN

KRAM DATA (K36)

TRACKING GAIN UP2 HIGH CUT FILTER A

KRAM DATA (K37)

TRACKING GAIN UP2 HIGH CUT FILTER B

KRAM DATA (K38)

TRACKING GAIN UP2 LOW BOOST FILTER A-H

KRAM DATA (K39)

TRACKING GAIN UP2 LOW BOOST FILTER A-L

KRAM DATA (K3A)

TRACKING GAIN UP2 LOW BOOST FILTER B-H

KRAM DATA (K3B)

TRACKING GAIN UP2 LOW BOOST FILTER B-L

KRAM DATA (K3C)

TRACKING GAIN UP PHASE COMPENSATE FILTER A

KRAM DATA (K3D)

TRACKING GAIN UP PHASE COMPENSATE FILTER B

KRAM DATA (K3E)

TRACKING GAIN UP OUTPUT GAIN

KRAM DATA (K3F)

NOT USED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 1SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($343X)

– 22 –

CXD2598Q

KRAM DATA (K40)

TRACKING HOLD FILTER INPUT GAIN

KRAM DATA (K41)

TRACKING HOLD FILTER A-H

KRAM DATA (K42)

TRACKING HOLD FILTER A-L

KRAM DATA (K43)

TRACKING HOLD FILTER B-H

KRAM DATA (K44)

TRACKING HOLD FILTER B-L

KRAM DATA (K45)

TRACKING HOLD FILTER OUTPUT GAIN

KRAM DATA (K46)

TRACKING HOLD INPUT GAIN (when THSK = 1 TGup2)

KRAM DATA (K47)

NOT USED

KRAM DATA (K48)

FOCUS HOLD FILTER INPUT GAIN

KRAM DATA (K49)

FOCUS HOLD FILTER A-H

KRAM DATA (K4A)

FOCUS HOLD FILTER A-L

KRAM DATA (K4B)

FOCUS HOLD FILTER B-H

KRAM DATA (K4C)

FOCUS HOLD FILTER B-L

KRAM DATA (K4D)

FOCUS HOLD FILTER OUTPUT GAIN

KRAM DATA (K4E)

NOT USED

KRAM DATA (K4F)

NOT USED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 1 0 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

Command Table ($344X)

– 23 –

CXD2598Q

0

1

0

PGFS, PFOK, RFAC

DOUT

Booster Surf Brake

Booster

FCS Bias Limit

FCS Bias Data

Traverse Center Data

3

1

0

1

0

1

0

1

0

1

0

1

0

1

PGFS1

A/D

SEL

SFBK1

THBON

0

1

0

PGFS0

COPY

EN

SFBK2

FHBON

0

1

0

RFOK1

EMPH

D

0

TLB1ON

0

FBL9

FB9

TV9

RFOK0

CAT

b8

0

FLB1ON

0

FBL8

FB8

TV8

0

DOUT

EN1

0

TLB2ON

0

FBL7

FB7

TV7

0

DOUT

DMUT

0

FBL6

FB6

TV6

0

DOUT

WOD

0

HBST1

0

FBL5

FB5

TV5

0

WIN

EN

0

HBST0

0

FBL4

FB4

TV4

0

DOUT

EN2

0

LB1S1

0

FBL3

FB3

TV3

0

LB1S0

0

FBL2

FB2

TV2

0

LB2S1

0

FBL1

FB1

TV1

0

LB2S0

0

—

TV0

SELECT

Register

Command

Address 1

D23 to D20

D19

D18 D17 D16

Address 2

D15

D15 D14

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2

Data 3Data 2Data 1Address 2

D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Command Table ($348X to 34FX)

—: Don’t care

0 0 1 1

– 24 –

CXD2598Q

FCS search, AGF

TRK jump, AGT

FZC, AGC, SLD move

DC measure, cancel

Serial data read out

FCS Bias, Gain,

Surf jump/brake

Mirr, DFCT, FOK

TZC, Cout, Bottom, Mirr

SLD filter

Filter

Clock, others

3

FT1

TDZC

FZSH

VCLM

DAC

0

SFO2

COSS

SFID

F1NM

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FT0

DTZC

FZSL

VCLC

SD6

FBON

SFO1

COTS

SFSK

F1DM

AGG4

FS5

TJ5

SM5

FLM

SD5

FBSS

SDF2

CETZ

THID

F3NM

XT4D

FS4

TJ4

SM4

FLC0

SD4

FBUP

SDF1

CETF

THSK

F3DM

XT2D

FS3

TJ3

SM3

RFLM

SD3

FBV1

MAX2

COT2

0

TINM

0

FS2

TJ2

SM2

RFLC

SD2

FBV0

MAX1

COT1

TLD2

TIUM

DRR2

FS1

TJ1

SM1

AGF

SD1

0

SFOX

MOT2

TLD1

T3NM

DRR1

FS0

TJ0

SM0

AGT

SD0

TJD0

BTF

0

TLD0

T3UM

DRR0

FTZ

SFJP

AGS

DFSW

0

FPS1

D2V2

BTS1

0

DF1S

0

FG6

TG6

AGJ

LKSW

0

FPS0

D2V1

BTS0

0

TLCD

ASFG

FG5

TG5

AGGF

TBLM

0

TPS1

D1V2

MRC1

0

FTQ

FG4

TG4

AGGT

TCLM

0

TPS0

D1V1

MRC0

0

LKIN

LPAS

FG3

TG3

AGV1

FLC1

0

RINT

0

COIN

0

FG2

TG2

AGV2

TLC2

0

SJHD

0

MDFI

0

FG1

TG1

AGHS

TLC1

0

INBK

0

MIRI

AGHF

FG0

TG0

AGHT

TLC0

0

MTI0

0

XT1D

ASOT

SELECT

Register

Command

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

0 0 1 1

Command Table ($35X to 3FX)

– 25 –

CXD2598Q

Auto sequence

Blind (A, E),

Brake (B),

Overflow (C, G)

Sled KICK,

BRAKE (D),

KICK (F)

Auto sequence (N)

track jump

count setting

MODE

specification

Function

specification

Audio CTRL

Traverse monitor

counter setting

Spindle servo

coefficient setting

CLV CTRL

SPD mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

AS3

TR3

SD3

32768

CD-

ROM

1

VARI

ON

32768

Gain

MDP1

0

CM3

AS2

TR2

SD2

16384

DOUT

Mute

DSPB

ON/OFF

VARI

USE

16384

Gain

MDP0

TB

CM2

AS1

TR1

SD1

8192

DOUT

Mute-F

ASEQ

ON/OFF

Mute

8192

Gain

MDS1

TP

CM1

AS0

TR0

SD0

4096

WSEL

1

ATT

4096

Gain

MDS0

CLVS

Gain

CM0

MT3

0

KF3

2048

VCO

SEL1

BiliGL

MAIN

PCT1

2048

Gain

DCLV1

VP7

EPWM

MT2

0

KF2

1024

ASHS

BiliGL

SUB

PCT2

1024

Gain

DCLV0

VP6

SPDC

MT1

0

KF1

512

SOCT0

FLFC

MCSL

512

PCC1

VP5

ICAP

MT0

0

KF0

256

VCO

SEL2

XWOC

SOC2

256

PCC0

VP4

SFSL

LSSL

0

128

KSL3

DAC

EMO

DCOF

128

SFP3

VP3

VC2C

0

64

KSL2

DAC

ATT

FMUT

64

SFP2

VP2

HIFC

0

32

KSL1

SYCOF

BSBST

32

SFP1

VP1

LPWR

0

16

KSL0

0

BBST

16

SFP0

VP0

VPON

—

8

0

PLM3

ATTCH

SEL

8

SRP3

VP

CTL1

Gain

CAV1

—

4

0

PLM2

ATD10

4

SRP2

VP

CTL0

Gain

CAV0

—

2

XVCO2

THRU

PLM1

ATD9

2

SRP1

0

—

1

0

PLM0

ATD8

1

SRP0

0

INV

VPCO

4

5

6

7

8

9

A

B

C

D

E

Register

Command

Address

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 1 Data 2 Data 3 Data 4

Command Table ($4X to EX)

—: Don’t care

– 26 –

CXD2598Q

FOCUS SERVO OFF,

0V OUT

TRACKING GAIN UP

FILTER SELECT 1

TRACKING SERVO OFF

SLED SERVO OFF

SLED KICK LEVEL

(±1 × basic value) (Default)

KRAM DATA

($3400XX to $344fXX)

0

1

0

—

0

1

2

0 0 0 0

0 0 0 1

0 0 1 0

FOCUS

CONTROL

TRACKING

CONTROL

TRACKING

MODE

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Register

Command

3 SELECT

Address

D23 to D20

0 0 1 1

0 0 1 1 0 1 0 0 0

See "Coefficient ROM Preset Values Table".

0 0 0 0 — — — — — — — — — — — — — — — —

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D0 D0

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Address 3

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D0 D0

§1-3. CPU Command Presets

Command Preset Table ($0X to 34X)

—: Don’t care

MODE

specification

1 0 0 08

Function

specification

Audio CTRL

Traverse monitor

counter setting

Spindle servo

coefficient setting

1 0 0 1

1 0 1 0

1 0 1 1

9

A

B

C

Register

Command

Address Data 1

Data 2

Data 3

Data 4

—: Don’t care

ERC4

SCOR

SEL

SCSY SOCT1 TXON

TXOUT OUTLI OUTL0

DAC

SMUTL

ATD7

0

EDC7

DAC

SMUTR

ATD6

LRMIX

EDC6

ZMUT

ATD5

MTSL1

EDC5

ZDPL

ATD4

MTSL0

EDC4

0

ATD3

—

EDC3

0

ATD2

—

EDC2

0

ATD1

—

EDC1

0

ATD0

—

EDC0

D3 D2 D1 D0 D3 D2 D1 D0

Data 5 Data 6

FSTIN 0 OUTL2 0

DIV4 0 0 0

D3 D2 D1 D0

Data 7

Command Table ($4X to EX) cont.

– 27 –

CXD2598Q

Command Preset Table ($348X to 34FX)

0010

PGFS, PFOK, RFAC

DOUT

Booster Surf Brake

Booster

FCS Bias Limit

FCS Bias Data

Traverse Center Data

3

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SELECT

Register

Command

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2

Data 3Data 2Data 1Address 2

D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

0 0 1 1

– 28 –

CXD2598Q

FCS search, AGF

TRK jump, AGT

FZC, AGC, SLD move

DC measure, cancel

Serial data read out

FCS Bias, Gain,

Surf jump/brake

Mirr, DFCT, FOK

TZC, Cout, Bottom, Mirr

SLD filter

Filter

Clock, others

3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SELECT

Register

Command

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

0 0 1 1

Command Preset Table ($35X to 3FX)

– 29 –

CXD2598Q

Auto sequence

Blind (A, E),

Brake (B),

Overflow (C, G)

Sled KICK,

BRAKE (D),

KICK (F)

Auto sequence (N)

track jump count

setting

MODE

specification

Function

specification

Audio CTRL

Traverse monitor

counter setting

Spindle servo

coefficient setting

CLV CTRL

SPD mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

0

1

0

—

0

1

0

—

0

1

0

—

0

1

0

1

0

4

5

6

7

8

9

A

B

C

D

E

Register

Command

Address

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 1 Data 2 Data 3 Data 4

Command Preset Table ($4X to EX)

—: Don’t care

MODE specification

Function specification

Audio CTRL

Traverse monitor

counter setting

Spindle servo

coefficient setting

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

8

9

A

B

C

Register

Command

Address Data 1

Data 2

Data 3

Data 4

D3 D2 D1 D0 D3 D2 D1 D0

Data 5 Data 6

0

—

0

—

0

—

0

—

0

D3 D2 D1 D0

Data 7

0

– 30 –

CXD2598Q

ADDRESS

K00 K01 K02 K03 K04 K05 K06 K07 K08 K09 K0A

K0B K0C K0D K0E K0F

E0

81 23 7F

6A

10 14 30 7F 46 81

1C

7F 58 82 7F

SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19 K1A K1B K1C K1D K1E K1F

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29 K2A K2B K2C K2D K2E K2F

4E

32 20 30 80 77 80 77 00 F1 7F

3B

81 44 7F

5E

FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix

∗

TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L

82 44 18 30 7F 46 81

3A

7F 66 82

44 4E 1B

00

TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED

DATA CONTENTS

∗

Fix indicates that normal preset values should be used.