Sony CXD2588R, CXD2588Q Datasheet
Description
The CXD2588Q/R is a digital signal processor LSI
for CD players. This LSI incorporates a digital servo,
digital filter, zero detection circuit, 1-bit DAC and
analog low-pass filter on a single chip.
Features
Digital Signal Processor (DSP) Block
• Playback mode which supports CAV (Constant
Angular Velocity)
• Frame jitter free
• 0.5× to 4× continuous playback possible
• Allows relative rotational velocity readout
• Supports spindle external control
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports normal-speed, 4× speed playback
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry compensation circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Digital audio interface outputs
• Digital level meter, peak meter
• CD TEXT data demodulation
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
Digital Filter, DAC and Analog Low-Pass Filter Blocks
• DBB (digital bass boost) function
• Double-speed playback supported
• Digital de-emphasis
• Digital attenuation
• Zero detection function
• 8Fs oversampling digital filter
• S/N: 100dB or more (master clock: 384Fs, typ.)
• Logical value: 109dB
• THD + N: 0.007% or less (master clock: 384Fs, typ.)
• Rejection band attenuation: –60dB or less
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage VDD –0.3 to +7.0 V
• Input voltage VI –0.3 to +7.0 V
(VSS – 0.3V to VDD + 0.3)
• Output voltage VO –0.3 to +7.0 V
• Storage temperature Tstg –40 to +125 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Recommended Operating Conditions
• Supply voltage VDD
Note)
+2.7 to +5.5 V
•
Operating temperature
Topr –20 to +75 °C
Note) The VDD for the CXD2588Q/R varies according
to the playback speed selection.
– 1 –
CXD2588Q/R
E97519-PS
CD Digital Signal Processor with Built-in Digital Servo and DAC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXD2588Q
100 pin QFP (Plastic)
CXD2588R
100 pin LQFP (Plastic)
Playback
speed
CD-DSP block DAC block
4×
4.75 to 5.25
1×
3.0 to 5.5 4.5 to 5.5
2.7 to 5.5
1×
2.7 to 5.5
VDD [V]
I/O Capacitance
• Input pin CI 11 (Max.) pF
• Output pin CO 11 (Max.) pF
• I/O pin CI/O 11 (Max.) pF
Note) Measurement conditions VDD = VI = 0V
fM = 1MHz
For the availability of this product, please contact the sales office.
– 2 –
CXD2588Q/R
Block Diagram
PWM PWM
AOUT1
AIN1
LOUT1
AOUT2
AIN2
LOUT2
3rd-Order
Noise Shaper
Over Sampling
Digital Filter
Serial-In
Interface
LMUT
RMUT
XTAO
XTAI
Timing
Logic
XRST
TEST
TES1
D/A
Interface
DOUT
EFM
demodurator
Error
Corrector
16K
RAM
Digital
OUT
Sub Code
Processor
Clock
Generator
Asymmetry
Corrector
Digital
PLL
CPU
Interface
Servo
Auto
Sequencer
DAC Block
PCMDI
BCK
PCMD
LRCK
C2PO
WFCK
EMPH
GFS
XUGF
XTSL
RFAC
ASYI
ASYO
BIAS
FSTO
FILO
FILI
PCO
CLTV
MDP
PWMI
SENS
DATA
XLAT
CLOK
SPOA
SPOB
XLON
SCOR
SBSO
EXCK
SERVO
Interface
SCLK
COUT
SSTP
ATSK
MIRR
DFCT
FOK
MIRR
DFCT
FOK
SERVO DSP
FOCUS SERVO
TRACKING
SERVO
SLED SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING PWM
GENERATOR
SLED PWM
GENERATOR
FFDR
FRDR
TFDR
TRDR
SFDR
SRDR
RFDC
CE
TE
SE
FE
VC
IGEN
OPAmp
Analog SW
A/D
Converter
ADIO
BCKI
SYSM
LRCKI
EMPHI
WDCK
VPCO
VCKI
OSC
V16M
VCTL
XPCK
C4M
SQSO
SQCK
LOCK
Digital
CLV
FSTI
TES2
Signal Processor
Block
Servo Block
– 3 –
CXD2588Q/R
Pin Configuration (CXD2588Q)
LMUT
NC
SQSO
SQCK
SBSO
EXCK
XRST
SYSM
DATA
XLAT
CLOK
SENS
SCLK
PWMI
V
DD
V
DD
ATSK
SPOA
SPOB
XLON
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
C4M
WDCK
COUT
MIRR
PCMD
LRCKI
LRCK
DOUT
V
DD
TES2
V
SS
VPCO
V16M
VCKI
VCTL
AV
DD
3
PCO
FILI
FILO
CLTV
AV
SS
3
RFAC
BIAS
ASYI
ASYO
AV
DD
0
IGEN
AV
SS
0
ADIO
RFDC
CE
TE
NC
SE
FE
VC
XTSL
TES1
TEST
VSS
VSS
FRDR
FFDR
TRDR
TFDR
SRDR
SFDR
FSTI
FSTO
SSTP
MDP
LOCK
FOK
DFCT
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
76
77
78
79
80
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
81
82
83
84
88
87
86
85
89
90
100
99
98
97
96
95
94
91
92
93
PCMDI
BCK
BCKI
EMPH
EMPHI
XVDD
XTAI
XTAO
XV
SS
AVDD1
AOUT1
AIN1
LOUT1
AV
SS1
AVSS2
LOUT2
AIN2
AOUT2
AVDD2
RMUT
– 4 –
CXD2588Q/R
Pin Configuration (CXD2588R)
SQSO
SQCK
SBSO
EXCK
XRST
SYSM
DATA
XLAT
CLOK
SENS
SCLK
PWMI
V
DD
V
DD
ATSK
SPOA
SPOB
XLON
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
C4M
DOUT
V
DD
TES2
V
SS
VPCO
V16M
VCKI
VCTL
AV
DD
3
PCO
FILI
FILO
CLTV
AV
SS
3
RFAC
BIAS
ASYI
ASYO
AV
DD
0
IGEN
AV
SS
0
ADIO
RFDC
CE
TE
LRCK
LRCKI
PCMD
PCMDI
BCK
BCKI
EMPH
EMPHI
XVDD
XTAI
XTAO
XVSS
AVDD1
AOUT1
AIN1
LOUT1
AVSS1
AVSS2
LOUT2
AIN2
AOUT2
AVDD2
RMUT
LMUT
NC
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
1
76
77
78
79
80
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
41
42
43
44
45
46
47
48
49
50
81
82
83
84
88
87
86
85
89
90
100
99
98
97
96
95
94
91
92
93
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
73
74
75
NC
SE
FE
VC
XTSL
TES1
TEST
V
SS
VSS
FRDR
FFDR
TRDR
TFDR
SRDR
SFDR
FSTI
FSTO
SSTP
MDP
LOCK
FOK
DFCT
MIRR
COUT
WDCK
– 5 –
CXD2588Q/R
Pin Description
CXD
2588Q
Symbol
Output
values
Description
Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data
output.
SQSO readout clock input.
Sub Q P to W serial output.
SBSO readout clock input.
System reset. Reset when low.
Mute input. Muted when high.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
SENS output to CPU.
SENS serial data readout clock input.
Spindle motor external control input.
Digital power supply.
Digital power supply.
Anti-shock input/output.
Microcomputer extension interface (input A)
Microcomputer extension interface (input B)
Microcomputer extension interface (output)
WFCK output.
XUGF output. MINT1 or RFCK is output by switching with the command.
XPCK output. MNT0 is output by switching with the command.
GFS output. MNT3 or XROF is output by switching with the command.
C2PO output. GTOP is output by switching with the command.
Outputs a high signal when either subcode sync S0 or S1 is detected.
4.2336MHz output. In CAV-W mode, 1/4 frequency division output for VCKI.
Word clock output. f = 2Fs.
Track count signal input/output.
Mirror signal input/output.
Defect signal input/output.
Focus OK signal input/output.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a
high signal. If GFS is low eight consecutive samples, this pin
outputs low. Or input when LKIN = 1.
Spindle motor servo control output.
Disc innermost track detection signal input.
2/3 frequency division output for XTAI pin.
1, 0
1, 0
1, 0
—
—
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, Z, 0
1, 0
O
I
O
I
I
I
I
I
I
O
I
I
—
—
I/O
I
I
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
O
I
O
SQSO
SQCK
SBSO
EXCK
XRST
SYSM
DATA
XLAT
CLOK
SENS
SCLK
PWMI
VDD
VDD
ATSK
SPOA
SPOB
XLON
WFCK
XUGF
XPCK
GFS
C2PO
SCOR
C4M
WDCK
COUT
MIRR
DFCT
FOK
LOCK
MDP
SSTP
FSTO
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I/O
CXD
2588R
Pin No.
– 6 –
CXD2588Q/R
CXD
2588Q
Symbol
Output
values
Description
2/3 frequency division input for XTAI pin.
Sled drive output.
Sled drive output.
Tracking drive output.
Tracking drive output.
Focus drive output.
Focus drive output.
Digital GND.
Digital GND.
Test pin. Normally, GND.
Test pin. Normally, GND.
Crystal selection input. Low when the crystal is 16.9344MHz; high
when the crystal is 33.8688MHz.
Center voltage input.
Focus error signal input.
Sled error signal input.
Tracking error signal input.
Center servo analog input.
RF signal input.
Test pin. No connected.
Analog GND.
Operational amplifier constant current input.
Analog power supply.
EFM full-swing output. (low = Vss, high = VDD)
Asymmetry comparator voltage input.
Asymmetry circuit constant current input.
EFM signal input.
Analog GND.
Multiplier VCO1 control voltage input.
Master PLL filter output. (slave = digital PLL)
Master PLL filter input.
Master PLL charge pump output.
Analog power supply.
Wide-band EFM PLL VCO2 control voltage input.
Wide-band EFM PLL VCO2 oscillation input.
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
—
—
Analog
—
—
1, 0
—
Analog
1, Z, 0
—
I
O
O
O
O
O
O
—
—
I
I
I
I
I
I
I
I
I
O
—
I
—
O
I
I
I
—
I
O
I
O
—
I
I
FSTI
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
VSS
VSS
TEST
TES1
XTSL
VC
FE
SE
NC
TE
CE
RFDC
ADIO
AVSS0
IGEN
AVDD0
ASYO
ASYI
BIAS
RFAC
AVSS3
CLTV
FILO
FILI
PCO
AVDD3
VCTL
VCKI
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
I/O
CXD
2588R
Pin No.
– 7 –
CXD2588Q/R
CXD
2588Q
Symbol
Output
values
Description
Wide-band EFM PLL VCO2 oscillation output.
Wide-band EFM PLL charge pump output.
Digital GND.
Test pin. Normally GND.
Digital power supply.
Digital Out output.
D/A interface. LR clock output f = Fs.
D/A interface. LR clock input.
D/A interface. Serial data output.
(two's complement, MSB first)
D/A interface. Serial data input.
(two's complement, MSB first)
D/A interface. Bit clock output.
D/A interface. Bit clock input.
Outputs a high signal when the playback disc has emphasis, and a
low signal when there is no emphasis.
Inputs a high signal when de-emphasis is on, and a low signal when
de-emphasis is off.
Master clock power supply.
Crystal oscillation circuit input. Master clock is externally input from
this pin.
Crystal oscillation circuit output.
Master clock GND.
Analog power supply.
L ch analog output.
L ch operational amplifier input.
L ch LINE output.
Analog GND.
Analog GND.
R ch LINE output.
R ch operational amplifier output.
R ch analog output.
Analog power supply.
R ch zero detection flag.
L ch zero detection flag.
1, 0
1, Z, 0
—
—
1, 0
1, 0
1, 0
1, 0
1, 0
—
—
—
—
—
—
1, 0
1, 0
O
O
—
I
—
O
O
I
O
I
O
I
O
I
—
I
O
—
—
O
I
O
—
—
O
I
O
—
O
O
V16M
VPCO
VSS
TES2
VDD
DOUT
LRCK
KRCKI
PCMD
PCMDI
BCK
BCKI
EMPH
EMPHI
XVDD
XTAI
XTAO
XVSS
AVDD1
AOUT1
AIN1
LOUT1
AVSS1
AVSS2
LOUT2
AIN2
AOUT2
AVDD2
RMUT
LMUT
NC
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
CXD
2588R
Pin No.
– 8 –
CXD2588Q/R
Notes) • PCMD is a MSB first, two's complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before
sync protection.
• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
• C2PO represents the data error status.
• XROF is generated when the 16K RAM exceeds the ±4F jitter margin.
Monitor Pin Output Combinations
0
0
1
MTSL1
0
1
0
MTSL0
XUGF
MNT1
RFCK
XPCK
MNT0
XPCK
GFS
MNT3
XROF
C2PO
C2PO
GTOP
Command bit
Output data
– 9 –
CXD2588Q/R
Electrical Characteristics
1. DC Characteristics (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Applicable pins
∗1
SYSM, DATA, XLAT, PWMI, SSTP, FSTI, XTSL, TEST, TES1, VCKI, TES2
∗2
SQCK, XRST, CLOK
∗3
LRCKI, PCMDI, BCKI, EMPHI
∗4
ASYI, RFAC, CLTV, FILI, VCTL
∗5
SQSO, SBSO, SENS, ATSK, XLON, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK, COUT,
MIRR, DFCT, FOK, LOCK, FSTO, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, LRCK,
PCMD, BCK, EMPH, RMUT, LMUT
∗6
V16M
∗7
MDP, PCO, VPCO
∗8
FILO
∗9
VC, FE, SE, TE, CE
∗10
RFDC
∗11
EXCK, ATSK, COUT, MIRR, DFCT, FOK, LOCK
∗12
SCLK, SPOA, SPOB
Item
Input
voltage (1)
Input
voltage (2)
Input
voltage (3)
Input
voltage (4)
Output
Avoltage (1)
Output
Avoltage (2)
Output
Avoltage (3)
Output
Avoltage (4)
Input leak current (1)
Input leak current (2)
Input leak current (3)
Input leak current (4)
∗1, ∗11
∗2, ∗12
∗3
∗4, ∗9, ∗10
∗5
∗6
∗7
∗1, ∗2
∗11, ∗12
∗9
∗10
∗8
Schmitt input
Analog input
IOH = –2mA
IOL = 4mA
IOH = –4mA
IOL = 8mA
IOH = –6mA
IOL = 4mA
IOH = –0.28mA
IOL = 0.36mA
VIN = VSS
or VDD
VIN = VSS
or VDD
VI = 1.5 to 3.5V
VI = 0 to 5.0V
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
Input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
VIH (1)
VIL (1)
VIH (2)
VIL (2)
VIH (3)
VIL (3)
VIN (4)
VOH (1)
VOL (1)
VOH (2)
VOL (2)
VOH (3)
VOL (3)
VOH (4)
VOL (4)
ILI (1)
ILI (2)
ILI (3)
ILI (4)
0.7VDD
0.8VDD
0.8VDD
Vss
VDD – 0.8
Vss
VDD – 0.8
Vss
VDD – 0.8
Vss
VDD – 0.5
Vss
–10
–40
–20
–40
0.3VDD
0.2VDD
0.2VDD
VDD
VDD
0.4
VDD
0.4
VDD
0.4
VDD
0.4
10
40
20
600
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
Conditions Min. Typ. Max. Unit
Applicable
pins
– 10 –
CXD2588Q/R
2. AC Characteristics
(1) XTAI pin
(a) When using self-excited oscillation
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
(b) When inputting pulses to XTAI pin
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
(c) When inputting sine waves to XTAI pin via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Oscillation
frequency
fMAX
7
34
MHz
Item Symbol Min. Typ. Max.
Unit
High level pulse
width
tWHX
13 500
ns
Low level pulse
width
tWLX
13 500
ns
Pulse cycle
tCK
26 1,000
ns
Input high level VIHX VDD – 1.0
V
Input low level VILX 0.8
V
Rise time, fall
time
tR, tF
10
ns
Item Symbol Min.
Typ. Max. Unit
Input amplitude VI 2.0 VDD + 0.3 Vp-p
Item Symbol Min.
Typ. Max. Unit
tR tF
tWHX
tWLX
tCX
VILX
VIHX × 0.1
V
IHX × 0.9
VIHX
XTAI
V
DD/2
– 11 –
CXD2588Q/R
(2) CLOK, DATA, XLAT, COUT, SQCK, and EXCK pins
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum
operating frequency is 300kHz and its minimum pulse width is 1.5µs.
(3) BCKI, LRCKI and PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK, SQCK frequency
EXCK, SQCK pulse width
fCK
tWCK
tSU
tH
tD
tWL
fT
fWT
750
300
300
300
750
750
Note)
0.65
0.65
Note)
MHz
ns
ns
ns
ns
ns
MHz
ns
Item Symbol
Min. Typ. Max. Unit
tWCK tWCK
1/fCK
tH
tSU
tWL
tD
1/fT
tWT tWT
tH
tSU
CLOK
DATA
XLAT
EXCK
SQCK
SBSO
SQSO
BCK pulse width
DATAL, R setup time
DATAL, R hold time
LRCK setup time
tW
tSU
tH
tSU
ns
ns
ns
ns
Item Symbol
Conditions
Typ.
94
18
18
18
Min.
Max.
Unit
VDD/2 VDD/2
tW(BCKI)tW(BCKI)
tSU
(PCMDI)
t
H
(PCMDI)
tSU
(LRCKI)
BCKI
PCMDI
LRCKI
– 12 –
CXD2588Q/R
(5) COUT, MIRR and DFCT pins
Operating frequency (VDD = AVDD = 5.0V ±5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
COUT maximum
operating frequency
MIRR maximum
operating frequency
DFCT maximum
operating frequency
fCOUT
fMIRR
fDFCTH
40
40
5
kHz
kHz
kHz
∗1
∗2
∗3
Item Symbol
Min. Typ.
Max.
Unit
Conditions
∗1
When using a high-speed traverse TZC
∗2
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.12VDD to 0.26VDD
• = 25%
∗3
During complete RF signal omission
When settings related to DFCT signal generation are Typ.
(4) SCLK pin
SCLK frequency
SCLK pulse width
Delay time
fSCLK
tSPW
tDLS
31.3
15
16 MHz
ns
µs
Item
Symbol Min. Typ. Max.
Unit
tSPWtDLS
1/fSCLK
MSB LSB•••
•••
XLAT
SCLK
Serial Read Out Data
(SENS)
A
B
B
A + B
– 13 –
CXD2588Q/R
1-bit DAC and LPF Block Analog Characteristics
Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)
Fs = 44.1kHz in all cases.
The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.
LPF external circuit diagram
Block diagram of analog characteristics measurement
Item
Total harmonic
distortion
Signal-to-noise
ratio
Symbol
THD
S/N
Conditions
1kHz, 0dB data
Crystal
1kHz, 0dB data
(Using A-weighting filter)
384Fs
768Fs
384Fs
768Fs
96
96
0.0050
0.0045
100
100
0.0070
0.0065
Min.
Typ.
Max.
Unit
%
dB
Audio Analyzer
SHIBASOKU (AM51A)
100k
22µ
680p
12k
12k
12k
150p
AOUT1 (2)
AIN1 (2)
LOUT1 (2)
Audio Analyzer
CXD2588Q/R
Rch A
Lch B
DATA RF
TEST DISC
768Fs/384Fs
– 14 –
CXD2588Q/R
(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C)
Output voltage
Load resistance
VOUT
RL
∗1
∗1
Vrms
kΩ
Item Symbol
8
Min.
Max.
1.12
Typ.
Applicable pins
Unit
∗
Measurement is conducted for the LPF external circuit diagram with the sine wave output of 1kHz and 0dB.
Applicable pins
∗1
LOUT1, LOUT2
– 15 –
CXD2588Q/R
Contents
§1. CPU Interface
§1-1. CPU Interface Timing ........................................................................................................................ 16
§1-2. CPU Interface Command Table ........................................................................................................16
§1-3. CPU Command Presets .................................................................................................................... 26
§1-4. Description of SENS Signals and Commands ................................................................................... 31
§2. Subcode Interface
§2-1. P to W Subcode Readout .................................................................................................................. 51
§2-2. 80-bit Sub Q Readout ........................................................................................................................ 51
§3. Description of Modes
§3-1. CLV-N Mode ...................................................................................................................................... 56
§3-2. CLV-W Mode ..................................................................................................................................... 56
§3-3. CAV-W Mode ..................................................................................................................................... 56
§4. Description of Other Functions
§4-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 58
§4-2. Frame Sync Protection ...................................................................................................................... 60
§4-3. Error Correction ................................................................................................................................. 60
§4-4. DA Interface ....................................................................................................................................... 61
§4-5. Digital Out .......................................................................................................................................... 63
§4-6. Servo Auto Sequence ....................................................................................................................... 63
§4-7. Digital CLV ......................................................................................................................................... 70
§4-8. CD-DSP Block Playback Speed ........................................................................................................ 71
§4-9. DAC Block Playback Speed .............................................................................................................. 71
§4-10. DAC Block Input Timing .................................................................................................................... 72
§4-11. Description of DAC Block Functions .................................................................................................. 72
§4-12. LPF Block .......................................................................................................................................... 76
§4-13. Asymmetry Compensation ................................................................................................................ 77
§4-14. CD Text Data Demodulation .............................................................................................................. 78
§5. Description of Servo Signal Processing System Functions and Commands
§5-1. General Description of Servo Signal Processing System .................................................................. 80
§5-2. Digital Servo Block Master Clock (MCK) ........................................................................................... 81
§5-3. AVRG Measurement and Compensation .......................................................................................... 81
§5-4. E:F Balance Adjustment Function ..................................................................................................... 83
§5-5. FCS Bias Adjustment Function .......................................................................................................... 83
§5-6. AGCNTL Function ............................................................................................................................. 85
§5-7. FCS Servo and FCS Search .............................................................................................................87
§5-8. TRK and SLD Servo Control .............................................................................................................88
§5-9. MIRR and DFCT Signal Generation .................................................................................................. 89
§5-10. DFCT Countermeasure Circuit .......................................................................................................... 90
§5-11. Anti-Shock Circuit .............................................................................................................................. 90
§5-12. Brake Circuit ...................................................................................................................................... 91
§5-13. COUT Signal ..................................................................................................................................... 92
§5-14. Serial Readout Circuit ........................................................................................................................ 92
§5-15. Writing to the Coefficient RAM .......................................................................................................... 93
§5-16. PWM Output ...................................................................................................................................... 93
§5-17. Servo Status Changes Produced by the LOCK Signal ..................................................................... 95
§5-18. Description of Commands and Data Sets ......................................................................................... 95
§5-19. List of Servo Filter Coefficients ........................................................................................................ 110
§5-20. Filter Composition ............................................................................................................................ 112
§5-21. TRACKING and FOCUS Frequency Response .............................................................................. 119
§6. Application Circuit .................................................................................................................................. 120
Explanation of abbreviations AVRG: Average
AGCNTL: Auto gain control
FCS: Focus
TRK: Tracking
SLD: Sled
DFCT: Defect
– 16 –
CXD2588Q/R
§1. CPU Interface
§1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
• The internal registers are initialized by a reset when XRST = 0.
Note) Be sure to set SQCK to high when XLAT is low.
§1-2. CPU Interface Command Table
Total bit length for each register
Register
0 to 2
3
4 to 6
7
8
9
A
B
C
D
E
8 bits
8 to 24 bits
8 bits
20 bits
28 bits
24 bits
28 bits
16 bits
8 bits
16 bits
20 bits
Total bit length
750ns or more
D18 D19 D20 D21 D22 D23
750ns or more
Valid
CLOK
DATA
XLAT
Registers
D0 D1
– 17 –
CXD2588Q/R
Command Table ($0X to 1X)
FOCUS SERVO ON
(FOCUS GAIN
NORMAL)
FOCUS SERVO ON
(FOCUS GAIN
DOWN)
FOCUS SERVO OFF,
0V OUT
FOCUS SERVO OFF,
FOCUS SEARCH
VOLTAGE OUT
FOCUS SEARCH
VOLTAGE DOWN
FOCUS SEACH
VOLTAGE UP
ANTI SHOCK ON
ANTI SHOCK OFF
BRAKE ON
BRAKE OFF
TRACKING GAIN
NORMAL
TRACKING GAIN UP
TRACKING GAIN UP
FILTER SELECT 1
TRACKING GAIN UP
FILTER SELECT 2
1
1
0
0
0
0
1
0
—
—
—
—
—
—
0
1
—
—
—
—
0
—
1
0
—
—
—
—
—
—
0
1
1
1
—
—
—
—
0
1
—
—
—
—
—
—
0
1
—
—
—
—
—
—
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0 0 0 0
0 0 0 1
FOCUS
CONTROL
TRACKING
CONTROL
Register
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
—: Don’t care
– 18 –
CXD2588Q/R
Command Table ($2X to 3X)
TRACKING SERVO OFF
TRACKING SERVO ON
FORWARD TRACK JUMP
REVERSE TRACK JUMP
SLED SERVO OFF
SLED SERVO ON
FORWARD SLED MOVE
REVERSE SLED MOVE
SLED KICK LEVEL
(±1 × basic value) (Default)
SLED KICK LEVEL
(±2
×
basic value)
SLED KICK LEVEL
(±3
×
basic value)
SLED KICK LEVEL
(±4
×
basic value)
0
0
1
1
—
—
—
—
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0
1
—
—
—
—
—
—
—
—
0
0
1
1
—
—
—
—
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
3
0 0 1 0
0 0 1 1
TRACKING
MODE
SELECT
Register
Command
Address
D23 to D20
Register
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
—: Don’t care
– 19 –
CXD2588Q/R
Command Table ($340X)
KRAM DATA (K00)
SLED INPUT GAIN
KRAM DATA (K01)
SLED LOW BOOST FILTER A-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K05)
SLED OUTPUT GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K07)
SLED AUTO GAIN
KRAM DATA (K08)
FOCUS HIGH CUT FILTER A
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0C)
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 0 0
SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
– 20 –
CXD2588Q/R
Command Table ($341X)
KRAM DATA (K10)
FOCUS PHASE COMPENSATE FILTER B
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K14)
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
KRAM DATA (K18)
FIX
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K1A)
TRACKING HIGH CUT FILTER A
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 0 1
SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
– 21 –
CXD2588Q/R
Command Table ($342X)
KRAM DATA (K20)
TRACKING PHASE COMPENSATE FILTER A
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 1 0
SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
– 22 –
CXD2588Q/R
Command Table ($343X)
KRAM DATA (K30)
SLED INPUT GAIN (when SFSK = 1 TG up2)
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K32)
NOT USED
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KRAM DATA (K3F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 1 1
SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
– 23 –
CXD2588Q/R
Command Table ($344X)
KRAM DATA (K40)
TRACKING HOLD FILTER INPUT GAIN
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K46)
TRACKING HOLD INPUT GAIN (when THSK = 1 TG up2)
KRAM DATA (K47)
NOT USED
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 1 0 0
SELECT
Register
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
– 24 –
CXD2588Q/R
Command Table ($34FX to 3FX)
0 0 1 1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
FOCUS BIAS LIMIT
FOCUS BIAS DATA
TRVSC DATA
FOCUS SEARCH SPEED/
VOLTAGE/AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE/AUTO GAIN
FZSL/SLED MOVE/
Voltage/AUTO GAIN
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
SERIAL DATA READ
MODE/SELECT
FOCUS BIAS
Operation for MIRR/
DFCT/FOK
TZC/COUT
BOTTOM/MIRR
SLED FILTER
Filter
Others
3
0 0 1 1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
FBL9
FB9
TV9
FBL8
FB8
TV8
FBL7
FB7
TV7
FBL6
FB6
TV6
FBL5
FB5
TV5
FBL4
FB4
TV4
FBL3
FB3
TV3
FBL2
FB2
TV2
FBL1
FB1
TV1
—
—
TV0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
FT1
TDZC
FZSH
VCLM
DAC
0
SFO2
FT0
DTZC
FZSL
VCLC
SD6
FBON
SFO1
FS5
TJ5
SM5
FLM
SD5
FBSS
SDF2
FS4
TJ4
SM4
FLC0
SD4
FBUP
SDF1
FS3
TJ3
SM3
RFLM
SD3
FBV1
MAX2
FS2
TJ2
SM2
RFLC
SD2
FBV0
MAX1
FS1
TJ1
SM1
AGF
SD1
0
SFOX
FS0
TJ0
SM0
AGT
SD0
TJD0
BTF
FTZ
SFJP
AGS
DFSW
0
FPS1
D2V2
FG6
TG6
AGJ
LKSW
0
FPS0
D2V1
FG5
TG5
AGGF
TBLM
0
TPS1
D1V2
FG4
TG4
AGGT
TCLM
0
TPS0
D1V1
FG3
TG3
AGV1
FLC1
0
0
RINT
FG2
TG2
AGV2
TLC2
0
SJHD
0
FG1
TG1
AGHS
TLC1
0
INBK
0
FG0
TG0
AGHT
TLC0
0
MTI0
0
1
1
1
1
1
1
1
1
0
1
F1NM
0
F1DM
AGG4
F3NM
XT4D
F3DM
XT2D
T1NM
0
T1UM
DRR2
T3NM
DRR1
T3UM
DRR0
DFIS
0
TLCD
ASFG
0
FTQ
LKIN
LPAS
COIN
SRO1
MDFI
0
MIRI
AGHF
XT1D
ASOT
1
1
0
0
0
1
COSS
SFID
COTS
SFSK
CETZ
THID
CETF
THSK
COT2
0
COT1
TLD2
MOT2
TLD1
0
TLD0
BTS1
0
BTS0
0
MRC1
0
MRC0
0
0
0
0
0
0
0
0
0
SELECT
Register
Command
Address 1
D23 to D20 D19 D18 D17 D16
Address 2
D15 D14 D13 D12
Data 1
D11 D10 D9 D8
Data 2
D7 D6 D5 D4
Data 3
D3 D2 D1 D0
Address
D23 to D20 D19 D18 D17 D16
Data 1
D15 D14 D13 D12
Data 2
D11 D10 D9 D8
Data 3
D7 D6 D5 D4
Data 4
D3 D2 D1 D0
—: Don’t care
– 25 –
CXD2588Q/R
Instruction Table
Register
4
5
6
7
8
9
A
B
C
D
E
Auto sequence
Blind (A, E),
Overflow (C)
Brake (B)
KICK (D)
Auto sequence (N)
track jump
count setting
MODE
specification
Function
specification
Audio CTRL
Serial bus
CTRL
Spindle servo
coefficient setting
CLV CTRL
CLV mode
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
1
1
0
0
1
0
1
0
1
0
1
1
0
0
1
0
1
0
—
—
—
2048
VCO
SEL1
0
0
0
0
TRMI
—
VP7
EPWM
—
—
—
1024
0
0
0
0
0
TRMO
—
VP6
SPDC
—
—
—
512
SOCT
0
0
OPSL20OPSL2
1
MTSL1
—
VP5
ICAP
—
—
—
256
VCO
SEL2
SYCOF
SYCOF
EMPH
EMPH
MTSL0
—
VP4
SFSL
—
—
—
128
KSL3
OPSL10OPSL1
1
SMUT
SMUT
0
—
VP3
VC2C
—
—
—
64
KSL2
MCSL
MCSL
0
0
0
—
VP2
HIFC
—
—
—
32
KSL1
0
0
AD9
AD9
0
—
VP1
LPWR
—
—
—
16
KSL0
0
0
AD8
AD8
0
—
VP0
VPON
—
—
—
8
0
ZDPL
ZDPL
AD7
AD7
—
—
—
Gain
CAV1
—
—
—
4
0
ZMUT
ZMUT
AD6
AD6
—
—
—
Gain
CAV0
—
—
—
2
VCO2
THRU
—
0
AD5
AD5
—
—
—
0
—
—
—
1
0
—
0
AD4
AD4
—
—
—
0
—
—
—
—
0
—
0
AD3
AD3
—
—
—
—
—
—
—
—
0
—
DCOF
AD2
AD2
—
—
—
—
—
—
—
—
0
—
0
AD1
AD1
—
—
—
—
—
—
—
—
0
—
0
AD0
AD0
—
—
—
—
—
—
—
—
TXON
—
—
—
FMUT
—
—
—
—
—
—
—
—
TXOUT
—
—
—
LRWO
—
—
—
—
—
—
—
—
OUTL1
—
—
—
BSBST
—
—
—
—
—
—
—
—
OUTL0
—
—
—
BBSL
—
—
—
—
AS3
0.18ms
0.36ms
11.6ms
32768
CDROM
0
0
0
0
SL1
Gain
MDP1
0
CM3
AS2
0.09ms
0.18ms
5.8ms
16384
DOUT
Mute
DSPB
ON/OFF
DSPB
ON/OFF
0
0
SL0
Gain
MDP0
TB
CM2
AS1
0.05ms
0.09ms
2.9ms
8192
DOUT
ON/OFF
0
0
Mute
Mute
CPUSR
Gain
MDS1
TP
CM1
AS0
0.02ms
0.05ms
1.45ms
4096
WSEL
0
0
ATT
ATT
0
Gain
MDS0
Gain
CLVS
CM0
Command
Address
D3 D2 D1 D0
Data 1
D3 D2 D1 D0
Data 2
D3 D2 D1 D0
Data 3
D3 D2 D1 D0
Data 4
D3 D2 D1 D0
Data 5
D3 D2 D1 D0
Data 6
D3 D2 D1 D0
– 26 –
CXD2588Q/R
FOCUS SERVO OFF,
0V OUT
TRACKING GAIN UP
FILTER SELECT 1
TRACKING SERVO OFF
SLED SERVO OFF
SLED KICK LEVEL
(±1 × basic value) (Default)
KRAM DATA
($3400XX to $344fXX)
0
0
0
0
0
0
0
0
0
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
2
0 0 0 0
0 0 0 1
0 0 1 0
FOCUS
CONTROL
TRACKING
CONTROL
TRACKING
MODE
Register
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Register
Command
3 SELECT
Address
D23 to D20
0 0 1 1
0 0 1 1 0 1 0 0 0 See "Coefficient ROM Preset Values Table".
0 0 0 0 — — — — — — — —
—
— — — — — — —
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D0 D0
Address 1
D23 to D20 D19 D18 D17 D16
Address 2
D15 D14 D13 D12
Address 3
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D0 D0
§1-3. CPU Command Presets
Command Preset Table ($0X to 34X)
—: Don’t care
– 27 –
CXD2588Q/R
Command Preset Table ($34FX to 3FX)
0 0 1 1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
FOCUS BIAS LIMIT
FOCUS BIAS DATA
TRVSC DATA
FOCUS SEARCH SPEED/
VOLTAGE AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE AUTO GAIN
FZSL/SLED MOVE/
Voltage/AUTO GAIN
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
SERIAL DATA READ
MODE/SELECT
FOCUS BIAS
Operation for MIRR/
DFCT/FOK
TZC/COUT
BOTTOM/MIRR
SLED FILTER
3
0 0 1 1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Filter
Others
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELECT
Register
Command
Address 1
D23 to D20 D19 D18 D17 D16
Address 2
D15 D14 D13 D12
Data 1
D11 D10 D9 D8
Data 2
D7 D6 D5 D4
Data 3
D3 D2 D1 D0
Address
D23 to D20 D19 D18 D17 D16
Data 1
D15 D14 D13 D12
Data 2
D11 D10 D9 D8
Data 3
D7 D6 D5 D4
Data 4
D3 D2 D1 D0
—: Don’t care
– 28 –
CXD2588Q/R
Reset Initialization
Register
4
5
6
7
8
9
A
B
C
D
E
Auto sequence
Blind (A, E),
Overflow (C)
Brake (B)
KICK (D)
Auto sequence (N)
track jump
count setting
MODE
specification
Function
specification
Audio CTRL
Serial bus
CTRL
Spindle servo
coefficient setting
CLV CTRL
CLV mode
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
1
0
0
0
1
1
0
0
0
1
0
0
0
0
—
—
—
0
0
0
0
0
—
1
0
—
—
—
0
0
0
0
1
—
1
0
—
—
—
0
0
0
0
0
—
1
0
—
—
—
1
0
0
0
0
—
0
0
—
—
—
0
0
0
0
0
—
0
0
—
—
—
0
0
0
1
0
—
0
0
—
—
—
0
1
0
0
0
—
0
0
—
—
—
0
0
0
0
0
—
0
0
—
—
—
0
0
0
0
—
—
—
0
—
—
—
0
0
0
0
—
—
—
0
—
—
—
0
0
0
0
—
—
—
0
—
—
—
0
0
0
0
—
—
—
0
—
—
—
—
0
0
0
—
—
—
—
—
—
—
—
0
0
0
—
—
—
—
—
—
—
—
0
0
0
—
—
—
—
—
—
—
—
0
0
0
—
—
—
—
—
—
—
—
0
—
0
—
—
—
—
—
—
—
—
0
—
0
—
—
—
—
—
—
—
—
0
—
0
—
—
—
—
—
—
—
—
0
—
0
—
—
—
—
Command
Address
D3 D2 D1 D0
Data 1
D3 D2 D1 D0
Data 2
D3 D2 D1 D0
Data 3
D3 D2 D1 D0
Data 4
D3 D2 D1 D0
Data 5
D3 D2 D1 D0
Data 6
D3 D2 D1 D0
– 29 –
CXD2588Q/R
<Coefficient ROM Preset Values Table (1)>
ADDRESS
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix
∗
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
DATA CONTENTS
∗
Fix indicates that normal preset values should be used.
– 30 –
CXD2588Q/R
<Coefficient ROM Preset Values Table (2)>
ADDRESS
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.)
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is a accessed with THSK = 1.)
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
DATA CONTENTS
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