Sony CXD2586R-1, CXD2586R Datasheet
CXD2586R/-1
For the availability of this product, please contact the sales office.
CD Digital Signal Processor with Built-in Digital Servo and DAC
Description
The CXD2586R/-1 is a digital signal processor LSI
for CD players. This LSI incorporates the digital
servo, digital filter and 1-bit DAC.
Features
• All digital signal processing during playback is
performed with a single chip
• Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor Block
• Playback mode which supports CAV (Constant
Angular Velocity)
• Frame jitter free
• Half-speed to octuple-speed continuous playback
possible with a low external clock (only CXD2586R-1
supports up to octuple speed)
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports normal-speed, double-speed, quadruple-
speed, sextuple-speed and octuple-speed playback
(only CXD2586R-1)
• Wide frame jitter margin (±28 frames) due to a
built-in 32K RAM
• The bit clock, which strobes the EFM signal, is
generated by the digital PLL
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
• Octuple-speed (only CXD2586R-1), sextuple-speed,
quadruple-speed and double-speed playback (digital
signal processor and digital servo blocks)
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub Q data error detection
• Digital spindle servo (with oversampling filter)
• 16-bit traverse counter
• Asymmetry compensation circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
Digital Servo Block
• Microcomputer software-based flexible servo control
• Servo error signal, offset cancel function
• Servo loop, auto gain control function
• E:F balance, focus bias adjustment function
Digital Filters (DAC and LPF blocks)
• Low-pass filter for DAC
• Digital de-emphasis
• Digital attenuation
• 4fs oversampling filter
• Adopts secondary ∆∑ noise shaper
• LPF for DAC analog output
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage VDD –0.3 to +7.0 V
• Input voltage VI –0.3 to +7.0 V
• Output voltage VO –0.3 to +7.0 V
• Storage temperature Tstg –40 to +125 °C
• Supply voltage difference VSS – AVSS –0.3 to +0.3 V
Recommended Operating Conditions
• Supply voltage
• Operating temperature
∗
The VDD (min.) for the CXD2586R/-1 varies according
to the playback speed and built-in VCO selection. The
VDD (min.) is 4.5V when high-speed VCO and
quadruple-speed playback are selected (variable pitch
off). The VDD (min.) for the CXD2586R/-1 under
various conditions are as shown in the following table.
Playback
speed
× 8
(only CXD2586R-1)
× 6
× 4
∗1
× 2
× 2
∗2
× 1
× 1
—: Dashes indicate that there is no assurance of the
processor operating. All values are for variable pitch off.
∗1
When the internal operation of the LSI is set to normalspeed playback and the operating clock of the signal
processor is doubled, double-speed playback results.
∗2
When the internal operation of the LSI is set to doublespeed mode and the crystal oscillating frequency is
halved in low power consumption mode, normal-speed
playback results.
– 1 –
144 pin LQFP (Plastic)
(VSS – 0.3V to VDD +0.3V)
VDD – AVDD –0.3 to +0.3 V
VDD (min.) [V]
VCO1 high
speed
4.75
4.50
4.50
4.00
3.40
3.40
3.40
VCO1 normal
speed
4.00
3.40
3.40
—
—
—
—
E95Y01A65-ST
DAC
block
—
—
—
—
—
—
4.50
Block Diagram
CXD2586R/-1
MCKO
MCLK
VPCO1, 2
VCKI
FSTO
C4M
C16M
PDO
VCOI
VCOO
PCO
FILI
FILO
CLTV
RFAC
ASYI
ASYO
ASYE
WFCK
SCOR
73
74
4, 5
135
76
77
78
134
128
127
10
12
14
15
19
83
84
XTLO
52
53
XTLI
VPCO1
4
VPCO2
105
5
ACDT
72
XTSL
62
DTS1
63
DTS2
64
DTS3
65
DTS4
66
DTS5
67
DTS6
68
DTS7
PCMDI
25
27
BCKI
23
LRCKI
DAC block
58
AOUT1
Clock
Generator
4fs Digital Filter
LPF
+
1 bit DAC
LPF
57
56
47
48
49
AIN1
LOUT1
AOUT2
AIN2
LOUT2
32K RAM
Priority
encoder
Peak
detector
processor
Serial/parallel
20
PSSL
42 to 31,
29, 28,
26, 24
82
MUTE
DA01 to DA16
8
Address
generator
D/A
data
processor
9
8
7
∗
Digital PLL
Vari-Pitch
double speed
MUX
EFM
Demodulator
Sync
protector
Timing
Generator1
Register
EXCK
SBSO
SQCK
SQSO
MON
FSW
MDP
MDS
PWMI
VCTL
V16M
RFDC
CE
TE
SE
FE
VC
108
107
110
106
136
142
143
144
111
86
85
88
87
Subcode
P to W
processor
80
2
2
2
2
2
2
DOUT
79
MD2
96
DATA
98
CLOK
XLAT
97
SENS
89
COUT
99
MIRR
102
DFCT
103
FOK
104
114, 117
116, 115
118, 121
120, 119
122, 125
124, 123
SFDR, SFON
SRDR, SRON
TFDR, TFON
TRDR, TRON
FFDR, FFON
FRDR, FRON
Digital out
Subcode Q
processor
Error
corrector
CLV
processor
Noise
Shaper
6
OSC
Signal processor block
18-times
oversampling
filter
MIRR
DFCT
FOK
Timing
Generator2
Servo
Interface
CPU interface
Servo
auto
sequencer
Servo block
SERVO DSP
OpAmp
1
AnaSw
A/D
CONVERTER
2
FOCUS SERVO
TRACKING SERVO
SLED SERVO
3
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING PWM
GENERATOR
SLED PWM
GENERATOR
141
RFC
140
129 131 132
ADIO
TEST
TES2
18
TES3
101
126 130137 139
16
1
3
2
0
DD
DV
DD
DV
DD
DV
DD
AV
2
DD
AV
59
3
DD
AV
46
4
DD
AV
51
5
DD
AV
43
1
SS
DV
81
– 2 –
2
SS
DV
3
SS
DV
11
1
SS
AV
2
SS
AV
55
31
SS
AV
60
32
SS
AV
45
41
SS
AV
50
42
SS
AV
54
5
SS
AV
91
XRST
Pin Configuration
CXD2586R/-1
NC.
MDP
MDS
LOCK
SSTP
SFDR
SRON
SRDR
SFON
TFDR
TRON
TRDR
TFON
FFDR
FRON
FRDR
FFON
DV
VCOO
VCOI
TEST
DV
TES2
TES3
NC.
PDO
VCKI
V16M
AV
DD2
IGEN
AV
ADIO
RFC
RFDC
DD3
SS3
SS2
CE
TE
128
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
108
MON
107
FSW
106
PWMI
FOK
TESTA
104105
103
DFCT
102
MIRR
101
2
DD
DV
100
NC.
99
COUT
98
CLOK
97
XLAT
96
DATA
95
ATSK
94
DFSW
93
SCLK
92
DIRC
91
XRST
90
NC.
89
SENS
88
SQCK
87
SQSO
86
EXCK
85
SBSO
84
SCOR
83
WFCK
82
MUTE
81
2
SS
DV
80
DOUT
79
MD2
78
C16M
C4M
7677
FSTO
75
FSTI
74
MCLK
73
MCKO
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
XTSL
DAS1
DAS0
XWO
DTS7
DTS6
DTS5
DTS4
DTS3
DTS2
DTS1
NC.
AV
SS32
AVDD3
AOUT1
AIN1
LOUT1
SS31
AV
AV
SS5
XTLI
XTLO
DD5
AV
SS42
AV
LOUT2
AIN2
AOUT2
AV
DD4
AV
SS41
NC.
SS1
DV
DA01
DA02
DA03
DA04
DA05
DA06
DA11
34
DA10
35
DA09
36
DA08
DA07
6
FE
5
4
3
VC
VPCO2
VPCO1
VCTL
1
2
SE
7
FILO
9
10
8
FILI
PCO
11
CLTV
1
SS
AV
12
13
RFAC
14 15
BIAS
ASYI
16
ASYO
1
DD
AV
19
18
17
NC.
1
DD
DV
20
ASYE
21
PSSL
22
WDCK
23
LRCK
24
LRCKI
25
DA16
26
DA15
PCMDI
27 28
BCKI
29
DA14
30
DA13
313233
NC.
DA12
– 3 –
Pin Description
CXD2586R/-1
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol I/O Description
O
O
O
O
O
I
I
I
I
I
I
I
I
I
1, Z, 0
1, Z, 0
Analog
1, Z, 0
1, 0
Sled error signal input.
Focus error signal input.
Center voltage input.
Wide-band EFM PLL VCO2 charge pump output.
Wide-band EFM PLL VCO2 charge pump output.
Wide-band EFM PLL VCO2 control voltage input.
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
Master PLL charge pump output.
Master VCO control voltage input.
Analog GND.
EFM signal input.
Asymmetry circuit constant current input.
Asymmetry comparator voltage input.
EFM full-swing output (low = VSS, high = VDD).
SE
FE
VC
VPCO1
VPCO2
VCTL
FILO
FILI
PCO
CLTV
AVSS1
RFAC
BIAS
ASYI
ASYO
16
18
19
20
21
22
23
24
25
26
27
28
29
31
32
AVDD1
DVDD1
ASYE
PSSL
WDCK
LRCK
LRCKI
DA16
PCMDI
DA15
BCKI
DA14
DA13
DA12
DA11
Analog power supply.
Digital power supply.
I
I
O
1, 0
O
1, 0
I
O
1, 0
I
O
1, 0
I
O
1, 0
O
1, 0
O
1, 0
O
1, 0
Asymmetry circuit on/off (low = off, high = on).
Audio data output mode switching input (low = serial, high = parallel).
D/A interface for 48-bit slot. Word clock f = 2Fs.
D/A interface for 48-bit slot. LR clock f = Fs.
LR clock input to DAC (48-bit slot).
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's
complement, MSB first) when PSSL = 0.
Audio data input to DAC (48-bit slot).
DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.
Bit clock input to DAC (48-bit slot).
DA14 output when PSSL = 1, 64-bit slot serial data output (two's
complement, LSB first) when PSSL = 0.
DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0.
DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0.
DA11 output when PSSL = 1, GTOP output when PSSL = 0.
33
34
35
36
DA10
DA09
DA08
DA07
O
1, 0
O
1, 0
O
1, 0
O
1, 0
DA10 output when PSSL = 1, XUGF output when PSSL = 0.
DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
DA08 output when PSSL = 1, GFS output when PSSL = 0.
DA07 output when PSSL = 1, RFCK output when PSSL = 0.
– 4 –
CXD2586R/-1
Pin
No.
37
38
39
40
41
42
43
45
46
47
48
49
50
51
52
Symbol I/O Description
O
O
O
O
O
O
O
I
O
O
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Analog
Analog
1, 0
DA06 output when PSSL = 1, C2PO output when PSSL = 0.
DA05 output when PSSL = 1, XRAOF output when PSSL = 0.
DA04 output when PSSL = 1, MNT3 output when PSSL = 0.
DA03 output when PSSL = 1, MNT2 output when PSSL = 0.
DA02 output when PSSL = 1, MNT1 output when PSSL = 0.
DA01 output when PSSL = 1, MNT0 output when PSSL = 0.
Digital GND.
Analog GND.
Analog power supply.
Channel 2 analog output.
Channel 2 analog input.
Channel 2 LINE output.
Analog GND.
Master clock power supply.
Master clock 33.8688MHz crystal oscillation circuit output.
DA06
DA05
DA04
DA03
DA02
DA01
DVSS1
AVSS41
AVDD4
AOUT2
AIN2
LOUT2
AVSS42
AVDD5
XTLO
53
54
55
56
57
58
59
60
62
63
64
65
66
67
68
69
70
XTLI
AVSS5
AVSS31
LOUT1
AIN1
AOUT1
AVDD3
AVSS32
DTS1
DTS2
DTS3
DTS4
DTS5
DTS6
DTS7
XWO
DAS0
I
O
I
O
I
I
I
I
I
Analog
Analog
Master clock 33.8688MHz crystal oscillation circuit output.
Master clock GND.
Analog GND.
Channel 1 LINE output pin.
Channel 1 analog input pin.
Channel 1 analog output pin.
Analog power supply.
Analog GND.
DAC test pin. Normally fixed to high.
DAC test pin. Normally fixed to high.
DAC test pin. Leave this open.
DAC test pin. Leave this open
DAC test pin. Leave this open.
DAC test pin. Leave this open.
DAC test pin. Normally fixed to low.
DAC sync window open input. Normally high, window open when low.
DAC test pin. Normally fixed to low.
71
72
73
74
75
DAS1
XTSL
MCKO
MCLK
FSTI
I
I
O
1, 0
I
I
DAC test pin. Normally fixed to low.
Crystal selection input.
DSP clock output.
DSP clock input.
2/3 frequency division input for MCLK pin.
– 5 –
CXD2586R/-1
Pin
No.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
91
Symbol I/O Description
FSTO
C4M
C16M
MD2
DOUT
DVSS2
MUTE
WFCK
SCOR
SBSO
EXCK
SQSO
SQCK
SENS
XRST
O
1, 0
O
1, 0
O
1, 0
I
O
1, 0
I
O
1, 0
O
1, 0
O
1, 0
I
O
1, 0
I
O
1, 0
I
2/3 frequency division output for MCLK pin. Does not change with variable pitch.
1/4 frequency division output for MCLK pin. Changes with variable pitch.
16.9344MHz output. Changes simultaneously with variable pitch.
Digital Out on/off control. (low: off, high: on)
Digital Out output pin.
Digital GND.
Mute (low: off, high: on)
WFCK (Write Flame Clock) output.
Outputs a high signal when either subcode sync S0 or S1 is detected.
Sub P to W serial output.
SBSO readout clock input.
Sub Q 80-bit and PCM peak and level data 16-bit output.
SQSO readout clock input.
SENS output to CPU.
System reset. Reset when low.
92
93
94
95
96
97
98
99
101
102
103
104
105
106
107
108
110
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
COUT
DVDD2
MIRR
DFCT
FOK
TESTA
PWMI
FSW
MON
MDP
I
I
I
I
I
I
I
O
1, 0
Used during 1-track jumps.
SENS serial data readout clock input.
DFCT switching pin. High: DFCT countermeasure circuit off.
Anti-shock pin.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
Track count signal output.
Digital power supply.
O
1, 0
O
1, 0
O
1, 0
Mirror signal output.
Defect signal output.
Focus OK signal output.
Test pin. Not connected.
I
O
Z, 0
O
1, 0
O
1, 0
Spindle motor external pin input.
Spindle motor output filter switching output.
Spindle motor on/off control output.
Spindle motor servo control output.
111
112
113
114
115
MDS
LOCK
SSTP
SFDR
SRON
O
1, 0
O
1, 0
I
O
1, 0
O
1, 0
Spindle motor servo control output.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low.
Disc innermost track detection signal input.
Sled drive output.
Sled drive output.
– 6 –
CXD2586R/-1
Pin
No.
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
Symbol I/O Description
O
SRDR
SFON
TFDR
TRON
TRDR
TFON
FFDR
FRON
FRDR
FFON
DVDD3
VCOO
VCOI
TEST
DVSS3
1, 0
O
1, 0
O
1, 0
O
1, 0
O
1, 0
O
1, 0
O
1, 0
O
1, 0
O
1, 0
O
1, 0
Sled drive output.
Sled drive output.
Tracking drive output.
Tracking drive output.
Tracking drive output.
Tracking drive output.
Focus drive output.
Focus drive output.
Focus drive output.
Focus drive output.
Digital power supply.
O
1, 0
I
I
Analog EFM PLL oscillation circuit output.
Analog EFM PLL oscillation circuit input. flock = 8.6436MHz.
Test pin. Normally fixed to low.
Digital GND.
TES2
131
TES3
132
PDO
134
VCKI
135
V16M
136
AVDD2
137
IGEN
138
AVSS2
139
ADIO
140
RFC
141
RFDC
142
CE
143
TE
144
∗
In the 144-pin LQFP, the following pins are NC:
I
I
O
1, Z, 0
I
O
1, 0
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Analog EFM PLL charge pump output.
Variable pitch clock input from the external VCO. fcenter = 16.9344MHz.
Wide-band EFM PLL VCO2 oscillation output.
Analog power supply.
I
Operational amplifier current source reference resistance connection.
Analog GND.
O
I
I
I
I
Operational amplifier output.
RF signal LPF time constant capacitor connection.
RF signal input.
Center servo analog input.
Tracking error signal input.
Pins 17, 30, 44, 61, 90, 100, 109, and 133
Notes) • The 64-bit slot is an LSB first, two's complement output. The 48-bit slot is an MSB first, two's
complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the negative pulse for the frame sync obtained from the EFM signal. It is the signal before
sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
– 7 –
CXD2586R/-1
Electrical Characteristics
1. DC Characteristics (VDD = AVDD = 5.0V ± 10%, Vss = AVss = 0V, Topr = –20 to +75°C)
Item
High level input voltage
Input voltage (1)
Low level input voltage
High level input voltage
Input voltage (2)
Low level input voltage
Input voltage (3)
Input voltage
High level output voltage
Output voltage (1)
Low level output voltage
High level output voltage
Output voltage (2)
Low level output voltage
Output voltage (1)
Low level output voltage
High level output voltage
Output voltage (4)
Low level output voltage
High level output voltage
Output voltage (5)
Low level output voltage
Input leak current (1)
Input leak current (2)
Input leak current (3)
Tri-state pin output leak current
VIH (1)
VIL (1)
VIH (2)
VIL (2)
VIN (3)
VOH (1)
VOL (1)
VOH (2)
VOL (2)
VOL (3)
VOH (4)
VOL (4)
VOH (5)
VOL (5)
ILI (1)
ILI (2)
ILI (3)
ILO
Conditions Min. Typ. Max. Unit
0.7VDD
0.3VDD
0.8VDD
Schmitt input
0.2VDD
Analog input
IOH = –4mA
IOL = 4mA
IOH = –2mA
IOL = 4mA
IOL = 4mA
IOH = –0.28mA
IOL = 0.36mA
IOH = –2mA
IOL = 8mA
VI = 0 to 5.5V
VI = 1.5 to 3.5V
VI = 0 to 5.0V
VO = 0 to 5.5V
Vss
VDD – 0.8
0
VDD – 0.8
0
0
VDD – 0.5
0
VDD – 0.5
0
–10
–20
–40
–5
VDD
VDD
0.4
VDD
0.4
0.4
VDD
0.4
VDD
0.4
10
20
600
5
Applicable pins
V
∗
1
V
V
∗
2
V
∗
3, 11, 12
V
V
∗
4
V
V
∗
5
V
∗
6
V
V
∗
7
V
V
∗
13
V
∗
µA
1, 2, 3, 12
∗
µA
8
∗
µA
9
∗
µA
10
Applicable pins
∗1
XTSL, DATA, XLAT, MD2, PSSL, TEST, TES2, TES3, DFSW, DIRC, SSTP, ATSK, BCKI, LRCKI, PCMDI,
DTS1, DTS2, DTS7, DAS0, DAS1, XWO, PWMI
∗2
CLOK, XRST, EXCK, SQCK, MUTE, VCKI, ASYE, FSTI, SCLK, MCLK
∗3
CLTV, FILI, RFAC, ASYI, RFDC, TE, SE, FE, VC, VCTL
∗4
MDP, PDO, PCO, VPCO1, VPCO2
∗5
ASYO, DOUT, FSTO, C4M, C16M, SBSO, SQSO, SCOR, MON, LOCK, WDCK, SENS, MDS, DA01 to
DA16, LRCK, WFCK, FOK, COUT, MIRR, DFCT, FFON, FRDR, FRON, FFDR, TFON, TRDR, TRON,
TFDR, SFON, SRDR, SRON, SFDR, MCKO, V16M
∗6
FSW
∗7
FILO
∗8
TE, SE, FE, VC
∗9
RFDC
∗10
SENS, MDS, MDP, FSW, PDO, PCO, VPCO1, VPCO2
∗11
RFC
∗12
AIN1, AIN2
∗13
AOUT1, AOUT2, LOUT1, LOUT2
– 8 –
2. AC Characteristics
(1) XTLI pin, VCOI pin
(a) When using self-excited oscillation
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ±10%)
Item Symbol Min. Typ. Max. Unit
CXD2586R/-1
Oscillation frequency
fMAX 7 34 MHz
(b) When inputting pulses to XTLI and VCOI pins
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ±10%)
Item Symbol Min. Typ. Max. Unit
High level pulse
width
Low level pulse
width
Pulse cycle
tWHX
tWLX
tCX
13 500
13 500
26 1000
Input high level VIHX VDD – 1.0
Input low level VILX 0.8
Rise time,
fall time
tR, tF
tCX
10
ns
ns
ns
V
V
ns
tWHX
XTLI
tR tF
tWLX
IHX
V
IHX × 0.9
V
V
DD/2
VIHX × 0.1
VILX
(c) When inputting sine waves to XTLI and VCOI pins via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ±10%)
Item Symbol Min. Typ. Max. Unit
Input amplitude VI 2.0 VDD + 0.3 Vp-p
– 9 –
(2) CLOK, DATA, XLAT, SQCK, and EXCK pins
(VDD = AVDD = 5.0V ±10%, VSS = AVSS = 0V, Topr = –20 to +75˚C)
Item Symbol Min. Typ. Max. Unit
CXD2586R/-1
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK SQCK frequency
EXCK SQCK pulse width
CLOK
DATA
XLAT
EXCK
SQCK
tSU
fCK
tWCK
tSU
tH
tD
tWL
fT
tWT
1/fCK
tWCK tWCK
tH
tWT tWT
1/fT
750
300
300
300
750
750
0.65
MHz
ns
ns
ns
ns
ns
0.65
MHz
ns
tD
tWL
SBSO
SQSO
tSU
tH
– 10 –
(3) SCLK pin
CXD2586R/-1
XLAT
tSPWtDLS
SCLK
Serial Read Out Data
(SENS)
1/fSCLK
MSB LSB
•••
•••
Item Symbol Min. Typ. Max. Unit
SCLK frequency
SCLK pulse width
Delay time
fSCLK
tSPW
tDLS
500
15
1 MHz
ns
µs
(4) COUT, MIRR and DFCT pins
Operating frequency (VDD = AVDD = 5.0V ±10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit
COUT maximum operating frequency
MIRR maximum operating frequency
DFCT maximum operating frequency
fCOUT
fMIRR
fDFCTH
40
40
5
kHz
kHz
kHz
Conditions
∗1
∗2
∗3
∗1
When using a high-speed traverse TZC.
∗2
B
A
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.6 to A1.3V
B
• = less than 25%
A + B
∗3
During complete RF signal omission.
When settings related to DFCT signal generation are Typ.
– 11 –
(5) BCKI, LRCKI and PCMDI pins (VDD = 5.0V ±10%, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit
CXD2586R/-1
Input BCKI frequency
Input BCKI pulse width
Input data setup time
Input data hold time
Input LRCK setup time
Input LRCK hold time
BCKI
PCMDI
tBCK
tWIB
tIDS
tIDH
tILRH
tILRS
100
10
15
10
15
tWIB tWIB
tIDHtIDS
tILRH
4.5 MHz
ns
50%
tILRS
LRCKI
(6) AOUT1, AOUT2, LOUT1 and LOUT2 pins
(VDD = AVDD =5.0V ±5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit Applicable pins
Output voltage (1)
Output voltage (2)
Load resistance
∗
When a sine wave of 1kHz and 0dB is output.
VOUT (1)
VOUT (2)
RL
0.1VDD
∗
VSS
10
Applicable pins
∗1
AOUT1, AOUT2
∗2
LOUT1, LOUT2
0.9VDD
VDD
∗
V
V
kΩ
∗1
∗2
∗1, ∗2
– 12 –
CXD2586R/-1
DAC Analog Characteristics
Measurement conditions
(Ta = 25°C, VDD = 5.0V, FS = 44.1kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, master clock = 768fs)
Item
S/N ratio
THD + N
Dynamic range
Channel separation
Output level
Difference in gain between channels
∗1
Using "A" weighting filter
∗2
–60dB, 1kHz input
Typ.
93
0.01
91
91
1.31
0.1
Unit
dB
%
dB
dB
V (rms)
dB
Remarks
(EIAJ)
(EIAJ)
(EIAJ)
(EIAJ)
The analog characteristics measurement circuit is shown below.
12k
AIN1
58
57
56
12k 12k
150p
47µ
680p
100k
AOUT1
LOUT1
∗1
∗1, ∗2
SHIBASOKU (AM51A)
Audio Analyzer
TEST DISK
LPF external circuit diagram
AOUT1
AIN1
DATA
CXD2586
Fs = 44.1kHz
LOUT1
AOUT2
AIN2
LOUT2
Audio Circuit
Block diagram of analog characteristics measurement
SHIBASOKU (AM51A)768fs
Analog
1ch
Audio Analyzer
2ch
– 13 –
CXD2586R/-1
Contents
[1] CPU Interface
§1-1. CPU Interface Timing ...................................................................................................................... 15
§1-2. CPU Interface Command Table ...................................................................................................... 15
§1-3. CPU Command Presets .................................................................................................................. 25
§1-4. Description of SENS Signals ........................................................................................................... 30
[2] Subcode Interface
§2-1. P to W Subcode Readout ................................................................................................................ 57
§2-2. 80-bit Sub Q Readout ...................................................................................................................... 57
[3] Description of Modes
§3-1. CLV-N Mode .................................................................................................................................... 63
§3-2. CLV-W Mode ................................................................................................................................... 63
§3-3. CAV-W Mode ................................................................................................................................... 63
[4] Description of Other Functions
§4-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................. 65
§4-2. Frame Sync Protection .................................................................................................................... 67
§4-3. Error Correction ............................................................................................................................... 67
§4-4. DA Interface ..................................................................................................................................... 68
§4-5. Digital Out ........................................................................................................................................ 71
§4-6. Servo Auto Sequence ...................................................................................................................... 72
§4-7. Digital CLV ....................................................................................................................................... 80
§4-8. Playback Speed ............................................................................................................................... 81
§4-9. DAC Block Playback Speed ............................................................................................................ 82
§4-10. DAC Block Input Timing .................................................................................................................. 82
§4-11. CXD2586R/-1 Clock System ........................................................................................................... 84
[5] Description of Servo Signal Processing-System Functions and Commands
§5-1. General Description of the Servo Signal Processing System .......................................................... 85
§5-2. Digital Servo Block Master Clock (MCK) ......................................................................................... 86
§5-3. AVRG Measurement and Compensation ........................................................................................ 86
§5-4. E:F Balance Adjustment Function ................................................................................................... 88
§5-5. FCS Bias Adjustment Function ........................................................................................................ 88
§5-6. AGCNTL Function ........................................................................................................................... 90
§5-7. FCS Servo and FCS Search ........................................................................................................... 92
§5-8. TRK and SLD Servo Control ........................................................................................................... 93
§5-9. MIRR and DFCT Signal Generation ................................................................................................ 94
§5-10. DFCT Countermeasure Circuit ........................................................................................................ 95
§5-11. Anti-Shock Circuit ............................................................................................................................ 95
§5-12. Brake Circuit .................................................................................................................................... 96
§5-13. COUT Signal ................................................................................................................................... 97
§5-14. Serial Readout Circuit ...................................................................................................................... 97
§5-15. Writing the Coefficient RAM ............................................................................................................ 98
§5-16. PWM Output .................................................................................................................................... 98
§5-17. DIRC Input Pin ............................................................................................................................... 100
§5-18. Servo Status Changes Produced by the LOCK Signal .................................................................. 101
§5-19. Description of Commands and Data Sets ..................................................................................... 101
§5-20. List of Servo Filter Coefficients ...................................................................................................... 113
§5-21. FILTER Composition ..................................................................................................................... 115
§5-22. TRACKING and FOCUS Frequency Response ............................................................................ 122
[6] Application Circuit
§6-1. Application Circuit .......................................................................................................................... 123
Explanation of abbreviations AVRG: Average
AGCNTL: Automatic gain control
FCS: Focus
TRK: Tracking
SLD: Sled
DFCT: Defect
– 14 –
[1] CPU Interface
§1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK, and XLAT to set the modes.
The interface timing chart is shown below.
750ns or more
CLOK
CXD2586R/-1
DATA
XLAT
Registers
D18 D19 D20 D21 D22 D23
• The internal registers are initialized by a reset when XRST = 0.
§1-2. CPU Interface Command Table
Total bit length for each register
Register
0 to 2
3
4 to 6
7
Total bit length
8bit
8 to 24bit
16bit
20bit
750ns or more
Valid
8
9
A
B
C to D
E
24bit
20bit
28bit
20bit
16bit
20bit
– 15 –
FOCUS SERVO ON
(FOCUS GAIN
NORMAL)
FOCUS SERVO ON
(FOCUS GAIN
DOWN)
FOCUS SERVO OFF,
0V OUT
FOCUS SERVO OFF,
FOCUS SEARCH
VOLTAGE OUT
FOCUS SEARCH
VOLTAGE DOWN
FOCUS SEACH
VOLTAGE UP
ANTI SHOCK ON
ANTI SHOCK OFF
BRAKE ON
BRAKE OFF
TRACKING GAIN
NORMAL
TRACKING GAIN UP
TRACKING GAIN UP
CXD2586R/-1
—: Don’t care
FILTER SELECT 1
TRACKING GAIN UP
FILTER SELECT 2
Data 5
Data 4
Data 3
D0
D3 D2 D1
D4
D7 D6 D5
D11 D10 D9 D8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Data 2
Data 1
Address
Command Table ($0X to 1X)
Register Command
—
D14 D13 D12
—
D15
—
—
0
D18 D17 D16
1
D19
D23 to D20
—
—
—
—
—
1
1
—
—
—
—
0
—
—
0 0 0 0
FOCUS
CONTROL
0
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
—
—
—
—
—
1
1
—
—
—
—
—
0
—
1
—
1
—
0
—
—
0
—
0 0 0 1
TRACKING
CONTROL
1
0
—
—
1
—
1
—
—
0
—
—
—
—
—
—
– 16 –
TRACKING SERVO
OFF
TRACKING SERVO ON
FORWARD TRACK
JUMP
—
—
—
—
—
—
REVERSE TRACK
JUMP
SLED SERVO OFF
SLED SERVO ON
—
—
—
—
—
—
FORWARD SLED
MOVE
REVERSE SLED
MOVE
—
—
—
—
SLED KICK LEVEL
(±1 × basic value) (Default)
SLED KICK LEVEL
(±2 × basic value)
SLED KICK LEVEL
(±3 × basic value)
—
—
—
—
—
—
—: Don’t care
SLED KICK LEVEL
(±4 × basic value)
—
—
CXD2586R/-1
Data 5
Data 4
Data 3
Data 2
D3 D2 D1 D0
D6 D5 D4
D7
D10 D9 D8
D11
D13 D12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Data 5
—
—
—
—
Data 4
—
—
—
—
Data 3
—
—
—
—
Data 2
—
D3 D2 D1 D0
D6 D5 D4
D7
D10 D9 D8
D11
D13 D12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D15 D14
—
—
D17 D16
Data 1
Address
Command
Command Table ($2X to 3X)
Register
0
0
D19 D18
D23 to D20
—
—
—
—
—
1
0
0
1
—
—
0
—
0
—
1
—
1
—
0 0 1 0
TRACKING
MODE
2
—
—
—
1
0
1
0
1
—
—
—
—
Data 1
1
—
—
Address
Command
Register
—
D15 D14
0
0
D17 D16
0
0
D19 D18
D23 to D20
—
1
0
0
0
—
0
1
0
0
0 0 1 1
SELECT
3
—
1
1
0
0
– 17 –
Data 2
KRAM DATA (K00)
SLED INPUT GAIN
KRAM DATA (K01)
KD0
KD1
D2 D1 D0
KD2
SLED LOW BOOST FILTER A-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K05)
KD0
KD0
KD0
KD0
KD0
KD1
KD1
KD1
KD1
KD1
KD2
KD2
KD2
KD2
KD2
SLED OUTPUT GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K07)
SLED AUTO GAIN
KRAM DATA (K08)
KD0
KD0
KD0
KD1
KD1
KD1
KD2
KD2
KD2
FOCUS HIGH CUT FILTER A
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0C)
KD0
KD0
KD0
KD0
KD1
KD1
KD1
KD1
KD2
KD2
KD2
KD2
CXD2586R/-1
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
KD0
KD0
KD0
KD1
KD1
KD1
KD2
KD2
KD2
D3
Data 1
D6 D5 D4
D7
D9 D8
Address 4
D11 D10
Address 3
D15 to D12
Address 2
D19 to D16
KD3
KD4
KD5
KD6
KD7
0
0
0
0
KD3
KD4
KD5
KD6
KD7
1
0
0
0
KD3
KD4
KD5
KD6
KD7
0
1
0
0
KD3
KD4
KD5
KD6
KD7
1
1
0
0
KD3
KD4
KD5
KD6
KD7
0
0
1
0
KD3
KD4
KD5
KD6
KD7
1
0
1
0
KD3
KD4
KD5
KD6
KD7
0
1
1
0
KD3
KD4
KD5
KD6
KD7
1
1
1
0
KD3
KD4
KD5
KD6
KD7
0
0
0
1
0 0 0 0SELECT
0 1 0 0
KD3
KD4
KD5
KD6
KD7
1
0
0
1
KD3
KD4
KD5
KD6
KD7
0
1
0
1
KD3
KD4
KD5
KD6
KD7
1
1
0
1
KD3
KD4
KD5
KD6
KD7
0
0
1
1
KD3
KD4
KD5
KD6
KD7
1
0
1
1
KD3
KD4
KD5
KD6
KD7
0
1
1
1
KD3
KD4
KD5
KD6
KD7
1
1
1
1
Address 1
D23 to D20
Command
Command Table ($340X)
Register
3 0 0 1 1
– 18 –
KRAM DATA (K10)
FOCUS PHASE COMPENSATE FILTER B
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K14)
KD0
KD0
KD0
KD0
D1 D0
KD1
KD1
KD1
KD1
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
KRAM DATA (K18)
FIX
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K1A)
KD0
KD0
KD0
KD0
KD0
KD0
KD1
KD1
KD1
KD1
KD1
KD1
TRACKING HIGH CUT FILTER A
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KD0
KD0
KD0
KD0
KD0
KD1
KD1
KD1
KD1
KD1
CXD2586R/-1
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
KD0
KD1
D4 D3 D2
D8 D7 D6 D5
Address 4 Data 1 Data 2
D11 D10 D9
Address 3
D15 to D12
Address 2
D19 to D16
KD2
KD3
KD4
KD5
KD6
KD7
0
0
0
0
KD2
KD3
KD4
KD5
KD6
KD7
1
0
0
0
KD2
KD3
KD4
KD5
KD6
KD7
0
1
0
0
KD2
KD3
KD4
KD5
KD6
KD7
1
1
0
0
KD2
KD3
KD4
KD5
KD6
KD7
0
0
1
0
KD2
KD3
KD4
KD5
KD6
KD7
1
0
1
0
KD2
KD3
KD4
KD5
KD6
KD7
0
1
1
0
KD2
KD3
KD4
KD5
KD6
KD7
1
1
1
0
KD2
KD3
KD4
KD5
KD6
KD7
0
0
0
1
0 0 0 1
0 1 0 0
KD2
KD3
KD4
KD5
KD6
KD7
1
0
0
1
KD2
KD3
KD4
KD5
KD6
KD7
0
1
0
1
KD2
KD3
KD4
KD5
KD6
KD7
1
1
0
1
KD2
KD3
KD4
KD5
KD6
KD7
0
0
1
1
KD2
KD3
KD4
KD5
KD6
KD7
1
0
1
1
KD2
KD3
KD4
KD5
KD6
KD7
0
1
1
1
KD2
KD3
KD4
KD5
KD6
KD7
1
1
1
1
Address 1
D23 to D20
Command
Register
Command Table ($341X)
0 0 1 1
SELECT
3
– 19 –
KRAM DATA (K20)
TRACKING PHASE COMPENSATE FILTER A
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KD0
KD0
KD0
KD0
KD0
D1 D0
KD1
KD1
KD1
KD1
KD1
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KD0
KD0
KD0
KD0
KD0
KD0
KD1
KD1
KD1
KD1
KD1
KD1
CXD2586R/-1
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2F)
NOT USED
KD0
KD0
KD0
KD0
KD0
KD1
KD1
KD1
KD1
KD1
D5 D4 D3 D2
D8 D7 D6
Address 4 Data 1 Data 2
D11 D10 D9
Address 3
D15 to D12
Address 2
D19 to D16
KD2
KD3
KD4
KD5
KD6
KD7
0
0
0
0
KD2
KD3
KD4
KD5
KD6
KD7
1
0
0
0
KD2
KD3
KD4
KD5
KD6
KD7
0
1
0
0
KD2
KD3
KD4
KD5
KD6
KD7
1
1
0
0
KD2
KD3
KD4
KD5
KD6
KD7
0
0
1
0
KD2
KD3
KD4
KD5
KD6
KD7
1
0
1
0
KD2
KD3
KD4
KD5
KD6
KD7
0
1
1
0
KD2
KD3
KD4
KD5
KD6
KD7
1
1
1
0
KD2
KD3
KD4
KD5
KD6
KD7
0
0
0
1
0 0 1 0SELECT
0 1 0 0
KD2
KD3
KD4
KD5
KD6
KD7
1
0
0
1
KD2
KD3
KD4
KD5
KD6
KD7
0
1
0
1
KD2
KD3
KD4
KD5
KD6
KD7
1
1
0
1
KD2
KD3
KD4
KD5
KD6
KD7
0
0
1
1
KD2
KD3
KD4
KD5
KD6
KD7
1
0
1
1
KD2
KD3
KD4
KD5
KD6
KD7
0
1
1
1
KD2
KD3
KD4
KD5
KD6
KD7
1
1
1
1
Address 1
D23 to D20
Command
Command Table ($342X)
Register
0 0 1 1
3
– 20 –
KRAM DATA (K30)
FIX
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K32)
NOT USED
KD0
KD0
KD0
KD1
KD1
KD1
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
KD0
KD0
KD0
KD0
KD0
KD1
KD1
KD1
KD1
KD1
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD1
KD1
KD1
KD1
KD1
KD1
KD1
CXD2586R/-1
KRAM DATA (K3F)
NOT USED
KD0
KD1
D2 D1 D0
D6 D5 D4 D3
D9 D8 D7
Address 4 Data 1 Data 2
D11 D10
Address 3
D15 to D12
KD2
KD3
KD4
KD5
KD6
KD7
0
0
0
0
KD2
KD3
KD4
KD5
KD6
KD7
1
0
0
0
KD2
KD3
KD4
KD5
KD6
KD7
0
1
0
0
KD2
KD3
KD4
KD5
KD6
KD7
1
1
0
0
KD2
KD3
KD4
KD5
KD6
KD7
0
0
1
0
KD2
KD3
KD4
KD5
KD6
KD7
1
0
1
0
KD2
KD3
KD4
KD5
KD6
KD7
0
1
1
0
KD2
KD3
KD4
KD5
KD6
KD7
1
1
1
0
KD2
KD3
KD4
KD5
KD6
KD7
0
0
0
1
0 0 1 1SELECT
KD2
KD3
KD4
KD5
KD6
KD7
1
0
0
1
KD2
KD3
KD4
KD5
KD6
KD7
0
1
0
1
KD2
KD3
KD4
KD5
KD6
KD7
1
1
0
1
KD2
KD3
KD4
KD5
KD6
KD7
0
0
1
1
KD2
KD3
KD4
KD5
KD6
KD7
1
0
1
1
KD2
KD3
KD4
KD5
KD6
KD7
0
1
1
1
KD2
KD3
KD4
KD5
KD6
KD7
1
1
1
1
Address 2
D19 to D16
Address 1
D23 to D20
Command
Command Table ($343X)
Register
0 1 0 0
3 0 0 1 1
– 21 –
Data 2
KRAM DATA (K40)
TRACKING HOLD FILTER INPUT GAIN
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KD0
KD0
KD0
KD0
D1 D0
KD1
KD1
KD1
KD1
KD2
KD2
KD2
KD2
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K46)
NOT USED
KRAM DATA (K47)
NOT USED
KD0
KD0
KD0
KD0
KD1
KD1
KD1
KD1
KD2
KD2
KD2
KD2
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KD0
KD0
KD0
KD0
KD0
KD1
KD1
KD1
KD1
KD1
KD2
KD2
KD2
KD2
KD2
CXD2586R/-1
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4F)
NOT USED
KD0
KD0
KD0
KD1
KD1
KD1
KD2
KD2
KD2
D5 D4 D3 D2
D8 D7 D6
Address 4 Data 1
D11 D10 D9
Address 3
D15 to D12
Address 2
D19 to D16
KD3
KD4
KD5
KD6
KD7
0
0
0
0
KD3
KD4
KD5
KD6
KD7
1
0
0
0
KD3
KD4
KD5
KD6
KD7
0
1
0
0
KD3
KD4
KD5
KD6
KD7
1
1
0
0
KD3
KD4
KD5
KD6
KD7
0
0
1
0
KD3
KD4
KD5
KD6
KD7
1
0
1
0
KD3
KD4
KD5
KD6
KD7
0
1
1
0
KD3
KD4
KD5
KD6
KD7
1
1
1
0
KD3
KD4
KD5
KD6
KD7
0
0
0
1
0 1 0 0SELECT
0 1 0 0
KD3
KD4
KD5
KD6
KD7
1
0
0
1
KD3
KD4
KD5
KD6
KD7
0
1
0
1
KD3
KD4
KD5
KD6
KD7
1
1
0
1
KD3
KD4
KD5
KD6
KD7
0
0
1
1
KD3
KD4
KD5
KD6
KD7
1
0
1
1
KD3
KD4
KD5
KD6
KD7
0
1
1
1
KD3
KD4
KD5
KD6
KD7
1
1
1
1
Address 1
D23 to D20
Command
Command Table ($344X)
Register
0 0 1 1
3
– 22 –
FOCUS BIAS LIMIT
FOCUS BIAS DATA
TRVSC DATA
FOCUS SEARCH SPEED/
VOLTAGE/AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE/AUTO GAIN
FZSL/SLED MOVE/
Voltage/AUTO GAIN
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
SERIAL DATA READ
MODE/SELECT
FOCUS BIAS
Operation for MIRR/
DFCT/FOK
TZC for COUT SLCT
HPTZC (Default)
TZC for COUT SLCT
DTZC
CXD2586R/-1
Filter
—: Don’t care
Others
D0
Data 3
D3 D2 D1
D4
Data 2
D7 D6 D5
Data 1
D11 D10 D9 D8
Address 2
D14 D13 D12
D15
—
FBL1
FBL2
FBL3
FBL4
FBL5
FBL6
FBL7
FBL8
FBL9
0
1
1
1
1
1
0
—
FB1
FB2
FB3
FB4
FB5
FB6
FB7
FB8
FB9
1
0
1
1
1
1
0
TV0
TV1
TV2
TV3
TV4
TV5
TV6
TV7
TV8
TV9
0
0
1
1
1
1
0
Data 4
Data 3
Data 2
Data 1
D0
D3 D2 D1
D4
D7 D6 D5
D11 D10 D9 D8
D14 D13 D12
D15
FG0
FG1
FG2
FG3
FG4
FG5
FG6
FTZ
FS0
FS1
FS2
FS3
FS4
FS5
FT0
FT1
1
TG0
TG1
TG2
TG3
TG4
TG5
TG6
SFJP
TJ0
TJ1
TJ2
TJ3
TJ4
TJ5
DTZC
0
0
AGHT
AGHS
AGV2
AGV1
AGGT
AGGF
AGJ
AGS
SM0
SM1
SM2
SM3
SM4
SM5
FZSL
FZSH
1
TLC0
TLC1
TLC2
FLC1
TCLM
TBLM
LKSW
DFSW
AGT
AGF
RFLC
RFLM
FLC0
FLM
VCLC
VCLM
0
0
0
0
0
0
0
0
0
SD0
SD1
SD2
SD3
SD4
SD5
SD6
DAC
1
MTI0
INBK
SJHD
CEIT
TPS0
TPS1
FPS0
FPS1
TJD0
0
FBV0
FBV1
FBUP
FBSS
FBON
0
0
0
0
0
RINT
D1V1
D1V2
D2V1
D2V2
BTF
SFOX
MAX1
MAX2
SDF1
SDF2
SFO1
SFO2
1
Data 4
Data 3
Data 2
Data 1
D0
D3 D2 D1
D4
D7 D6 D5
D11 D10 D9 D8
D14 D13 D12
D15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
Data 4
Data 3
Data 2
Data 1
D0
D3 D2 D1
D4
D7 D6 D5
D11 D10 D9 D8
D14 D13 D12
D15
XT1D
MIRI
0
0
0
RFLP
TLCD
DFIS
T3UM
T3NM
T1UM
T1NM
F3DM
F3NM
F1DM
F1NM
0
COT2
AGHF
SRO0
SRO1
LPAS
0
ASFG
0
DRR0
DRR1
DRR2
0
XT2D
XT4D
AGG4
0
1
0
0
0
1
1
0
0 0 1 1
1
0
Address
D18 D17 D16
0
D19
Address 1
D23 to D20
Register Command
Command Table ($34FX to 3FX)
0
1
D18 D17 D16
0
D19
D23 to D20
1
1
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
Address
0 0 1 1
SELECT
3
0
1
D18 D17 D16
1
D19
D23 to D20
0
1
1
0 0 1 1
Address
1
1
D18 D17 D16
1
D19
D23 to D20
1
1
1
0 0 1 1
– 23 –
CXD2586R/-1
Data 4
Data 3
Data 2
D0
D3 D2 D1
D2 D1 D0
D1 D0 D3
D3 D2
—
—
—
—
0
0
0
LSSL
MT0
MT1
MT2
MT3
—
—
—
—
0
0
0
0
0
0
0
0
—
—
—
—
0
0
0
0
KF0
KF1
KF2
KF3
1
2
4
8
16
32
64
128
256
512
1024
2048
0
1
0
0
KSL0
KSL1
KSL2
KSL3
VCO
SEL2
SOCT
ASHS
SEL
VCO
PLM0
PLM1
PLM2
PLM3
0
0
ATT
DAC
DAC
EMP
0
FLFC
SUB
BiliGL
MAIN
BiliGL
AT1D0
AT1D1
AT1D2
AT1D3
AT1D4
AT1D5
AT1D6
AT1D7
SOC2
DADS
PCT2
PCT1
1
2
4
8
16
32
64
128
256
512
1024
2048
—
—
—
—
0
0
0
0
0
0
Gain
Gain
DCLV0
DCLV1
—
—
—
—
VP0
VP1
VP2
VP3
VP4
VP5
VP6
VP7
0
FCSW
Gain
CAV0
Gain
CAV1
VPON
LPWR
HIFC
VC2C
SFSL
ICAP
SPDC
EPWM
—: Don’t care
AT2D0
D1 D0
Data 6
AT2D2 AT2D1
D0 D3 D2
AT2D5 AT2D4 AT2D3
Data 5
D3 D2 D1
Data 4
Data 1
D2 D1 D0
D1 D0 D3
Address
D3 D2
Command
AS0
AS1
AS2
AS3
0
0
1
0
Auto sequence
TR0
TR1
TR2
TR3
1
0
1
0
Blind (A, E),
Overflow (C, G),
Brake (B)
SD0
SD1
SD2
SD3
0
1
1
0
Sled KICK,
KICK (F),
BRAKE (D)
4096
8192
DOUT
16384
DOUT
CD-
32768
1
1
1
0
Auto sequence
(N) track jump
count setting
DPLL
WSEL
ON/OFF
ASEQ
Mute-F
ON/OFF
Mute
DSPB
ON/OFF
ROM
DCLV
ON/OFF
0
1
0
0
0
0
1
1
MODE setting
Function
specification
ATT
Mute
4096
8192
0
16384
0
32768
0
1
0
1
Audio CTRL
1
1
0
1
Traverse monitor
Gain
MDS0
Gain
MDS1
Gain
MDP0
Gain
MDP1
0
0
1
1
counter setting
Spindle servo
coefficient setting
Gain
CLVS
TP
TB
DCLV
PWM MD
1
0
1
1
CLV CTRL
CM0
CM1
CM2
CM3
0
1
1
1
SPD MODE
Data 1 Data 2 Data 3
Address
Command
1 0 1 0 AT2D7 AT2D6
Audio CTRL
4
Command Table ($4X to EX)
Register
5
6
7
8
9
A
B
C
E
D
A
Register
– 24 –
—: Don’t care
CXD2586R/-1
Data 5
Data 4
Data 3
FOCUS SERVO OFF,
0V OUT
TRACKING GAIN UP
FILTER SELECT 1
—
—
—
—
—
D2 D1 D0
D3
D6 D5 D4
D7
D9 D8
D11 D10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRACKING SERVO OFF
SLED SERVO OFF
—
—
Data 5
—
—
—
—
Data 4
—
—
—
—
Data 3
—
—
(±1 + basic value) (Default)
SLED KICK LEVEL
D2 D0 D0
— — — —
D3
— — —
D6 D5 D4
D7
D9 D8
— — — —
D11 D10
Data 2
D2 D0 D0
D3
Data 1
D6 D5 D4
D7
D9 D8
Address 3
D11 D10
KRAM DATA
($3400XX to $344fXX)
—
—
—
D13 D12
Data 2
D15 D14
D17 D16
Data 1
D19 D18
Address
D23 to D20
Command
FOCUS
§1-3. CPU Command Presets
Command Preset Table ($0X to 34X)
Register
—
—
—
—
—
0
1
0
0
0
0
0
0
0 0 0 0
0 0 0 1
CONTROL
TRACKING
0
1
CONTROL
—
—
Data 2
—
—
0
Data 1
0
0
0
Address
0 0 1 0
TRACKING
MODE
2
D13 D12
D15 D14
D17 D16
D19 D18
D23 to D20
Command
Register
— — — —
0 0 —
0 0
0 0 1 1
D13 D12
Address 2
D15 D14
D17 D16
Address 1
D23 to D20 D19 D18
3 SELECT
0 0 See the coefficient preset values table.
0 0 1 1 0 1 0
– 25 –
FOCUS BIAS LIMIT
FOCUS BIAS DATA
TRVSC DATA
FOCUS SEARCH SPEED/
VOLTAGE AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE AUTO GAIN
FZSL/SLED MOVE/
Voltage/AUTO GAIN
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
SERIAL DATA READ
MODE/SELECT
FOCUS BIAS
Operation for MIRR/
DFCT/FOK
TZC for COUT SLCT
HPTZC (Default)
CXD2586R/-1
Filter
Others
—: Don’t care
Data 3
Data 2
Data 1
D2 D1 D0
D3
D6 D5 D4
D7
D9 D8
D11 D10
D2 D1 D0
D3
D6 D5 D4
D7
D9 D8
D11 D10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
Data 4
0
0
0
0
Data 3
0
0
0
0
Data 2
0
0
1
D2 D1 D0
D3
D6 D5 D4
D7
D9 D8
D11 D10
1
1
0
1
1
1
0
0
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data 4
0
0
1
0
data 3
1
0
0
0
Data 2
0
0
0
D2 D1 D0
D3
D6 D5 D4
D7
D9 D8
D11 D10
— —
Data 4
data 3
— — — — — — —
Data 2
— — — —
1
1
1
1
0
0
1
0
0 0 1 1
1
Data 1
1
1
0
0
1
0
Address
Address 2
D13 D12
1
1
D15 D14
0
0
D17 D16
1
Address 1
Command
Register
Command Preset Table ($34FX to 3FX)
0
D23 to D20 D19 D18
D13 D12
D15 D14
D17 D16
D23 to D20 D19 D18
0
1
0
1
0
1
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0 0 1 1
SELECT
3
D13 D12
Data 1
D15 D14
D17 D16
Address
D23 to D20 D19 D18
— — —
1 0 0
1
0 0 1 1
Data 1
Address
D13 D12
D15 D14
D17 D16
D23 to D20 D19 D18
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0 0 1 1
– 26 –
CXD2586R/-1
Data 4
Data 3
Data 2
D2 D1 D0
D1 D0 D3
D0 D3 D2
—
—
—
—
—
—
0
0
0
0
0
0
0
—
—
0
0
0
0
0
0
0
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
0
1
0
0
1
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
—
0
—
0
—
0
—
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
—
0
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—: Don’t care
Data 6
Data 5
D2 D1 D0
D1 D0 D3
D3 D2
1
1 1 1
1 1 1
1
D3 D2 D1
Data 1
D2 D1 D0
D0 D3
Address
D3 D2 D1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
1
1
1
1
Data 2 Data 3 Data 4
Address Data 1
1 0 1 0
Auto sequence
Blind (A, E),
Brake (B),
Overflow (C, G)
Sled KICK,
BRAKE (D),
KICK (F)
Auto sequence
4
Command Preset Table ($4X to EX)
Register Command
5
6
(N) track jump
count setting
MODE setting
7
8
Function
specification
9
– 27 –
Audio CTRL
Traverse monitor
A
B
counter setting
Spindle servo
coefficient setting
C
CLV CTRL
SPD MODE
E
D
Command
Audio CTRL
A
Register
<Coefficient ROM Preset Values Table (1)>
CXD2586R/-1
ADDRESS
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
DATA CONTENTS
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
∗
Fix
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
– 28 –
<Coefficient ROM Preset Values Table (2)>
CXD2586R/-1
ADDRESS
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
DATA CONTENTS
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
∗
Fix
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
∗
Fix indicates that normal preset values should be used.
– 29 –
§1-4. Description of SENS Signals
SENS output
CXD2586R/-1
Microcomputer serial register
(latching not required)
$0X
$1X
$2X
$38
$38
$30 to 37
$3A
$3B to 3F
$3904
$3908
$390C
$391C
$391D
$391F
$4X
ASEQ = 0 ASEQ = 1
Z
Z
Z
Z
Z
Z
Z
FBIAS Count STOP
Z
Z
Z
Z
Z
Z
Z
Z
FZC
AS
TZC
∗
AGOK
XAVEBSY
SSTP
SSTP
TE Avrg Reg.
FE Avrg Reg.
VC Avrg Reg.
TRVSC Reg.
FB Reg.
RFDC Avrg Reg.
XBUSY
Output data
length
—
—
—
—
∗
—
—
—
—
9 bit
9 bit
9 bit
9 bit
9 bit
8 bit
—
$5X
$6X
$AX
$BX
$CX
$EX
$7X, 8X, 9X,
DX, FX
∗
$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement.
Z
Z
GFS
COMP
COUT
OV64
Z
FOK
0
GFS
COMP
COUT
OV64
0
—
—
—
—
—
—
—
SSTP is output in all other cases.
– 30 –
Loading...