Sony CXD2508AR, CXD2508AQ Datasheet

CD Digital Signal Processor
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CXD2508AQ/AR
Description
The CXD2508AQ/AR is a digital signal processor for CD players and is equipped with built-in digital filters, no-sound data detection circuit, and 1-bit DAC.
Features
DSP block
Digital PLL
SEC strategy-based error correction
Subcode demodulation, CRC checking
Digital spindle servo
Servo auto sequencer
Asymmetry compensation circuit
Digital audio interface output
16K RAM
Double-speed playback capability
New microcomputer interface circuit
Digital filter, DAC block
Double-speed playback capability
Digital de-emphasis
Digital attenuation
No-sound data detection circuit
4 Fs oversampling filter
Secondary ∆∑ noise shaper
PWM-system pulse conversion output Recommended Operating Conditions
Supply voltage VDD
Operating temperature Note) VDD (min.) is varied by the playback speed and built-in
VCO in the CXD2508AQ/AR. 4.5V is the value using the VCO which generates the slower frequency in double­speed playback. The table below shows the VDD (min.) for each condition.
Note)
4.5 to 5.5V (double-speed playback)
3.5 to 5.5V (normal-speed playback)
3.4 to 5.5V (low power consumption or special playback mode)
Topr –20 (min.) 75 (max.) °C
80 pin QFP (Plastic)
80 pin QFP (Plastic)
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
Supply voltage VDD –0.3 to 7.0 V
Input voltage VI –0.3 to 7.0 V
Input voltage
Output voltage VO –0.3 to 7.0 V
Storage temperature
Supply voltage variation
CXD2508AQ
CXD2508AQ
CXD2508AQ
80 pin QFP (Plastic)
CXD2508AR
80 pin LQFP (Plastic)
VIN Vss–0.3V (min.) VDD+0.3 (max.) V
Tstg –40 to 125 °C
VSS–AVSS –0.3V (min.) +0.3V (max.) VDD–AVDD –0.3V (min.) +0.3V (max.)
Playback
speed
× 2 × 1
× 1
When the internal operation of the LSI is set to double­speed mode and the crystal oscillation frequency is halved, normal-speed playback results.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
VCO
high-speed
3.40 4.50 3.40
3.40
3.40 3.40 3.40
VDD (min.) [V]
VCO
normal-speed
3.50
DAC block
3.40
– 1 –
E94602A54-ST
Pin Configuration
DTS1
V
XTAI
DTS2 DTS3
65 66 67 68
DD
69 70 71 72
73
74 75 76 77 78 79 80
ZEROL
ZEROR
NLPWM
LPWM AVDD2 AVDD3
XTAO AVss3 AVss2
NRPWM
RPWM
64
EMPHI
WFCK
63
62
DOUT
EMPH
61
60
C4M
59
FSTT
58
MNT0
57
MNT1
56
MNT3
55
C2PO
XROF
53
54
CXD2508AQ
Vss
52
RFCK
51
GFS
50
XPCK
49
XUGF
48
GTOP
47
BCKI
46
BCK
45
PCMD
PCMDI
44
LRCKI
43
42
LRCK
41
WDCK
CXD2508AQ/AR
ASYE
40
ASYO
39
ASYI
38
BIAS
37
RF
36
AVDD1
35
CLTV
34
AVss1
33
VDD
32
PCO
31
FILI
30
FILO
29
TEST
28
LOCK
27
MDS
26
MDP
25
EMPHI
WFCK
ZEROL
ZEROR
DTS1
V
NLPWM
LPWM AV
DD2
AVDD3
XTAI
XTAO AVss3 AVss2
NRPWM
RPWM
DTS2 DTS3
SCOR
SBSO
17
18
16
Vss
Vss
13
50
14
SEIN
RFCK
49
15
CNIN
GFS
48
DATO
XPCK
47
XLTO
6
5
7
MUTE
FSTT
57
SENS
56
8
XRST
MNT0
55
9
DATA
MNT1
54
10
XLAT
MNT3
53
12
11
CLOK
C2PO
XROF
52
51
CXD2508AR
2
1
SCOR
61 62 63
64
65
66
DD
67 68
69
70
71
72
73
74
75 76
77 78
79
80
3
SBSO
60
4
EXCK
EMPH
59
SQCK
SQSO
DOUT
58
C4M
CLKO
XUGF
46
SPOA
GTOP
45
19
BCKI
44
20
SPOB
BCK
43
21
XTSL
SPOC
PCMDI
42
22
XLON
LRCKI
PCMD
41
23
24
FOK
40 39 38
35
32
30 29 28
26
37 36
34 33
31
27
25 24
23 22 21
MON
LRCK WDCK ASYE ASYO ASYI BIAS RF AVdd1 CLTV AVss1 Vdd PCO FILI FILO TEST LOCK MDS MDP MON FOK
1
EXCK
2
SQSO
3
SQCK
4
MUTE
5
SENS
6
7
XRST
8
DATA
9
XLAT
10
CLOK
– 2 –
Vss
11
12
SEIN
13
CNIN
14
DATO
15
XLTO
16
CLKO
17
SPOA
18
SPOB
19
SPOC
20
XTSL
XLON
Block Diagram
63
EMPHI
LRCKI
PCMDI
BCKI
47
MUTE
BCK
PCMD
LRCK
WDCK
C2PO RFCK
MNT0 MNT1 MNT3
WFCK EMPH
62
GFS XUGF GTOP
43 45
46 44 42 41
52
58 57 56
64
51 49 48
54
CXD2508AQ/AR
ZEROR
ZEROL
XTAO
XTAI
65
66
74
73
NLPWM
69
LPWM
Digital Filter
+
1bit DAC
6
digital
OUT
digital
CLV
CPU
interface
SUB code Processor
error
corrector
D/A
Interface
16K RAM
EFM
demodulator
70 78 77
61
55 27 26
25 24
5 4 3
2 1
22 19 11 10
9 7
RPWM NRPWM
DOUT
XROF LOCK MDS MDP MON
SQCK SQSO EXCK SBSO SCOR XLON SPOA to C CLOK XLAT DATA SENS
Servo auto sequencer
23
FOK
13
SEIN
14
CNIN
XTSL
18
clock
generator
60
59
FSTT
C4M
36
RF
asymmetry
corrector
39
38
ASYI
ASYO
40
37
ASYE
BIAS
50
29
XPCK
digital
PLL
30
FILO
FILI
31
PCO
34
CLTV
Note) The pin numbers are for QFP. Refer to the Pin Description for those of LQFP.
– 3 –
17
16
15
CLKO
XLTO
DATO
Pin Description
CXD2508AQ/AR
Pin No.
RQ 79 80
10 11 12 13
1 2
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
11 12 13 14 15
Symbol
SCOR SBSO EXCK SQSO SQCK MUTE SENS XRST DATA XLAT CLOK VSS SEIN CNIN DATO
I/O
Outputs a high signal when either subcode sync S0 or S1 is detected.
O
Sub P to W serial output.
O
SBSO readout clock input.
I
Sub Q 80-bit serial output.
O
SQSO readout clock input.
I
High: mute; low: release
I
SENS output to CPU.
O
System reset. Reset when low.
I
Serial data input from CPU.
I
Latch input from CPU. Serial data is latched at the falling edge.
I
Serial data transfer clock input from CPU.
I
Description
GND. Sense input from SSP.
I
Track jump count signal input.
I
Serial data output to SSP.
O 14 15 16 17 18 19 20 21 22 23 24
25 26
27 28 29
16 17 18 19 20 21 22 23 24 25 26
27 28
29 30 31
XLTO CLKO SPOA SPOB SPOC XTSL XLON FOK MON MDP MDS
LOCK TEST
FILO FILI PCO
Serial data latch output to SSP. Latched at the falling edge.
O
Serial data transfer clock output to SSP.
O
Microcomputer extended interface (input A).
I
Microcomputer extended interface (input B).
I
Microcomputer extended interface (input C).
I
Crystal selection input. Low for 16.9344MHz; high for 33.8688MHz
I
Microcomputer extended interface (output).
O
Focus OK input. Used for SENS output and the servo auto sequencer.
I
Spindle motor on/off control output.
O
Spindle motor servo control.
O
Spindle motor servo control.
O
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
O
If GFS is low eight consecutive samples, this pin outputs low. TEST pin. Normally GND.
I
Master PLL (slave = digital PLL) filter output.
O
Master PLL filter input.
I
Master PLL charge pump output.
O 30 31 32
32 33 34
VDD AVSS1 CLTV
Digital power supply for DSP. Analog GND for DSP. Master PLL VCO control voltage input.
I
– 4 –
CXD2508AQ/AR
Pin No.
RQ
33
35
34
36
35
37
36
38
37
39
38
40
39
41
40
42
41
43
42
44
43
45
44
46
45
47
46
48
47
49
Symbol
AVDD1 RF BIAS ASYI ASYO ASYE WDCK LRCK LRCKI PCMD PCMDI BCK BCKI GTOP XUGF
I/O
Description
Analog power supply for DSP.
I
EFM signal input.
I
Constant current input of asymmetry compensation circuit.
I
Comparator voltage input of asymmetry compensation circuit.
O
EFM full-swing output (low = Vss, high = VDD).
I
Low: asymmetry compensation off; high: asymmetry compensation on.
O
D/A interface for 48-bit slot. Word clock (2Fs).
O
D/A interface for 48-bit slot. LR clock (Fs).
I
LR clock input for DAC. (48-bit slot)
O
D/A interface. Serial data (two's complement, MSB first).
I
Audio data input for DAC. (48-bit slot)
O
D/A interface. Bit clock.
I
Bit clock input for DAC. (48-bit slot)
O
GTOP output.
O
XUGF output. 48 49 50 51 52 53 54 55 56 57 58 59
60 61
62 63
50 51 52 53 54 55 56 57 58 59 60 61
62 63
64 65
XPCK GFS RFCK VSS C2PO XROF MNT3 MNT1 MNT0 FSTT C4M DOUT
EMPH EMPHI
WFCK ZEROL
O
XPLCK output.
O
GFS output.
O
RFCK output.
GND.
O
C2PO output.
O
XRAOF output.
O
MNT3 output.
O
MNT1 output.
O
MNT0 output.
O
2/3 frequency-divider output for Pins 73 and 74.
O
4.2336MHz output.
O
Digital Out output.
Outputs high signal when the playback disc has emphasis, low signal when no
O
emphasis.
I
DAC de-emphasis on/off. High: on; low: off.
O
WFCK (write frame clock) output.
No-sound data detection output; high when no sound data is detected.
O
(Left channel) 64 65
66
66 67
68
ZEROR DTS1
VDD
No-sound data detection output; high when no sound data is detected.
O
(Right channel)
I
Test pin 1 for DAC; normally low. Digital power supply for DAC.
– 5 –
CXD2508AQ/AR
Pin No.
Symbol
I/O
Description
RQ
67
69 68 69 70 71 72 73 74 75 76 77 78
70
71
72
73
74
75
76
77
78
79
80
NLPWM LPWM AVDD2 AVDD3 XTAI XTAO AVSS3 AVSS2 NRPWM RPWM DTS2 DTS3
O
Left channel PWM output. (Reverse phase)
O
Left channel PWM output. (Forward phase) Power supply for PWM driver. Power supply for crystal.
I
33.8688MHz crystal oscillation circuit input.
O
33.8688MHz crystal oscillation circuit output. GND for crystal. GND for PWM driver.
O
Right channel PWM output. (Reverse phase)
O
Right channel PWM output. (Forward phase)
I
DAC test pin 2; normally low.
I
DAC test pin 3; normally low.
Note)
PCMD is an MSB first, two's complement output.
GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
XUGF is the negative pulse for the frame sync derived from the EFM signal. It is the signal before sync
protection.
XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the EFM signal transition point coincide.
GFS goes high when the frame sync and the insertion protection timing match.
RFCK is derived with the crystal accuracy. This signal has a cycle of 136µ.
C2PO represents the data error status.
XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.
– 6 –
CXD2508AQ/AR
Electrical Characteristics DC Characteristics (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
NOTE)
Item
High level input voltage
Low level input voltage
Input voltage (1)Input voltage (2)Input voltage (3)Output voltage (1)Output voltage (2)Output voltage (3)Output voltage (4)
High level input voltage
Low level input voltage
Input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
VIH (1)
VIL (1)
VIH (2)
VIL (2)
VIN (3)
VOH (1)
VOL (1)
VOH (2)
VOL (2)
Conditions
Schmitt input
Analog input
IOH = –4mA
IOL = 4mA
IOH = –2mA
IOL = 4mA
Min.
0.7VDD
0.8VDD
VSS
VDD–0.8
0
VDD–0.8
0
Typ.
Max.
0.3VDD
0.2VDD
VDD
VDD
0.4
VDD
0.4
Unit
V
V
V
V
V
V
V
V
V
Applicable
pins
1
2
3
4
5
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Input leak current Tri-state pin output leak
current
VOH (3)
VOL (3)
VOH (4)
VOL (4)
ILI
ILO
IOH = –0.28mA
IOL = 0.36mA
IOH = –10mA
IOL = 10mA VI = 0 to 5.25V VO = 0 to 5.25V
VDD–0.5
0
VDD–0.4
0
VDD
0.4
VDD
0.4 ±5 ±5
V
V
V
V µA µA
1, 2, 3
Applicable pins
1
XTSL, DATA, XLAT, PCMDI, EMPHI, DTS1, DTS2, DTS3, SPOA, SPOB, SPOC
2
CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, ASYE, LRCKI, BCKI
3
CLTV, FILI, RF, BIAS, ASYI
4
MDP, PCO
5
ASYO, DOUT, FSTT, C4M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO, XLTO, SENS, MDS, LRCK, WFCK, PCMD, BCK, GTOP, XUGF, XPCK, GFS, RFCK, XROF, MNT0, MNT1, MNT3, ZEROL, ZEROR
6
FILO
7
LPWM, NLPWM, RPWM, NRPWM
8
SENS, MDS, MDP Note) "AVDD" refers to AVDD1, AVDD2, and AVDD3. In addition, "AVss" refers to AVss1, AVss2, and AVss3.
6
7
8
– 7 –
AC Characteristics
1) XTAI pin
(1) When using self-oscillation (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item Symbol Min. Typ. Max. Unit
Oscillation frequency fMAX 15 34 MHz
(2) When inputting pulses to XTAI
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item Symbol Min. Typ. Max. Unit
CXD2508AQ/AR
High level pulse width
Low level pulse width
Pulse cycle
Input high level
Input low level Rise time,
fall time
tWHX
tWLX
tCK
13 500
13 500
26 1,000
VIHX VDD – 1.0
VILX 0.8
tR, tF
tCX
tWHX
10
tWLX
ns
ns
ns
V
V
ns
IHX
V V
IHX × 0.9
XTAI
tr
tr
(3) When inputting sine waves to XTAI via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item Symbol Min. Typ. Max. Unit
Input amplitude V1 2.0 VDD + 0.3 Vp-p
– 8 –
V
DD/2
VIHX × 0.1
VILX
2) CLOK, DATA, XLAT, CNIN, SQCK EXCK pins
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit
CXD2508AQ/AR
Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width
fCK
tWCK tSU tH tD tWL
fT fWT
CLK
DATA
XLT
EXCK
CNIN
SQCK
SUBQ SQCK
750 300 300 300 750
750
tSU
tSU
1/fCX
tWCK tWCK
tH
tWT tWT
1/fr
tH
0.65
0.65
tD
MHz
ns ns ns ns ns
MHz
ns
tWL
In pseudo double-speed playback mode, when SL0 = SL1 = 1, the maximum operating frequency for SQCK is 300kHz and the minimum pulse width is 1.5µs.
3) BCKI, LRCKI, and PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) Item Symbol
BCK pulse width DATAL, R setup time DATAL, R hold time LRCK setup time
BCKI
PCMDI
tW tSU tH tSU
Conditions
tW(BCKI)tW(BCKI)
VDD/2 VDD/2
tSU
(PCMDI)
(PCMDI)
Min.
94 18 18 18
tH
Typ.
Max. Unit
118 141 nsec
tsu
(LRCKI)
nsec nsec nsec
LRCKI
– 9 –
CXD2508AQ/AR
1-bit DAC Block Analog Characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)
Item
Total harmonic distortion
S/N ratio
Symbol
THD
S/N
Conditions
1kHz, 0dB data
1kHz, 0dB data (using filter A)
Playback mode Normal speed Pseudo double-speed playback Normal speed Pseudo double-speed playback
Min.
87
83 For both items, Fs=44.1kHz The circuits for measuring the total harmonic distortion and S/N ratio are shown below.
4.7k
RPWM
NRPWM
11k
470p 470p
11k
4.7k
820p
820p
4.7k
4.7k
4.7k
2700p
4.7k 560p
22µ
100
330k
Analog LPF Circuit
Typ.
Max.
0.015
0.025
SHIBASOKU (AM51A)
Audio Analyzer
Unit
%
dB
EFM
Signal
Generater
768Fs/384Fs (Normal speed/Pseudo double-speed playback)
RF
CXD2508AQ/AR
RPWM NRPWM NLPWM LPWM
Analog
Circuit
Rch A
Lch B
Block Diagram for Measuring Analog Characteristics
SHIBASOKU (AM51A)
Audio
Analyzer
– 10 –
CXD2508AQ/AR
Description of Functions
1. CPU Interface and Instructions
CPU interface
This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below.
750ns or more
CLOK
D1
DATA
D2 D3 D0 D1 D2 D3
750ns or more
Valid
300ns max
XLAT
Registers 4 to E
Data
Address
Information on each address and the data is provided in Table 1-1.
The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2. Note) When XLAT is low, EXCK and SQCK must be set high.
– 11 –
CXD2508AQ/AR
Data 4
Data 3
Data 2
D0D3 D2 D1
D3 D2 D1
D0
D2 D1
D0 D3
17
2
4
8
16
32
64
128
256
512
1024
VCO
SEL
FSTT
SEL
0
0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
DADS
Address Data 1
D3 D2 D1
D0
D1
D3 D2
D0
AS1 AS0
AS3 AS2
0
0
1
0
0.05ms 0.02ms
0.18ms 0.09ms 1
0
1
0
0.18ms 0.09ms 0.05ms
0.36ms
5.8ms 2.9ms 1.45ms
11.6ms
0
1
1
0
2048
16384 8192 4096
32768 1
1
1
0
WSEL
DOUT
ON/OFF
DOUT
MUTE
CD-
ROM
0
0
0
1
0
DSPB
ON/OFF
0 0 0
1
0
0
1
Mute ATT
0 0
0
1
0
1
SL 0 CPUSR 0
SL 1
1
1
0
1
Gain
MDS0
Gain
MDS1
Gain
MDP0
Gain
MDP1
0
0
1
1
Gain
CLVS
TB TP
DCLV
PWMmod
1
0
1
1
CM1 CM0
CM3 CM2
0
1
1
1
Table 1-1
Don't Use
1
1
1
1
Command
Auto sequence
name
Register
4
Command Table
Blind (A, E), Overflow (C)
Brake (B)
KICK (D)
Auto sequence (N)
track jump count setting
6
5
MODE specification
Function specification
Audio CTRL
Serial bus CTRL
8
9
A
B
– 12 –
Servo coefficient setting
CLV CTRL
CLV mode
TEST mode
F
C
E
D
CXD2508AQ/AR
Data 4
Data 3
Data 2
D0D3 D2 D1
D3 D2 D1
D0
D2 D1
D0 D3
07
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
1
1
1
0
Address Data 1
D3 D2 D1
D0
D1
D3 D2
D0
0
1
0
1
0
0
0
0
1
0
0
0
0
Table 1-2
0
0
0
0
0
1
0
1
0
1
1
0
0
0
1
1
0
1
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
1
1
1
0
0
0
Don't Use
0
0
1
0
1
0
1
1
1
1
1
1
1
1
Command
Auto sequence
name
4
Register
Reset Initialization
Blind (A, E), Overflow (C)
Brake (B)
KICK (D)
Auto sequence (N)
track jump count setting
5 0
6
MODE specification
Function specification
Audio CTRL
Serial bus CTRL
8
9
A
B
– 13 –
Servo coefficient setting
CLV CTRL
CLV mode
TEST mode
F
C
E
D
1-1. The meaning of the data for each address is explained below. $4X commands
CXD2508AQ/AR
Command CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2N TRACK JUMP N TRACK MOVE
AS3
0 0 1 1 1 1
AS2
0 1 0 0 1 1
AS1
0 1 0 1 0 1
AS0
0
1 RXF RXF RXF RXF
RXF = 0 FORWARD RXF = 0 REVERSE
When the FOCUS-ON command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
When the TRACK JUMP/MOVE commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is
interrupted.
$5X commands
Auto sequence timer setting Setting timers: A, E, C, B
Command
Blind (A, E), Over flow (C)
D3
0.18ms
D2
0.09ms
D1
0.05ms
D0
0.02ms
Brake (B)
0.36ms
0.18ms
0.09ms
Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)
A = E = C = 0.11ms B = 0.23ms
$6X commands
Auto sequence timer setting Setting timer: D
Command
KICK (D)
D3
11.6ms
D2
5.8ms
2.9ms
Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)
D = 10.15ms
$7X commands
Auto sequence TRACK JUMP/MOVE count setting (N)
Data 1 Data 2
Command
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Auto sequence track jump number setting
2152142132122112102928272625242322212
D1
0.05ms
D0
1.45ms
Data 3 Data 4
0
This command is used to set N when a 2N TRACK JUMP and an N TRACK MOVE are executed for auto sequence.
The maximum track count is 65,535, but note that with 2N track jumps the maximum track jump count is determined by the mechanical limitations of the optical system.
The number of track jump is counted according to the signals input from CNIN pin.
– 14 –
$8X commands
CXD2508AQ/AR
Command
MODE specification
CDROM
Command bit
CDROM = 1
CDROM = 0
Command bit DOUT MUTE = 1 DOUT MUTE = 0
Command bit
DOUT ON-OFF = 1 DOUT ON-OFF = 0
Data 1
D3 D2 D1 D0
DOUT MUTE
DOUT
ON-OFF
WSEL
C2PO timing
1-3
1-3
CDROM mode; average value interpolation and pre-value hold are not performed.
Audio mode; average value interpolation and pre-value hold are performed.
D3 D2
000
Processing
Data 2
D1
Processing Digital Out output is muted. (DA output is not muted.) When no other mute conditions are set, Digital Out output is not muted.
Processing Digital Out is output from the DOUT pin. Digital Out is not output from the DOUT pin.
D0
VCO
SEL
Command bit
WSEL = 1 WSEL = 0
Command bit
VCOSEL = 1
VCOSEL = 0
$9X commands
Command
Function
specifications
Command bit
DSPB = 0
Sync protection window width ±26 channel clock
±6 channel clock
In normal-speed playback, channel clock = 4.3218MHz.
Processing
VCO for double-speed playback is selected.
VCO for normal-speed playback is selected.
Data 1
D3 D2 D1 D0
0
DSPB
ON-OFF
00
Normal-speed playback
Application Anti-rolling is enhanced. Sync window protection is enhanced.
Application Double-speed playback or low voltage
operation is possible. The selection is made for the normal
speed playback.
Data 2
D3 D2 D1 D0
000
FSTT
SEL
Processing
DSPB = 1
Command bit FSTTSEL = 0 FSTTSEL = 1
Double-speed playback
The clock with two-thirds frequency of crystal is output to FSTT pin. The clock with the sixth frequency of crystal is output to FSTT pin.
– 15 –
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