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CXD2508AQ/AR
Description
The CXD2508AQ/AR is a digital signal processor
for CD players and is equipped with built-in digital
filters, no-sound data detection circuit, and 1-bit
DAC.
• Operating temperature
Note) VDD (min.) is varied by the playback speed and built-in
VCO in the CXD2508AQ/AR. 4.5V is the value using the
VCO which generates the slower frequency in doublespeed playback. The table below shows the VDD (min.)
for each condition.
Note)
4.5 to 5.5V
(double-speed playback)
3.5 to 5.5V
(normal-speed playback)
3.4 to 5.5V
(low power consumption
or special playback mode)
When the internal operation of the LSI is set to doublespeed mode and the crystal oscillation frequency is
halved, normal-speed playback results.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
VCO
high-speed
3.404.503.40
3.40
3.403.403.40
VDD (min.) [V]
VCO
normal-speed
3.50
DAC block
3.40
– 1 –
E94602A54-ST
Pin Configuration
DTS1
V
XTAI
DTS2
DTS3
65
66
67
68
DD
69
70
71
72
73
74
75
76
77
78
79
80
ZEROL
ZEROR
NLPWM
LPWM
AVDD2
AVDD3
XTAO
AVss3
AVss2
NRPWM
RPWM
64
EMPHI
WFCK
63
62
DOUT
EMPH
61
60
C4M
59
FSTT
58
MNT0
57
MNT1
56
MNT3
55
C2PO
XROF
53
54
CXD2508AQ
Vss
52
RFCK
51
GFS
50
XPCK
49
XUGF
48
GTOP
47
BCKI
46
BCK
45
PCMD
PCMDI
44
LRCKI
43
42
LRCK
41
WDCK
CXD2508AQ/AR
ASYE
40
ASYO
39
ASYI
38
BIAS
37
RF
36
AVDD1
35
CLTV
34
AVss1
33
VDD
32
PCO
31
FILI
30
FILO
29
TEST
28
LOCK
27
MDS
26
MDP
25
EMPHI
WFCK
ZEROL
ZEROR
DTS1
V
NLPWM
LPWM
AV
DD2
AVDD3
XTAI
XTAO
AVss3
AVss2
NRPWM
RPWM
DTS2
DTS3
SCOR
SBSO
17
18
16
Vss
Vss
13
50
14
SEIN
RFCK
49
15
CNIN
GFS
48
DATO
XPCK
47
XLTO
6
5
7
MUTE
FSTT
57
SENS
56
8
XRST
MNT0
55
9
DATA
MNT1
54
10
XLAT
MNT3
53
12
11
CLOK
C2PO
XROF
52
51
CXD2508AR
2
1
SCOR
61
62
63
64
65
66
DD
67
68
69
70
71
72
73
74
75
76
77
78
79
80
3
SBSO
60
4
EXCK
EMPH
59
SQCK
SQSO
DOUT
58
C4M
CLKO
XUGF
46
SPOA
GTOP
45
19
BCKI
44
20
SPOB
BCK
43
21
XTSL
SPOC
PCMDI
42
22
XLON
LRCKI
PCMD
41
23
24
FOK
40
39
38
35
32
30
29
28
26
37
36
34
33
31
27
25
24
23
22
21
MON
LRCK
WDCK
ASYE
ASYO
ASYI
BIAS
RF
AVdd1
CLTV
AVss1
Vdd
PCO
FILI
FILO
TEST
LOCK
MDS
MDP
MON
FOK
1
EXCK
2
SQSO
3
SQCK
4
MUTE
5
SENS
6
7
XRST
8
DATA
9
XLAT
10
CLOK
– 2 –
Vss
11
12
SEIN
13
CNIN
14
DATO
15
XLTO
16
CLKO
17
SPOA
18
SPOB
19
SPOC
20
XTSL
XLON
Block Diagram
63
EMPHI
LRCKI
PCMDI
BCKI
47
MUTE
BCK
PCMD
LRCK
WDCK
C2PO
RFCK
MNT0
MNT1
MNT3
WFCK
EMPH
62
GFS
XUGF
GTOP
43
45
46
44
42
41
52
58
57
56
64
51
49
48
54
CXD2508AQ/AR
ZEROR
ZEROL
XTAO
XTAI
65
66
74
73
NLPWM
69
LPWM
Digital Filter
+
1bit DAC
6
digital
OUT
digital
CLV
CPU
interface
SUB code
Processor
error
corrector
D/A
Interface
16K RAM
EFM
demodulator
70
78
77
61
55
27
26
25
24
5
4
3
2
1
22
19
11
10
9
7
RPWM
NRPWM
DOUT
XROF
LOCK
MDS
MDP
MON
SQCK
SQSO
EXCK
SBSO
SCOR
XLON
SPOA to C
CLOK
XLAT
DATA
SENS
Servo auto
sequencer
23
FOK
13
SEIN
14
CNIN
XTSL
18
clock
generator
60
59
FSTT
C4M
36
RF
asymmetry
corrector
39
38
ASYI
ASYO
40
37
ASYE
BIAS
50
29
XPCK
digital
PLL
30
FILO
FILI
31
PCO
34
CLTV
Note) The pin numbers are for QFP. Refer to the Pin Description for those of LQFP.
– 3 –
17
16
15
CLKO
XLTO
DATO
Pin Description
CXD2508AQ/AR
Pin No.
RQ
79
80
10
11
12
13
1
2
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
11
12
13
14
15
Symbol
SCOR
SBSO
EXCK
SQSO
SQCK
MUTE
SENS
XRST
DATA
XLAT
CLOK
VSS
SEIN
CNIN
DATO
I/O
Outputs a high signal when either subcode sync S0 or S1 is detected.
O
Sub P to W serial output.
O
SBSO readout clock input.
I
Sub Q 80-bit serial output.
O
SQSO readout clock input.
I
High: mute; low: release
I
SENS output to CPU.
O
System reset. Reset when low.
I
Serial data input from CPU.
I
Latch input from CPU. Serial data is latched at the falling edge.
Block Diagram for Measuring Analog Characteristics
SHIBASOKU (AM51A)
Audio
Analyzer
– 10 –
CXD2508AQ/AR
Description of Functions
1. CPU Interface and Instructions
• CPU interface
This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below.
750ns or more
CLOK
D1
DATA
D2D3D0D1D2D3
750ns or more
Valid
300ns max
XLAT
Registers 4 to E
Data
Address
• Information on each address and the data is provided in Table 1-1.
• The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2.
Note) When XLAT is low, EXCK and SQCK must be set high.
– 11 –
CXD2508AQ/AR
Data 4
Data 3
Data 2
D0D3D2D1
D3D2D1
D0
D2D1
D0D3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17
—
—
—
—
—
—
—
—
—
—
—
2
4
8
16
32
64
128
256
512
1024
—
—
—
—
—
—
—
—
VCO
SEL
—
—
—
—
—
—
—
—
—
—
FSTT
SEL
0
0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
—
—
DADS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AddressData 1
D3D2D1
D0
D1
D3D2
D0
—
AS1AS0
AS3AS2
0
0
1
0
—
0.05ms 0.02ms
0.18ms 0.09ms
1
0
1
0
0.18ms 0.09ms 0.05ms
0.36ms
—
5.8ms 2.9ms 1.45ms
11.6ms
0
1
1
0
2048
16384 81924096
32768
1
1
1
0
—
WSEL
DOUT
ON/OFF
DOUT
MUTE
CD-
ROM
0
0
0
1
0
DSPB
ON/OFF
000
1
0
0
1
—
MuteATT
00
0
1
0
1
—
SL 0 CPUSR0
SL 1
1
1
0
1
—
Gain
MDS0
Gain
MDS1
Gain
MDP0
Gain
MDP1
0
0
1
1
—
Gain
CLVS
TBTP
DCLV
PWMmod
1
0
1
1
—
CM1CM0
CM3CM2
0
1
1
1
—
Table 1-1
Don't Use
1
1
1
1
Command
Auto sequence
name
Register
4
Command Table
Blind (A, E), Overflow (C)
Brake (B)
KICK (D)
Auto sequence (N)
track jump count setting
6
5
MODE specification
Function specification
Audio CTRL
Serial bus CTRL
8
9
A
B
– 12 –
Servo coefficient setting
CLV CTRL
CLV mode
TEST mode
F
C
E
D
CXD2508AQ/AR
Data 4
Data 3
Data 2
D0D3D2D1
D3D2D1
D0
D2D1
D0D3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
07
—
—
—
—
—
—
—
—
—
—
—
—
0
—
0
—
0
—
0
—
0
—
0
—
0
—
0
1
0
—
0
—
1
—
—
—
—
—
—
—
—
0
0
0
—
—
—
—
—
1
—
—
—
—
—
1
—
—
—
—
—
1
—
—
—
—
—
1
—
—
—
—
—
1
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
AddressData 1
D3D2D1
D0
D1
D3D2
D0
—
—
0
1
0
—
1
0
0
—
0
—
—
—
—
—
—
0
1
0
0
0
0
Table 1-2
0
0
0
0
0
1
0
1
0
1
1
0
0
0
1
1
0
1
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
0
0
1
0
1
0
0
1
1
1
0
0
0
Don't Use
0
0
1
0
1
0
1
1
1
1
1
1
1
1
Command
Auto sequence
name
4
Register
Reset Initialization
Blind (A, E), Overflow (C)
Brake (B)
KICK (D)
Auto sequence (N)
track jump count setting
50
6
MODE specification
Function specification
Audio CTRL
Serial bus CTRL
8
9
A
B
– 13 –
Servo coefficient setting
CLV CTRL
CLV mode
TEST mode
F
C
E
D
1-1. The meaning of the data for each address is explained below.
$4X commands
• When the FOCUS-ON command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the TRACK JUMP/MOVE commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is
interrupted.
$5X commands
Auto sequence timer setting
Setting timers: A, E, C, B
Command
Blind (A, E), Over flow (C)
D3
0.18ms
D2
0.09ms
D1
0.05ms
D0
0.02ms
Brake (B)
0.36ms
0.18ms
0.09ms
Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)
A = E = C = 0.11ms
B = 0.23ms
$6X commands
Auto sequence timer setting
Setting timer: D
Command
KICK (D)
D3
11.6ms
D2
5.8ms
2.9ms
Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)
D = 10.15ms
$7X commands
Auto sequence TRACK JUMP/MOVE count setting (N)
Data 1Data 2
Command
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Auto sequence track jump
number setting
2152142132122112102928272625242322212
D1
0.05ms
D0
1.45ms
Data 3Data 4
0
This command is used to set N when a 2N TRACK JUMP and an N TRACK MOVE are executed for auto
sequence.
• The maximum track count is 65,535, but note that with 2N track jumps the maximum track jump count is
determined by the mechanical limitations of the optical system.
• The number of track jump is counted according to the signals input from CNIN pin.
– 14 –
$8X commands
CXD2508AQ/AR
Command
MODE
specification
CDROM
Command bit
CDROM = 1
CDROM = 0
Command bit
DOUT MUTE = 1
DOUT MUTE = 0
Command bit
DOUT ON-OFF = 1
DOUT ON-OFF = 0
Data 1
D3D2D1D0
DOUT
MUTE
DOUT
ON-OFF
WSEL
C2PO timing
1-3
1-3
CDROM mode; average value interpolation and
pre-value hold are not performed.
Audio mode; average value interpolation and pre-value
hold are performed.
D3D2
000
Processing
Data 2
D1
Processing
Digital Out output is muted. (DA output is not muted.)
When no other mute conditions are set, Digital Out output is not muted.
Processing
Digital Out is output from the DOUT pin.
Digital Out is not output from the DOUT pin.
D0
VCO
SEL
Command bit
WSEL = 1
WSEL = 0
Command bit
VCOSEL = 1
VCOSEL = 0
$9X commands
Command
Function
specifications
Command bit
DSPB = 0
Sync protection window width
±26 channel clock
∗
±6 channel clock
∗
In normal-speed playback, channel clock = 4.3218MHz.
Processing
VCO for double-speed
playback is selected.
VCO for normal-speed
playback is selected.
Data 1
D3D2D1D0
0
DSPB
ON-OFF
00
Normal-speed playback
Application
Anti-rolling is enhanced.
Sync window protection is enhanced.
Application
Double-speed playback or low voltage
operation is possible.
The selection is made for the normal
speed playback.
Data 2
D3D2D1D0
000
FSTT
SEL
Processing
DSPB = 1
Command bit
FSTTSEL = 0
FSTTSEL = 1
Double-speed playback
The clock with two-thirds frequency of crystal is output to FSTT pin.
The clock with the sixth frequency of crystal is output to FSTT pin.
– 15 –
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