Sony CXD2507AQ Datasheet

CD Digital Signal Processor

For the availability of this product, please contact the sales office.

Description

The CXD2507AQ is a digital signal processor for
CD players and is equipped with the following
functions.

Features

•Digital PLL

•EFM frame sync protection

•SEC strategy-based error correction

•Subcode demodulation, CRC checking

•Digital spindle servo

•Servo auto-sequencer

•Asymmetry compensation circuit

•Digital audio interface output

•16K RAM

•Double-speed playback capability

•New microcomputer interface circuit

CXD2507AQ

64 pin QFP (Plastic)

-L01

-L121

Absolute Maximum Ratings

•Supply voltage VDD –0.3 to +7.0 V

•Supply voltage variationVSS– AVSS –0.3 to +0.3 V

VDD– AVDD –0.3 to +0.3 V

•Input voltage VI –0.3 to +7.0 V

VIN VSS – 0.3 to VDD + 0.3 V

•Output voltage VO –0.3 to +7.0 V

•Storage temperature Tstg –40 to +125 °C

Recommended Operating Conditions

•Supply voltage VDD 4.5 to 5.5V (double-speed playback)

3.5 to 5.5V (normal-speed playback)

3.0 to 5.5V (low power consumption, special playback mode)

•Operating temperature Topr –20 (min.) 75 (max.) °C

∗

When the internal operation of the LSI is set to double-speed mode and the crystal oscillation
frequency is halved, normal-speed playback results.

∗

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1–

E94601A11

Pin Configuration

DATA

51

52

XLAT

53

CLOK

54

SEIN

55

CNIN

56

DATO

57

XLTO

58

DD

V

59

CLKO

60

SPOA

50

XRST

49

SENS

48

MUTE

47

SQCK

46

SQSO

45

EXCK

44

SBSO

43

SCOR

42

Vss

WFCK

41

EMPH

40

DOUT

39

38

C4M

37

FSTT

36

XTSL

35

XTAO

34

XTAI

33

MNT0

CXD2507AQ

MNT1

32

MNT3

31

XROF

30

C2PO

29

RFCK

28

GFS

27

DD

V

26

XPCK

25

XUGF

24

SPOB
SPOC
SPOD

XLON

61
62
63
64

1

FOK

2

MON

3

MDP

4

MDS

5

LOCK

6

TEST

7

FILO

23

GTOP
BCK

22
21

PCMD

20

LRCK

9

FILI

PCO

10

Vss

11

AVss

8

12

CLTV

13

DD

AV

14 15

RF

BIAS

16

ASYI

17

ASYO

18

ASYE

19

WDCK

– 2 –

Block Diagram

CXD2507AQ

MNT0

MNT1

MNT3

WFCK
EMPH

GFS

XUGF

GTOP

33

32

31

41
40
27

24
23

RFCK

28

29

Error

corrector

MUTE

C2PO

48

EFM

Demodulator

WDCK

19

Interface

LRCK

20

D/A

PCMD

21

BCK

22

16K RAM

SUB code
processor

DOUT

39

Digital

OUT

Digital

CLV

CPU

Interface

30

5
4
3

2

47

46

45
44

43
64
60
53
52
51
49

XROF
LOCK
MDS
MDP
MON

SQCK
SQSO
EXCK

SBSO
SCOR
XLON
SPOA to D
CLOK
XLAT
DATA

SENS

XTSL

XTAO

XTAI

36
35
34

Clock

generator

37

38

FSTT

C4M

14

Asymmetry

corrector

16

RF

ASYI

17

18

ASYE

ASYO

15

BIAS

25

7

XPCK

– 3 –

Digital

PLL

8

FILI

FILO

9

12

PCO

CLTV

Servo auto
sequencer

1

54

FOK

SEIN

55

CNIN

59

57

56

CLKO

XLTO

DATO

Pin Description

Pin

Symbol

No.

I/O

CXD2507AQ

Description

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

1
2
3
4

5
6

7
8
9

FOK
MON
MDP
MDS

LOCK
TEST

FILO
FILI
PCO
VSS
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
ASYE
WDCK
LRCK
PCMD
BCK
GTOP
XUGF
XPCK
VDD
GFS
RFCK
C2PO
XROF
MNT3
MNT1
MNT0
XTAI
XTAO
XTSL

O
O
O

O

O

O
—
—

—

O

O

O

O

O

O

O

O
—

O

O

O

O

O

O

O

O

I

I

I

I

I
I
I

I

I

I

1, 0
1, Z, 0
1, Z, 0

1, 0

Analog

1, Z, 0

—
—

—

1, 0

1, 0

1, 0

1, 0

1, 0

1, 0

1, 0

1, 0

—
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0

1, 0

Focus OK input. Used for SENS output and the servo auto sequencer.
Spindle motor on/off control output.
Spindle motor servo control.
Spindle motor servo control.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.

If GFS is low eight consecutive samples, this pin outputs low.
TEST pin. Normally GND.
Master PLL (slave = digital PLL) filter output.
Master PLL filter input.
Master PLL charge pump output.
GND.
Analog GND.
Master VCO control voltage input.
Analog power supply (+5V).
EFM signal input.
Constant current input of asymmetry circuit.
Asymmetry comparator voltage input.
EFM full-swing output (low = Vss, high = VDD).
Low: asymmetry circuit off; high: asymmetry circuit on.
D/A interface. Word clock f = 2Fs.
D/A interface. LR clock f = Fs.
D/A interface. Serial data (two's complement, MSB first).
D/A interface. Bit clock.
GTOP output.
XUGF output.
XPLCK output.
Power supply (+5V).
GFS output.
RFCK output.
C2PO output.
XRAOF output.
MNT3 output.
MNT1 output.
MNT0 output.

16.9344MHz crystal oscillation circuit input, or 33.8688MHz input.

16.9344MHz crystal oscillation circuit output.
Crystal selection input. Set low when the crystal is 16.9344MHz, high when 33.8688MHz.

– 4 –

Pin
No.

37
38
39
40
41
42
43
44
45
46
47
48

Symbol

FSTT
C4M
DOUT
EMPH
WFCK
VSS
SCOR
SBSO
EXCK
SQSO
SQCK
MUTE

O
O
O
O
O

—

O
O

O

CXD2507AQ

I/O

1, 0
1, 0
1, 0
1, 0
1, 0

—
1, 0
1, 0

I

1, 0

I
I

2/3 frequency divider output for Pins 34 and 35.

4.2336MHz output.
Digital Out output.
Outputs high signal when the playback disc has emphasis, low signal when no emphasis.
WFCK output.
GND.
Outputs high signal when either subcode sync S0 or S1 is detected.
Sub P to W serial output.
SBSO readout clock input.
SubQ 80-bit serial output.
SQSO readout clock input.
High: mute; low: release

Description

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

SENS
XRST
DATA
XLAT
CLOK
SEIN
CNIN
DATO
XLTO
VDD
CLKO
SPOA
SPOB
SPOC
SPOD
XLON

O

O
O

—

O

O

1, 0

I
I
I
I
I
I

1, 0
1, 0

—
1, 0

I
I
I
I

1, 0

SENS output to CPU.
System reset. Reset when low.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
Sense input from SSP.
Track jump count signal input.
Serial data output to SSP.
Serial data latch output to SSP. Latched at the falling edge.
Power supply (+5V).
Serial data transfer clock output to SSP.
Microcomputer extended interface (input A).
Microcomputer extended interface (input B).
Microcomputer extended interface (input C).
Microcomputer extended interface (input D).
Microcomputer extended interface (output).

Notes)

• PCMD is two's complement output of MSB first.

• GTOP is used to monitor the frame sync protection status.

• XUGF is the negative pulse for the frame sync derived from the EFM signal. It is the signal before

sync protection.

• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.

• GFS goes high when the frame sync and the insertion protection timing match.

• RFCK is derived from the crystal accuracy. This signal has a cycle of 136µ.

• C2PO represents the data error status.

• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.

– 5 –

CXD2507AQ

Electrical Characteristics
DC Characteristics (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item

High level input voltage

Low level input voltage

Input voltage (1)Input voltage (2)Input voltage (3)Output voltage (1)Output voltage (2)Output voltage (3)

High level input voltage

Low level input voltage

Input voltage

High level output
voltage

Low level output
voltage

High level output
voltage

Low level output
voltage

VIH (1)

VIL (1)

VIH (2)

VIL (2)

VIN (3)

VOH (1)

VOL (1)

VOH (2)

VOL (2)

Conditions

Schmitt input

Analog input

IOH = –4mA

IOL = 4mA

IOH = –2mA

IOL = 4mA

Min. Typ.

0.7VDD

0.8VDD

VSS

VDD – 0.8

0

VDD – 0.8

0

Max.

0.3VDD

0.2VDD

VDD

VDD

0.4

VDD

0.4

Unit

V

V

V

V

V

V

V

V

V

Applicable

pins

∗1

∗2

∗3

∗4

∗5

High level output
voltage

Low level output
voltage

Input leak current
Tri-state pin output leak

current

VOH (4)

VOL (4)

ILI

ILO

IOH = –0.28mA

IOL = 0.36mA
VI = 0 to 5.25V
VO = 0 to 5.25V

VDD – 0.5

0

VDD

0.4
±5
±5

V

V
µA
µA

∗1, ∗2, ∗3

Applicable pins

∗1

XTSL, DATA, XLAT

∗2

CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, ASYE

∗3

CLTV, FILI, RF

∗4

MDP, PCO

∗5

ASYO, DOUT, FSTT, C4M, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO,
XLTO, SENS, MDS, LRCK, WFCK, PCMD, BCK, GTOP, XUGF, XPCK, GFS, RFCK, XROF, MNT0, MNT1,
MNT3

∗6

FILO

∗7

MDS, MDP, PCO

∗6

∗7

– 6 –

AC Characteristics

1) XTAI and VCOI pins

(1) When using self-oscillation (Topr = –20 to +75°C, VDD =AVDD = 5.0V ± 5%)

Item Symbol Min. Typ. Max. Unit

Oscillation frequency fMAX 7 34 MHz

(2) When inputting pulses to XTAI and VCOI

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

Item Symbol Min. Typ. Max. Unit

CXD2507AQ

High level
pulse width

Low level
pulse width

Pulse cycle

Input high level

Input low level
Rise time,

fall time

tWHX

tWLX

tCX

13 500

13 500

26 1,000

VIHX VDD – 1.0

VILX 0.8

tR, tF

tCX

tWHX

10

tWLX

ns

ns

ns

ns

V

V

IHX

V
V

IHX × 0.9

XTAI

tR tF

(3) When inputting sine waves to XTAI and VCOI pins via a capacitor

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

Item Symbol Min. Typ. Max. Unit

Input amplitude V1 2.0 VDD + 0.3 Vp-p

– 7 –

V

DD/2

VIHX × 0.1
VILX

2) CLOK, DATA, XLAT, CNIN, SQCK EXCK pins

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item Symbol Min. Typ. Max. Unit

CXD2507AQ

Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK SQCK frequency
EXCK SQCK pulse width

fCK

tWCK
tSU
tH
tD
tWL

fT

tWT

DATA

EXCK

CNIN

SQCK

SBSO
SQSO

CLK

XLT

750
300
300
300
750

750

∗

tSU

tSU

1/fCX

tWCK tWCK

tH

tWT tWT

1/fr

tH

0.65

0.65

MHz

ns
ns
ns
ns
ns

∗

MHz

ns

tD

tWL

∗

In low power consumption and special playback mode, when SL0 = SL1 = 1, the maximum operating
frequency for SQCK is 300kHz and the minimum pulse width is 1.5µs.

Description of Functions

1. CPU Interface and Instructions

• CPU interface

This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below.

750ns or more

CLOK

D1

DATA

XLAT

Registers 4 to E

D2 D3 D0 D1 D2 D3

Data

Address

750ns or more

Valid

300ns max

• Information on each address and the data is provided in Table 1-1.

• The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2.
Note) When XLAT is low, EXCK and SQCK must be set high.

– 8 –

CXD2507AQ

D1 D0D3 D2

Data 4

D0 D3 D2

Data 3

D3 D2 D1

D1 D0

Data 2

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

17

2

4

8

16

32

64

128

256

512

1024

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

0

0

0

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

D3 D2

D1 D0

D2

D3

D1 D0

Address Data 1

—

AS0

AS2 AS1

AS3
0

0

1

0

—

0.05ms0.02ms

0.09ms0.05ms

0.18ms0.09ms

0.36ms0.18ms

1

0

1

—

2.9ms 1.45ms

11.6ms 5.8ms

0

1

1

0

2048

4096

16384 8192

32768
1

1

1

0

—

WSEL

DOUT

ON/OFF

DOUT

MUTE

CD-

ROM

0

0

0

1

0

DSPB

ON/OFF

0 000

1

0

0

1

—

ATT

0 Mute

0

1

0

1

—

—

0

Gain

Gain

CPUSR

Gain

SL0

Gain

SL1
1

0

1

0

0

1

1

1

CLVS

MDS0

MDS1

MDP0

DCLV

MDP1

—

—

Gain

TB TP

CM2 CM1 CM0

CM3

PWMmod

1

0

0

1

1

1

1

1

—

Table 1-1

Don't Use

1

1

1

1

Command

Auto sequence

Blind (A, E), Overflow (C)

name

Register

5 0

4

CD2507 Command Table

Brake (B)

KICK (D)

6

Auto sequence (N)

track jump count setting

MODE specification

Function specification

Audio CTRL

8

9

A

– 9 –

Serial bus CTRL

Servo coefficient setting

CLV CTRL

CLV mode

TEST mode

B

C

D

F

E

Values shown as "0" in the above table must be sent as "0".

CXD2507AQ

D1 D0D3 D2

Data 4

D0 D3 D2

Data 3

D3 D2 D1

D1 D0

Data 2

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

07

—

—

—

—

—

—

—

—

0

—

—

—

—

—

—

—

—

0

—

—

—

—

—

—

—

—

0

—

—

—

—

—

—

—

—

0

—

—

—

—

—

—

—

—

0

—

—

—

—

—

—

—

—

0

—

—

—

—

—

—

—

—

0

—

—

—

—

—

—

—

—

—

—

—

0

—

—

—

—

—

—

0

—

—

—

—

—

—

0

—

—

—

—

—

—

1

0

0

D3 D2

D2 D1 D0

D3

D1 D0

Address Data 1

—

0

0

0

0

0

0

1

0

—

1

0

1

0

1

0

1

—

1

1

1

0

0

1

1

0

—

0

0

—

—

—

—

—

—

0

1

0

0

0

0

0

0

Table 1-2

1

0

1

1

1

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

0

1

0

1

0

0

1

0

0

1

1

1

0

0

1

0

1

0

0

1

1

1

0

0

0

Don't Use

0

0

1

0

1

0

1

1

1

1

1

1

1

1

Command

Auto sequence

Blind (A, E), Overflow (C)

Brake (B)

KICK (D)

name

Register

4

6

5 0

CXD2507 Reset Initialization

Auto sequencer (N)

track jump count setting

MODE specification

Function specification

Audio CTRL

8

9

A

– 10 –

Serial bus CTRL

Servo coefficient setting

CLV CTRL

CLV mode

TEST mode

B

C

D

F

E

1-1. The meaning of the data for each address is explained below.
$4X commands

CXD2507AQ

Command
CANCEL
FOCUS-ON
1 TRACK JUMP
10 TRACK JUMP
2N TRACK JUMP
N TRACK MOVE

AS3

0
0
1
1
1
1

AS2

0
1
0
0
1
1

AS1

0
1
0
1
0
1

AS0

0

1
RXF
RXF
RXF
RXF

RXF = 0 FORWARD
RXF = 1 REVERSE

• When the FOCUS-ON command ($47) is canceled, $02 is sent and the auto sequence is interrupted.

• When the TRACK JUMP/MOVE commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is

interrupted.

$5X commands

Auto sequence timer setting
Setting timers: A, E, C, B

Command

Blind (A, E), Over flow (C)

D3

0.18ms

D2

0.09ms

D1

0.05ms

D0

0.02ms

Brake (B)

0.36ms

0.18ms

0.09ms

Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial reset)

A = E = C = 0.11ms
B = 0.23ms

$6X commands

Auto sequence timer setting
Setting timer: D

Command

KICK (D)

D3

11.6ms

D2

5.8ms

2.9ms

Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial reset)

D = 10.15ms

$7X commands

Auto sequence TRACK JUMP/MOVE count setting (N)

Data 1 Data 2

Command

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Auto sequence track jump
count setting

2152142132122112102928272625242322212

D1

0.05ms

D0

1.45ms

Data 3 Data 4

0

This command is used to set N when a 2N TRACK JUMP and an N TRACK MOVE are executed for auto
sequence.

• The maximum track count is 65,535, but note that with 2N track jumps the maximum track jump count is
determined by the mechanical limitations of the optical system.

• The number of track jump is counted according to the signals input from CNIN pin.

– 11 –

$8X commands

CXD2507AQ

Command

MODE
specification

CDROM

Command bit

CDROM = 1

CDROM = 0

Command bit
DOUT MUTE = 1
DOUT MUTE = 0

Command bit

DOUT ON-OFF = 1
DOUT ON-OFF = 0

Command bit

WSEL = 1

D3 D2 D1 D0

DOUT
MUTE

C2PO timing

1-3

1-3

DOUT

ON-OFF

WSEL

Processing

CDROM mode; average value interpolation and
pre-value hold are not performed.

Audio mode; average value interpolation and pre-value
hold are performed.

Processing
Digital out output is muted. (DA output is not muted.)
When no other mute conditions are set, digital out is not muted.

Processing

Digital out is output from the DOUT pin.
Digital out is not output from the DOUT pin.

Sync protection window width
±26 channel clock

∗

Anti-rolling is enhanced.

Application

WSEL = 0

∗

In normal-speed playback, channel clock = 4.3218MHz.

±6 channel clock

$9X commands

Data 1

Command

D3 D2 D1 D0

Function

specifications

0

DSPB

ON-OFF

00

Command bit

DSPB = 0
DSPB = 1

Normal-speed playback
Double-speed playback

$AX commands

Data 1

Command

D3 D2 D1 D0

Audio CTRL 0 0 Mute ATT

Sync window protection is enhanced.

Data 2

D3 D2 D1 D0

0000

Processing

Command bit

Mute = 0
Mute = 1

Meaning

Mute off if other mute
conditions are not set.

Mute on.

– 12 –

Command bit

ATT = 0
ATT = 1

Meaning

Attenuation off.
–12dB