Sony CXD2457R Datasheet
Timing Generator for Progressive Scan CCD Image Sensor
Description
The CXD2457R is an IC developed to generate the
timing pulses required by Progressive Scan CCD
image sensors as well as signal processing circuits.
Features
• Electronic shutter function
• Supports non-interlaced operation
• Base oscillation frequency 30.0MHz
• Horizontal drive frequency switchable between
15/10/5MHz
• Switchable between FINE (Progressive Scan) mode
or DRAFT (high-frame rate readout) mode
• Vertical driver
Applications
Progressive Scan CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensor
ICX204AK
Absolute Maximum Ratings
• Supply voltage VDDa, VDDb, VDDc, VDDd
Vss – 0.5 to Vss + 7.0 V
• Supply voltage VSS VL – 0.5 to VL + 10.0 V
• Supply voltage VH VL – 0.5 to VL + 26.0 V
• Supply voltage VM VL – 0.5 to VL + 26.0 V
• Input voltage VI Vss – 0.5 to VDD + 0.5 V
• Output voltage VO Vss – 0.5 to VDD + 0.5 V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage 1 VDDa, VDDb, VDDc
3.0 to 3.6 V
• Supply voltage 2 VDDd 3.0 to 3.6 V
• Supply voltage 3 VH 14.25 to 15.75 V
• Supply voltage 4 VL –9.0 to –5.0 V
• Supply voltage 5 VM 0 V
• Operating temperature
Topr –20 to +75 °C
– 1 –
E98113A86-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXD2457R
48 pin LQFP (Plastic)
– 2 –
CXD2457R
Block Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
XSGA and XSGB are readout pulses that use V2A and V2B, respectively, as the VH value.
H2
AVD1
XCPDM
V-Driver
AVD2
XSHP
XSHD
XRS
VSS3
PBLK
XCPOB
ADCLK
RST
MCK
VDD1
2MCK
TEST2
SEN
SSK
SSI
Register
Pulse Generator
ID
EXP
HRO
FRO
VSS4
H1
VSS2
V
SS1
RG
AVD0
TEST1
VDD0
OSCI
1/3
OSCO
CKI
V
SS0
CKO
PS
DSGAT
VL
SUB
V2B
VH
V2A
V3
V1
XV2
XV3
XV1
XSUB
XSGB
XSGA
VM
FRI
HRI
1/2
1/1270
SSG
1/3
1/792 1/264
– 3 –
CXD2457R
Pin Configuration (Top View)
1 2 3 4 5 6 7 8 9 10 11 12
13
14
15
16
17
18
19
20
21
22
23
24
2526272829
30
313233343536
37
38
39
40
41
42
43
44
45
46
47
48
The enclosed pins use separate power supplies.
H2
AVD1
XCPDM
AVD2
XSHP
XSHD
XRS
V
SS3
PBLK
XCPOB
ADCLK
RST
MCK
VDD1
2MCK
TEST2
SEN
SSK
SSI
ID
EXP
HRO
FRO
V
SS4
H1
V
SS2
V
SS1
RG
AVD0
TEST1
V
DD0
OSCI
OSCO
CKI
V
SS0
CKO
PS
DSGAT
VL
SUB
V2B
VH
V2A
V3
V1
VM
FRI
HRI
– 4 –
CXD2457R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
CKO
Vss0
CKI
OSCO
OSCI
VDD0
TEST1
AVD0
RG
Vss1
Vss2
H1
H2
AVD1
XCPDM
AVD2
XSHP
XSHD
XRS
VSS3
PBLK
XCPOB
ADCLK
RST
MCK
VDD1
2MCK
TEST2
SEN
SSK
SSI
ID
EXP
O
—
I
O
I
—
I
—
O
—
—
O
O
—
O
—
O
O
O
—
O
O
O
I
O
—
O
I
I
I
I
O
O
Oscillator output. (30.0MHz)
GND
Oscillator input. (30.0MHz)
Inverter output for oscillation. (30.0MHz)
Inverter input for oscillation. (30.0MHz)
Power supply.
Test. With pull-down resistor. Fix to low.
Power supply.
Reset gate pulse output.
GND
GND
Clock output for horizontal CCD drive.
Clock output for horizontal CCD drive.
Power supply.
Clamp pulse.
Power supply.
Sample-and-hold pulse.
Sample-and-hold pulse.
Sample-and-hold pulse.
GND
Blanking cleaning pulse.
Clamp pulse.
Clock output for AD conversion.
Reset (Low: Reset, High: Normal operation).
Always input one reset pulse during power-on.
Clock output for digital circuit.
Power supply.
Clock output for digital circuit.
Test. Fix to high.
PS = High: Drive frequency setting input.
PS = Low: Serial setting strobe input.
PS = High: Readout method setting input.
PS = Low: Serial setting clock input.
PS = High: Shutter speed setting input.
PS = Low: Serial setting data input.
Line identification signal output write enable pulse output or XSUB output.
Pulse output indicating exposure is underway or checksum result output.
Symbol I/O Description
– 5 –
CXD2457R
Pin
No.
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
HRO
FRO
VSS4
HRI
FRI
VM
V1
V3
V2A
VH
V2B
SUB
VL
DSGAT
PS
O
O
—
I
I
—
O
O
O
—
O
O
—
I
I
Horizontal sync signal (HR) output or XSGB output.
Vertical sync signal (FR) output or XSGA output.
GND
Horizontal sync signal (HR) input.
Vertical sync signal (FR) input.
GND (vertical clock driver GND).
Clock output for vertical CCD drive.
Clock output for vertical CCD drive.
Clock output for vertical CCD drive.
15V power supply (vertical clock driver power supply).
Clock output for vertical CCD drive.
CCD electric charge sweep pulse output.
–7.5V power supply (vertical clock driver power supply).
Output stop (Same operation control as SLP when low).
Parallel/serial switching for mode setting input method.
(High: Parallel, Low: Serial) With pull-down resistor.
Symbol I/O Description
– 6 –
CXD2457R
Electrical Characteristics
DC Characteristics
(Within the recommended operating conditions)
Item
Supply voltage 1
Supply voltage 2
Supply voltage 3
Supply voltage 4
Supply voltage 5
Supply voltage 6
Supply voltage 7
Input voltage 1
Input voltage 2
Input voltage 3
Output voltage 1
Output voltage 2
Output voltage 3
Output voltage 4
Output voltage 5
Output voltage 6
Output voltage 7
Output voltage 8
VDD0, VDD1,
AVD0
AVD1
AVD2
VH
VM
VL
CKI
TEST1, PS
RST, TEST2,
SEN, SSK, SSI,
HRI, FRI, DSGAT
CKO, MCK,
2MCK
RG
H1, H2
XCPDM, XSHP,
XSHD, XRS,
PBLK, XCPOB
ID, EXP, HRO,
FRO
SUB
V1, V3
V2A, V2B
VDDa
VDDb
VDDc
VDDd
VH
VM
VL
VIH1
VIL1
VIH2
VIL2
Vt + 1
Vt – 1
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
VOH5
VOL5
VOH6
VOL6
VOM7
VOL7
VOM101
VOM102
VOL8
VOL8
3.0
3.0
3.0
3.0
14.5
—
–9.0
0.7VDDa
0.7VDDb
0.8VDDa
VDDa – 0.8
VDDb – 0.8
VDDc – 0.8
VDDd – 0.8
VDDa – 0.8
VH– 0.25
VM– 0.25
VH– 0.25
VM– 0.25
3.3
3.3
3.3
3.3
15.5
0.0
3.6
3.6
3.6
3.6
15.5
—
–5.0
0.3VDDa
0.3VDDa
0.2VDDa
0.4
0.4
0.4
0.4
0.4
VL + 0.25
VL + 0.25
VM + 0.25
VL + 0.25
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Feed current where IOH = –10.0mA
Pull-in current where IOL = 7.2mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –22.0mA
Pull-in current where IOL = 14.4mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –2.4mA
Pull-in current where IOL = 4.8mA
Feed current where IOH = –4.0mA
Pull-in current where IOL = 5.4mA
Feed current where IOH = –5.0mA
Pull-in current where IOL = 10.0mA
Feed current where IOH = –7.2mA
Pull-in current where IOL = 5.0mA
Feed current where IOH = –5.0mA
Pull-in current where IOL = 10.0mA
Pins Symbol Conditions Min. Typ. Max. Unit
– 7 –
CXD2457R
Inverter I/O Characteristics for Oscillation
(Within the recommended operating conditions)
Item
Logical Vth
Input voltage
Output voltage
Feedback resistor
Oscillator frequency
OSCI
OSCI
OSCO
OSCI, OSCO
OSCI, OSCO
LVth
VIH
VIL
VOH
VOL
RFB
f
0.7VDDd
VDDa/2
500k
20
VDDa/2
2M
0.3VDDa
VDDa/2
5M
50
V
V
V
V
V
Ω
MHz
Feed current where IOH = –6.0mA
Pull-in current where IOL = 6.0mA
VIN = VDDd or Vss
Pins
Symbol
Conditions Min. Typ. Max. Unit
Base Oscillation Clock Input Characteristics (Within the recommended operating conditions)
Item
Logical Vth
Input voltage
Input amplification
CKI
LVth
VIH
VIL
VIN
0.7VDDa
0.3
VDDa/2
0.3VDDa
V
V
V
Vp-p
fmax 50MHz sine wave
Pins
Symbol
Conditions Min. Typ. Max.
Unit
∗1
Input voltage is the input voltage characteristics for direct input from an external source. Input amplification
is the input amplification characteristics for input through capacitor.
Switching Characteristics (VH = 15.0V, VM = GND, VL = –8.5V)
Item
Rise time
TTLM
TTMH
TTLH
350
450
50
250
300
50
550
700
80
400
450
80
1.0
1.0
1.0
1.0
ns
ns
ns
VL to VM
VM to VH
VL to VH
Fall time
TTML
TTHM
TTHL
ns
ns
ns
VM to VL
VH to VM
VH to VL
Output noise
voltage
VCLH
VCLL
VCMH
VCML
V
V
V
V
Symbol Conditions Min. Typ. Max.
Unit
∗1
The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
∗2
For noise and latch-up countermeasures, be sure to connect a bypass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
– 8 –
CXD2457R
Switching Waveforms
VH
VM
VL
TTMH
90%
10%
90%
10%
VM
VL
VH
VL
TTLH
90%
10%
TTLM
90%
10%
TTML
90%
10%
V2A (V2B)
TTLM
90%
10%
TTML
90%
10%
V1 (V3)
VSUB
TTHM
90%
10%
TTHL
Waveform Noise
VH
VL
VCLH
VCLL
VCMH
VCML
Measurement Circuit
R2
C1
C1
C2C2
C2C2
C1C1
R1
R1
R1
R1
V1
R1: 27Ω
R2: 5Ω
C1: 1500pF
C2: 3300pF
V3
V2A
V2B
– 9 –
CXD2457R
2) Serial interface clock internal loading characteristics
V2A
HRI
300ns
0.5V
DDa
0.5V
DDa
300ns
Do not rise the SEN level in this time
(300ns after the fall of HRI just before XSGA pulse generation
to 300ns after the fall of HRI just after XSGA pulse generation)
(Within the recommended operating conditions)
AC Characteristics
1) AC characteristics between the serial interface clocks
SSI
SSK
SEN
SEN
ts2
0.8V
DDa
0.8VDDa
0.2V
DDa
0.8V
DDa
0.2V
DDa
0.2V
DDa
th2
ts1
th1
ts3
Symbol
ts1
th1
ts2
th2
ts3
fk
SSI setup time, activated by the rising edge of SSK
SSI hold time, activated by the rising edge of SSK
SSK setup time, activated by the rising edge of SEN
SSK hold time, activated by the rising edge of SEN
SEN setup time, activated by the rising edge of SSK
SSK frequency
20
20
20
20
20
7.5
ns
ns
ns
ns
ns
MHZ
Definition Min. Typ. Max. Unit
– 10 –
CXD2457R
4) FRI and HRI loading characteristics
tsSYNC thSYNC
0.5VDDa
0.5VDDa
0.5V
DDa
FRI, HRI
MCK
MCK load capacitance = 10pF (Within the recommended operating conditions)
Symbol
tsSYNC
thSYNC
FRI and HRI setup time, activated by the rising edge of MCK
FRI and HRI hold time, activated by the rising edge of MCK
5
5
ns
ns
Definition Min. Typ. Max. Unit
3) Output timing characteristics using DSGAT and RST
DSGAT, RST
EXP, XCPDM, XCPOB
PBLK, XSHP, XSHD, XRS,
RG, H1, H2
tpRST
twRST
0.5V
DDa
0.5VDDa
0.5VDDa, b, c, d
H1 and H2 load capacitance = 180pF
EXP, XCPDM, PBLK, XSHP, XSHD, XRS and RG load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpRST
twRST
Time until the above outputs reach the specified value after
the fall of DSGAT and RST
RST and DSGAT pulse width
10
75 ns
ns
Definition
Min. Typ.
Max. Unit
– 11 –
CXD2457R
5) Output variation characteristics of ID, WEN, EXP, FRO and HRO
tpdEXP
tpdSYNCO
0.5V
DDa
0.5VDDa
0.5V
DDaMCK
EXP, ID, WEN
FRO, HRO
EXP, ID and WEN load capacitance = 10pF (Within the recommended operating conditions)
Symbol
tpdEXP
tpdSYNCO
Time until the WEN, ID and EXP outputs change after the
fall of MCK
Time until the FRO and HRO outputs change after the fall
of MCK
0.5
1.0
8.5
11.5nsns
Definition Min. Typ. Max. Unit
– 12 –
CXD2457R
Data
D00
to
D07
CHIP
Chip switching
See D00 to D07
CHIP.
All 0
D08
to
D10
CTGRY
Category switching
See D08 to D10
CTGRY.
All 0
D11
to
D31
DATA
Control data for each category
The meaning of this CTGRY control data
differs according to the category set by D08 to
D10.
See D11 to D31
DATA.
All 0
D32
to
D39
Checksum bits
Checksum bits
See D32 to D39
CHKSUM.
All 0
Symbol
Function
When reset
Description of Operation
1. Progressive Scan CCD drive pulse generation
• Combining this IC with a crystal oscillator generates a fundamental frequency of 30.0MHz.
• CCD drive pulse generation is synchronized with HRI and FRI.
• The CCD drive method can be changed to various modes by inputting serial data or parallel data to the
CXD2457R.
• The various drive methods possessed by the CXD2457R are shown in the Timing Charts A-1 to 4 (V rate)
and B-1 to 6 (H rate).
2. Serial data input method
• All CXD2457R operations can be controlled via the serial interface. The serial data format is as follows.
00SSI
SSK
SEN
01 02 03 04 05 06 33 34 35 36 37 38 39
Serial data format
Serial data
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