Sony CXD2453Q Datasheet

Timing Generator for LCD Panels

For the availability of this product, please contact the sales office.

Description

The CXD2453Q is a timing signal generator for driving the LCX017AL and LCX023AL LCD panels. This chip outputs timing signals which support XGA signals (1024 × 768 dots) and S-XGA signals (1280 × 1024 dots).

Features

• Supports various XGA signals (1024 × 768 dots)

having horizontal scanning frequencies of 44-69kHz

and vertical scanning frequencies of 55 to 85Hz.

• Supports S-XGA (1280 × 1024 dots) pulse

eliminator (horizontal scanning frequency of 69kHz

or less).

• Controls the sample-and-hold position of the

CXA2112R sample-and-hold driver.

• Line inversion and field inversion signal generation

• AC drive of LCD panels during no signal.

CXD2453Q

80 pin QFP (Plastic)

Absolute Maximum Ratings (VSS = 0V)

• Supply voltage VDD VSS – 0.5 to +4.0 V

• Input voltage VI

(3.3V input pin) VSS – 0.5 to VDD + 0.5 V (5.0V input pin) VSS – 0.5 to VDD + 2.5 V

• Output voltage VO VSS – 0.5 to VDD + 0.5 V

• Storage temperature

Tstg –55 to +125 °C

Applications

LCD projectors, etc.

Structure

Silicon gate CMOS IC

Note: Company names and product names, etc.

contains in these materials are the trademarks or registered trademarks of the respective companies.

Recommended Operating Conditions

• Supply voltage VDD +3.0 to +3.6 V

• Operating temperature

Topr –20 to +75 °C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E97425B7Y-PS

Block Diagram

78

XCLR

TST5

24

VSYNC HSYNC

28 29

3

Direct Clear

SYNC DETECTOR

XCKI1

CKI1

4

Master Clock

(Main)

SLCK1

26

11

CKI2

21

CKI3

XCKI3

22

SLCK2

CKI4

13

30

Master Clock

(Sub)

AUX V COUNTER

CXD2453Q

9

TST2

34

TST7

35

TST8

36

TST9

74

TST11

75

TST12 TST13

76

SLHR HRET

IRACT

CLP1 CLP2

ENB PRG PCG

HCK1 HCK2

HST

17 38 69

39 40 47 48 49 51 53 55

PLL COUNTER

H POSITION COUNTER

H TIMING GENERATOR

V POSITION COUNTER

V TIMING GENERATOR

LINE CONTROLLER

ADDITIONAL PULSE GENERATOR

43

19

41 44 45

15 16

27

72 79 80

67

68

70

1

BLK

SLFR VCK VST FRP

TST1 TST3 TST4 TST6 TST10 TST14 TST15

XVS

XHS

ORACT

SCLK

SDAT

SCTL

18

DD

6

7

SERIAL DATA I/F

8

56

57

SHPA

58

SHPB

59

SHPC

60

SHPD

INV

61

VB

62

HB

64

65

DWN

66

XRGT

RGT

12

5

2

10

ss

V

14

23

20

ss

V

25

37

31

ss

V

50

42

ss

V

52

63

71

54

ss

V

77

ss

V

32

VDD

33

VDD VDD

46

73

VDD

ss

V

– 2 –

Pin Description

CXD2453Q

Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

Symbol I/O Description

TST1 VSS

—

Test pin (Not connected.)

—

GND

CKI1

I

Master clock input 1 (differential)

XCKI1 VSS SCLK SDAT SCTL TST2 VSS CKI2 VSS CKI4 VSS TST3

—

GND

I

Serial data clock input

I

Serial data input

I

Serial data control signal input

—

Test pin (connect to GND)

—

GND

I

Master clock input 2

—

GND

I

Master clock input 4

—

GND

—

Test pin (Not connected.)

Input pin for

open status

— —

—

— — — — — — — — — —

— 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

TST4 SLHR VDD SLFR VSS CKI3 XCKI3 VSS TST5 VSS SLCK1 TST6 VSYNC HSYNC SLCK2 VSS VDD

—

Test pin (Not connected.)

I

Reset by HSYNC of PLL counter (High: Disabled, Low: Enabled)

—

Power supply

I

FRP polarity inversion cycle selection (High: Field inversion, Low: Line inversion)

—

GND

I

Master clock input 3 (differential)

—

GND

—

Test pin (Not connected.)

—

GND

I

Clock input selection 1 (High: CKI2, Low: CKI1)

—

Test pin (Not connected.)

I

Vertical sync signal input

I

Horizontal sync signal input

I

Clock input selection 2 (High: CKI4, Low: CKI3)

—

GND

—

Power supply

—

H

—

L

—

L — — —

L — —

33 34 35 36

VDD TST7 TST8 TST9

—

Power supply

—

Test pin (connect to VDD)

—

Test pin (connect to VDD)

—

Test pin (connect to VDD)

— — — —

– 3 –

CXD2453Q

No.

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Symbol I/O Description

VSS HRET CLP1 CLP2 VCK VSS BLK VST FRP VDD ENB PRG PCG VSS HCK1

—

GND

O

Phase comparison pulse output

O

Pedestal clamp pulse 1 output

O

Pedestal clamp pulse 2 output

O

V clock pulse output

—

GND

O

BLK pulse output

O

V start pulse output

O

AC drive inversion pulse output

—

Power supply

O

ENB pulse output

O

PRG pulse output

O

PCG pulse output

—

GND

O

H clock 1 pulse output

Input pin for

open status

— — — — — — — — — — — — — —

— 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

VSS HCK2 VSS HST SHPA SHPB SHPC SHPD INV VB HB VSS DWN XRGT RGT XVS XHS

—

GND

O

H clock 2 pulse output

—

GND

O

H start pulse output

O