Sony CXD2450R Datasheet

Timing Generator for Progressive Scan CCD Image Sensor

Description

The CXD2450R is a timing generator IC which generates the timing pulses for performing progressive scan readout for digital still camera and personal computer image input applications using the ICX098AK CCD image sensor.

This chip has a built-in vertical driver.

Features

• Base oscillation frequency 36.81MHz (2340fH)

• Monitoring readout allowed

• High-speed/low-speed electronic shutter function

• Horizontal driver for CCD image sensor

• Vertical driver for CCD image sensor

• Signal processor IC system clock generation

1170fH, 780fH

• Vertical/horizontal sync (SSG) timing generation

Applications

• Digital still cameras

• Personal computer image input

Structure

Silicon gate CMOS IC

Pin Configuration

Absolute Maximum Ratings

• Supply voltage VDD VSS – 0.5 to +7.0 V

VM VL – 0.5 to +26.0 V VH VL – 0.5 to +26.0 V VL VL – 0.5 to +26.0 V

• Input voltage VI VSS – 0.5 to VDD + 0.5 V

• Output voltage VO VSS – 0.5 to VDD + 0.5 V

• Operating temperature

Topr –20 to +75 °C

• Storage temperature Tstg –55 to +150 °C

Recommended Operating Conditions

• Supply voltage

VDDa, VDDb, VDDc, VDDd 3.0 to 3.6 V

VM 0.0 V VH 14.5 to 15.5 V VL –5.0 to –6.0 V

• Operating temperature Topr –20 to +75 °C

Applicable CCD Image Sensors

ICX098AK (Type 1/4 CCD)

– 1 –

E97819A9X

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD2450R

48 pin LQFP (Plastic)

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

2627

28

29

30

40

39

38

37

36

35

34

31

32

33

41 42

43 44 45 46 47 48

1

OSCI

3MCK

V

SS

1

WEN

TEST

V

DD

1

XCLPOB

H1

V

SS

2

RG

V

DD

2

V

SS

5

CLD

FRI

HRI

HRO

FRO

EBCKSM

SEN

SSK

SSI

V

DD

6

RST

OSCO

VL

VSUB

V1

V2b

V2a

V3

VM

MCK

DSGAT

H2

V

DD3

V

DD4

XSHP

XSHD

V

SS4

1/2MCK

ID

V

SS

3

XCLPDM

XRS

V

DD5

PBLK

VH

3/2MCK

∗

Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.

– 2 –

CXD2450R

Block Diagram

40

34

31

33

H1

RG

FRI

HRI

HRO

FRO

H2

41

42

43

44

46

Latch

1/2

1/3

3

4

7

15

21

WEN

XCLPDM XCLPOB ID

PBLK

Latch

1/2

1/390

1/525

SSG

32

9

8

10

12

13

11

14

XSHP

XSHD

XRS

17

18

19

16

20

39

38

35

45

47

48

1

OSCI

3MCK

CLD

1/2MCK

OSCO

MCK

3/2MCK

23

1/2

22

24 26

6

V

DD1

V

DD5

V

DD6

2

36

V

SS1

V

SS5

V Driver

HRI

differential

Pulse Generator

Register

SSI

SSK

SEN

30

EBCKSM

37

DSGAT

TEST

5

RST

25

27

28

29

V1 V2a V2b V3 VSUB VH VM VL

V

SS

4

V

DD

4

V

SS

2

V

DD

2

V

SS

3

V

DD

3

– 3 –

CXD2450R

Pin Description

Pin No.

1 2

3

4 5

6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21

22

23 24 25 26

27 28 29

30

3MCK Vss1

WEN

ID TEST

VDD1 XCLPOB VDD2

RG Vss2 Vss3 H1 H2 VDD3 XCLPDM VDD4 XSHP XSHD XRS Vss4 PBLK

1/2MCK

3/2MCK VDD5 RST VDD6

SSI SSK SEN

EBCKSM

I

—

O

I

—

O

—

O — —

O

O —

O

O —

O

O —

I

—

I I I

I

Internal main clock. (2340fH) GND Memory write timing.

Stop control possible using the serial interface data. Vertical direction line identification pulse output.

Stop control possible using the serial interface data. IC test pin; normally fixed to GND. (With pull-down resistor)

3.3V power supply. (Power supply for common logic block) CCD optical black signal clamp pulse output.

Stop control possible using the serial interface data.

3.3V power supply. (Power supply for RG) CCD reset gate pulse output. (780fH) GND GND CCD horizontal register clock output. (780fH) CCD horizontal register clock output. (780fH)

3.3V power supply. (Power supply for H1/H2) CCD dummy signal clamp pulse output.

3.3V power supply. (Power supply for CDS system) CCD precharge level sample-and-hold pulse output. (780fH) CCD data level sample-and-hold pulse output. (780fH) Sample-and-hold pulse output for analog/digital conversion phase alignment. (780fH) GND Pulse output for horizontal and vertical blanking interval pulse cleaning. Horizontal direction pixel identification pulse output.

Stop control possible using the serial interface data. System clock output for signal processing IC. (1170fH)

Stop control possible using the serial interface data.

3.3V power supply. (Power supply for common logic block) Internal system reset input. High: Normal status, Low: Reset status

Always input one reset pulse after power-on.

3.3V power supply. (Power supply for common logic block) Serial interface data input for internal mode settings. Serial interface clock input for internal mode settings. Serial interface strobe input for internal mode settings. CHKSUM enable. (With pull-down resistor)

High: Sum check invalid, Low: Sum check valid

Symbol I/O Description

– 4 –

CXD2450R

31

32 33

34 35 36

37

38 39 40 41 42 43 44 45 46 47 48

FRO

HRO HRI

FRI CLD VSS5

DSGAT

MCK VM V1 V3 V2a VH V2b VSUB VL OSCO OSCI

O

I I

O

—

I

O

—

O O O

—

O O

—

O

I

Vertical sync signal output. Stop control possible using the serial interface data.

Horizontal sync signal output. Stop control possible using the serial interface data.

Horizontal sync signal input. Vertical sync signal input. Clock output for analog/digital conversion IC. (780fH)

Phase adjustment in 60° units possible using the serial interface data. GND Control input used to stop drive pulse generation for CCD image sensor,

sample-and-hold IC and analog/digital conversion IC. High:Normal status,Low:Stop status Controlled pulse can be changed using the serial interface data.

System clock output for signal processor IC. (780fH) GND (GND for vertical driver) CCD vertical register clock output. (Binary output) CCD vertical register clock output. (Binary output) CCD vertical register clock output. (Ternary output)

15.0V system power supply. (Power supply for vertical driver) CCD vertical register clock output. (Ternary output) CCD electronic shutter pulse output. –5.5V system power supply. (Power supply for vertical driver) Inverter output for oscillation. Inverter input for oscillation.

Pin No.

Symbol I/O Description

– 5 –

CXD2450R

Electrical Characteristics

DC Characteristics

(Within the recommended operating conditions)

Item Supply voltage 1 Supply voltage 2 Supply voltage 3 Supply voltage 4 Supply voltage 5 Supply voltage 6 Supply voltage 7

Input voltage 1

∗1

∗1 , ∗2

Input voltage 2

Input voltage 3

∗2

Output voltage 1

Output voltage 2

Output voltage 3

Output voltage 4

Output voltage 5

Output voltage 6

Output voltage 7

Output voltage 8

Output voltage 9

Output voltage 10

VDD2 VDD3 VDD4 VDD1, VDD5, VDD6 VH VM VL RST, DSGAT,

SSI, SSK, SEN, FRI, HRI

EBCKSM

TEST

RG

H1, H2

XSHP, XSHD, XRS, PBLK, XCLPDM

3/2MCK, MCK, CLD

1/2MCK

XCLPOB, ID, WEN

FRO, HRO

VSUB

V1, V3

V2a, V2b

VDDa VDDb VDDc VDDd VH VM VL

VIH1 VIL1

VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2

VOH3 VOL3

VOH4 VOL4 VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 VOH8 VOL8 VOM9 VOL9 VOH10 VOM101 VOM102 VOL10

3.0

14.5 —

–6.0

0.8VDDd

0.7VDDd

VDDa – 0.8

VDDb – 0.8

VDDc– 0.8

VDDd – 0.8

VH – 0.25

VM – 0.25

VH – 0.25

VM – 0.25

3.3

15.0

0.0

–5.5

3.6

15.5 —

–5.0

0.2VDDd

0.3VDDd

0.4

VL + 0.25

VM + 0.25

VL + 0.25

V V V V V V V

V V

V V V V V V V V

V V

V V V V V V V V V V V V V V V V

Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –10.4mA Pull-in current where IOL = 7.2mA

Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA

Feed current where IOH = –10.4mA Pull-in current where IOL = 7.2mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –2.4mA Pull-in current where IOL = 4.8mA Feed current where IOH = –3.6mA Pull-in current where IOL = 7.2mA Feed current where IOH = –4.0mA Pull-in current where IOL = 5.4mA Feed current where IOM = –5.0mA Pull-in current where IOL = 10.0mA Feed current where IOH = –7.2mA Pull-in current where IOM = 5.0mA Feed current where IOM = –5.0mA Pull-in current where IOL = 10.0mA

Pins

Symbol

Conditions Min. Typ. Max. Unit

∗1

These input pins do not have protective diodes on the internal power supply side.

∗2

These input pins have internal pull-down resistors.

∗3

The above table indicates the condition for 3.3V drive of low voltage drive blocks.

– 6 –

CXD2450R

Inverter I/O Characteristics for Oscillation

(Within the recommended operating conditions)

Item

Logical Vth Input voltage

Output voltage

Feedback resistor Oscillation

frequency

OSCI

OSCO

OSCI, OSCO OSCI, OSCO

LVth VIH VIL

VOH

VOL RFB f

0.7VDDd

VDDd/2

500k

20

VDDd/2

2M

0.3VDDd

VDDd/2

5M

50

V V V

V

Ω

MHz

Feed current where IOH = –6.0mA

Pull-in current where IOL = 6.0mA

VIN = VDDd or Vss

Pins Symbol Conditions Min. Typ. Max. Unit

Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment

(Within the recommended operating conditions)

Item

Logical Vth

Input voltage

Input amplification

3MCK

LVth VIH VIL VIN

0.7VDDd

0.3

VDDd/2

0.3VDDd

V V V

Vp-p

fmax 50MHz sine wave

Pins Symbol Conditions Min. Typ. Max.

Unit

∗1

Input voltage is the input voltage characteristics for direct input from an external source. Input amplification is the input amplification characteristics in the case of input through capacitor.

Switching Characteristics

(VH = 15.0V, VM = GND, VL = –5.5V)

Item

TTLM TTMH TTLH TTML TTHM TTHL VCLH VCLL VCMH VCML

— — — — — — — — — —

150 150

50 100 150

50

—

300 300 100 200 300 100

1.0

ns ns ns ns ns ns

V V V V

VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL

Symbol Conditions Min. Typ. Max.

Unit

∗1

The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge.

∗2

For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND.

Rise time

Fall time

Output noise voltage

– 7 –

CXD2450R

Switching Waveforms

10%

90% 90%

TTLH TTHL

90%

TTLM

90%

10%

TTML

TTLM TTML

90%

10%

TTMH TTHM

90%

10%

90%

10%

VSUB

V1 (V3)

V2a (V2b)

VH

VM

VL

VM

VL

VH

VL

Waveform Noise

VH

VL

VCML

VCMH

VCLLVCLH

– 8 –

CXD2450R

Measurement Circuit

Serial interface data

C6

C6 C6

C4 C5

C3

R2

R1

R1 R1

R1

C1 C1

C1

C2

+3.3V –5.5V

+15.0V

3MCK

R1: 68W C1: 450pF C4: 30pF R2: 15W C2: 2200pF C5: 100pF

C3: 500pF C6: 10pF

C5

C2

C1

36 25

37

48

24

13

1

12

– 9 –

CXD2450R

AC Characteristics

1) AC characteristics between the serial interface clocks

0.8VDDd

0.2V

DDd

0.2V

DDd

0.2V

DDd

0.8V

DDd

th1ts1

th2ts2

ts3

SSI

SSK

SEN

(Within the recommended operating conditions)

Symbol

ts1 th1 ts2 th2 ts3

SSI setup time, activated by the rising edge of SSK SSI hold time, activated by the rising edge of SSK SSK setup time, activated by the rising edge of SEN SSK hold time, activated by the rising edge of SEN SEN setup time, activated by the rising edge of SSK

20 20 20 20 20

ns ns ns ns ns

Definition Min. Typ. Max. Unit

2) Serial interface clock internal loading characteristics

FRI

HRI

Example: During recording drive mode

0.2VDDd

HRI

V2a

0.8VDDd

th4

ts4

SEN

0.2VDDd

V2a

Enlarged view

Note) Be sure to maintain a constantly high SEN logic level near the falling edge of HRI immediately before

the readout period.

Symbol

ts4 th4

SEN setup time, activated by the falling edge of HRI SEN hold time, activated by the falling edge of HRI

0 0

ns ns

Definition Min. Typ. Max. Unit

(Within the recommended operating conditions)