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– 1 –
CXD2437TQ
E96319A95-PS
Timing Generator for Progressive Scan CCD Image Sensor
Description
The CXD2437TQ is an IC developed to generate
the timing pulses required by the Progressive Scan
CCD image sensors as well as signal processing
circuits.
Features
• External trigger function
• Electronic shutter function
• Supports non-interlaced operation
• 12 frames/s. Double-speed readout (24 frames/s)
is also possible by mixing two vertical pixels.
• Base oscillation 40.490496MHz
Applications
Progressive Scan CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX085AK, ICX085AL
Absolute Maximum Ratings
• Supply voltage VDD Vss – 0.5 to +7.0 V
• Input voltage VI Vss – 0.5 to VDD + 0.5 V
• Output voltage VO Vss – 0.5 to VDD + 0.5 V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage VDD 4.75 to 5.25 V
• Operating temperature
Topr –20 to +75 °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
64 pin TQFP (Plastic)
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CXD2437TQ
Block Diagram
18
19
21
22
23
25
26
27
30
31
32
51
52
53
BUSY
CL
CLD1
CKO
WEN
ID
PBLK
XCPDM
XCPOB
XRS1
XSHD1
XSHP1
RG
XH2
XH1
XV1
XV2
XV3
V
DD
XSUB
OSCO
OSCI
V
SS
INT
XSG
ESG
TRIG
STDBY
XGRST
VD
HD
STRB
DCLK
DATA
11
13
14
RM
FSE
SMDE
36
35
34
46
47
48
56
57
58
59
61
62
4
1/2
64
CKI
2
1
20
28
33
42
54
63
10
24
29
37
41
50
55
60
3
9
6
7
8
TG
PULSE GENERATOR
REGISTER
DECODE
COUNTER
GATE
CLD2
38
39
49
40
XRS2
XSHD2
XSHP2
TEST1
TEST2
TEST3
TEST4
5
12
15
16
Pin Configuration (Top View)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
40
39
38
37
36
35
34
33
4142
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
63
64
61
62
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
CLD2
BUSY
VSS
CL
CLD1
CKO
V
DD
VSS
XGRST
STDBY
TRIG
ESG
V
SS
HD
VD
V
DD
CKI
WEN
ID
NC
NC
NC
V
DD
V
SS
XRS2
XSHD2
XSHP2
V
SS
PBLK
XCPDM
XCPOB
V
DD
XRS1
XSHD1
XSHP1
V
SS
VDD
RG
XH2
XH1
V
SS
XV1
XV2
XV3
V
DD
XSUB
XSG
CH
OSCO
OSCI
V
SS
INT
TEST1
STRB
DCLK
DATA
V
SS
V
DD
RM
TEST2
FSE
SMDE
TEST3
TEST4
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– 3 –
CXD2437TQ
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
OSCO
OSCI
VSS
INT
TEST1
STRB
DCLK
DATA
VSS
VDD
RM
TEST2
FSE
SMDE
TEST3
TEST4
CH
XSG
XSUB
VDD
XV3
XV2
XV1
VSS
XH1
XH2
RG
VDD
VSS
XSHP1
XSHD1
XRS1
VDD
XCPOB
O
I
—
I
I
I
I
I
—
—
I
I
I
I
I
I
—
O
O
—
O
O
O
—
O
O
O
—
—
O
O
O
—
O
Inverter output for oscillation.
Inverter input for oscillation.
GND
Switching for base oscillation input (with pull-up resistor).
High: Oscillation provided by the internal oscillation cell, Low: CKI input valid
Test (with pull-up resistor). Fix to high.
Shutter speed setting (with pull-up resistor).
Shutter speed setting (with pull-up resistor).
Shutter speed setting (with pull-up resistor).
GND
Power supply.
Switching for frame rate (with pull-up resistor).
High: Normal readout mode, Low: Double-speed readout mode
Test (with pull-up resistor). Fix to high.
Switching for external trigger discharge operation (with pull-up resistor).
High: High-speed discharge, Low: No high-speed discharge
Switching for readout timing (with pull-up resistor).
High: ESG setting invalid, Low: ESG input valid
Test (with pull-up resistor). Fix to high.
Test (with pull-up resistor). Fix to high.
Switching for color separated pulse output (with pull-up resistor).
High: Normal pulse output mode, Low: Color separated pulse output mode
Sensor charge readout pulse output.
CCD discharge pulse output.
Power supply.
Clock output for vertical CCD drive.
Clock output for vertical CCD drive.
Clock output for vertical CCD drive.
GND
Clock output for horizontal CCD drive.
Clock output for horizontal CCD drive.
Reset gate pulse output.
Power supply.
GND
Sample-and-hold pulse output.
Sample-and-hold pulse output.
Sample-and-hold pulse output.
Power supply.
Clamp pulse output.
Symbol I/O Description
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35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
– 4 –
CXD2437TQ
XCPDM
PBLK
VSS
XSHP2
XSHD2
XRS2
VSS
VDD
NC
NC
NC
ID
WEN
BUSY
CLD2
VSS
CL
CLD1
CKO
VDD
VSS
XGRST
STDBY
TRIG
ESG
VSS
HD
VD
VDD
CKI
O
O
—
O
O
O
—
—
O
O
O
O
—
O
O
O
—
—
I
I
I
I
—
I
I
—
I
Clamp pulse output.
Blanking cleaning pulse output.
GND
Sample-and-hold pulse output.
Sample-and-hold pulse output.
Sample-and-hold pulse output.
GND
Power supply.
Line identification output.
Write enable output.
Trigger mode flag.
AD conversion pulse output.
GND
Clock output (1616fH).
AD conversion pulse output.
Clock output (3232fH).
Power supply.
GND
Resets all internal FF. Low: Reset (with pull-up resistor).
Always input one reset pulse after power–on.
Standby (with pull-up resistor).
High: Normal, Low: Internal clock supply stopped
External trigger input (with pull-up resistor).
External readout input (with pull-up resistor).
GND
Horizontal sync signal input.
Vertical sync signal input.
Power supply.
Clock input (valid when INT = low).
Pin
No.
Symbol I/O Description
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CXD2437TQ
Electrical Characteristics
1. DC Characteristics
(VDD = 4.75 to 5.25V, Topr = –20 to +75°C)
Item
Supply voltage
Input voltage 1
(Input pins other than those listed below)
Input voltage 2
(Pin 2)
Output voltage 1
(Output pins other than those listed below)
Output voltage 2
(Pins 30, 31, 32, 38, 39, 40, 49, 51, 52 and 53)
Output voltage 3
(Pins 25, 26 and 27)
Output voltage 4
(Pin 1)
Feedback resistor
Pull-up resistor
Pull-down resistor
Current consumption
VDD
VIH1
VIL1
VIH2
VIL2
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
RFB
RPU
RPD
IDD
IOH = –2.5mA
IOL = 4.5mA
IOH = –5.0mA
IOL = 9.0mA
IOH = –7.5mA
IOL = 13.5mA
VIN = VSS or VDD
VIL = 0V
VIH = VDD
VDD = 5V
4.75
0.7VDD
0.7VDD
VDD – 0.4
VDD – 0.4
VDD – 0.4
VDD/2
5.0
1M
50k
50k
60
5.25
0.3VDD
0.3VDD
0.4
0.4
0.4
VDD/2
100k
100k
V
V
V
V
V
V
V
V
V
V
V
V
V
Ω
Ω
Ω
mA
Symbol
Conditions Min. Typ. Max. Unit
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CXD2437TQ
2. AC Characteristics
1) Waveform characteristics of XH1, XH2 and RG
XH1
0.9VDD
0.1VDD
tWH1 tRH1tFH1
XH2
0.9VDD
0.1VDD
tWH2 tFH2tRH2
RG
0.1VDD
0.9VDD
tWRG tFRGtRRG
(VDD = 5.0V, Topr = 25°C, load capacitance of XH1 and XH2 = 30pF, load capacitance of RG = 10pF)
tRH1
tFH1
tWH1
tRH2
tFH2
tWH2
tRRG
tFRG
tWRG
XH1 rise time
XH1 fall time
XH1 low level time
XH2 rise time
XH2 fall time
XH2 high level time
RG rise time
RG fall time
RG high level time
3
3
25
3
3
25
2
2
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol Definition Min. Typ. Max. Unit
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CXD2437TQ
2) Phase characteristics of XH1, XH2, RG, XSHP, XSHD, XRS, CL, CLD and CKO
0.5VDD
tH1
0.5VDD0.5VDDXH1
XH2 0.5VDD 0.5VDD
tPD2tPD1
RG 0.5VDD
tPD3
0.5VDD
tPD4
XSHP 0.5VDD 0.5VDD
tW1 tPD5
XSHD 0.5VDD 0.5VDD
tW2 tPD6
XRS
CLD
CL
0.5VDD
0.5VDD
0.5VDD
0.5VDD
0.5VDD
0.5VDD0.5VDD
0.5VDD
tW5
tPD11
tW4
tPD7
tPD8 tPD9
tW3
tPD10
CKO
Symbol
tH1
tPD1
tPD2
tPD3
tPD4
tPD5
tPD6
tPD7
tPD8
tPD9
tPD10
XH1 cycle
XH2 falling delay, activated by the rising edge of XH1
XH2 rising delay, activated by the falling edge of XH1
XH1 falling delay, activated by the rising edge of RG
XSHP falling delay, activated by the falling edge of RG
XSHP rising delay, activated by the rising edge of XH1
XH1 falling delay, activated by the rising edge of XSHD
CLD falling delay, activated by the falling edge of XSHD
CLD falling delay, activated by the rising edge of XRS
XRS falling delay, activated by the falling edge of CLD
CL rising delay, activated by the falling edge of CLD
49.4
0
0
4
4.5
9
3
23
21.5
9
2.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Definition Max.Typ.Min. Unit
(VDD = 5.0V, Topr = 25°C, load capacitance of CL and CKO = 30pF,
load capacitance of CLD, XSHP, XSHD, XRS and RG = 10pF)
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0.5VDD
tSETUP
0.5VDD
CL 0.5VDD
HD, VD, TRIG,
ESG
t
HOLD
Symbol
tSETUP
tHOLD
HD, VD, TRIG and ESG setup time, activated by CL
HD, VD, TRIG and ESG hold time, activated by CL
6
6
ns
ns
Definition Max.Typ.Min. Unit
(VDD = 5.0V, Topr = 25°C, load capacitance of CL = 30pF)
3) Phase conditions of HD, VD, TRIG and ESG
Symbol
tPD11
tW1
tW2
tW3
tW4
tW5
CKO rising delay, activated by the falling (rising) edge of XH1
XSHP pulse width
XSHD pulse width
CLD pulse width
CL pulse width
CKO pulse width
2.5
21
20
21
25
11.5
ns
ns
ns
ns
ns
ns
Definition Max.Typ.Min. Unit
3) Phase conditions of HD, VD, TRIG and ESG
0.3VDD
tWRST
0.3VDD
XGRST
(Within the recommended operating condition)
Symbol
tWRST
XGRST pulse width 50 ns
Definition Max.Typ.Min. Unit
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tPDCL1
0.5VDD
CL 0.5VDD0.5VDD
tPDCL2
0.5VDD
XSG, XSUB, PBLK,
XCPDM, XCPOB
XV1, XV2, XV3
BUSY, WEN, ID
tPDCL3
0.5VDD
Symbol
tPDCL1
tPDCL2
tPDCL3
XV1, XV2 and XV3 delay, activated by the falling edge of CL
BUSY, WEN and ID delay, activated by the rising edge of CL
XSG, XSUB, PBLK, XCPDM and XCPOB delay, activated by the
rising edge of CL
30
35
30
20
20
15
ns
ns
ns
Definition Max.Typ.Min. Unit
5) Phase characteristics of XV1, XV2, XV3, XSG, XSUB, PBLK, XCPDM, XCPOB, BUSY, WEN and ID
(VDD = 5.0V, Topr = 25°C, load capacitance of CL = 30pF,
load capacitance of XV1, XV2, XV3, XSG, XSUB, PBLK, XCPDM, XCPOB, BUSY, WEN and ID = 10pF)
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CXD2437TQ
Description of Functions
1. Progressive Scan CCD drive pulse generation
• Combining this IC with a crystal oscillator generates a fundamental frequency of 40.49MHz.
• CCD drive pulse generation is synchronized with the HD and VD inputs.
• Setting the RM pin to low sets the frame rate to double-speed readout mode (24 frames/s). However, the
CCD vertical resolution is halved.
• fCL = 1616fHD, fHD = 1044fVD (normal readout mode: RM = high)
• fCL = 1616fHD, fHD = 522fVD (double-speed readout mode: RM = low)
• The various operations are performed by the TRIG and ESG inputs. (See the following items.)
<Detection timing for VD, RM, TRIG and ESG>
1
CL
65 68
HD
XH1
Detection timing for VD,
RM, TRIG and ESG
After HD input is detected, VD, RM, TRIG and ESG are detected at the rising edge of the 65th CL pulse.
However, the low level period for each pulse should be set to 1H or longer to prevent misoperation.
2. Electronic shutter
<Shutter modes>
The electronic shutter has the following four shutter modes.
• Electronic shutter off: Exposure time is 1/12s (RM = high) or 1/24s (RM = low)
• High-speed electronic shutter: Exposure time is shorter than 1/12s (RM = high) or 1/24s (RM = low)
• Low-speed electronic shutter: Exposure time is longer than 1/12s (RM = high) or 1/24s (RM = low)
<Shutter mode and speed setting methods>
The shutter speed is set serially using the STRB, DCLK and DATA pins. The electronic shutter mode and the
meanings of the numbers indicated by D0 to 10 vary according to the SMD1 and SMD2 settings of the internal
register.
DCLK
DATA
STRB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 SMD1 SMD2