Sony CXD2434TQ Datasheet

CXD2434TQ

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Timing Generator for Progressive Scan CCD Image Sensor

Description

The CXD2434TQ is an IC developed to generate
the timing pulses required by the Progressive Scan
CCD image sensors as well as signal processing
circuits.

Features

• External trigger function

• Electronic shutter function

• Supports non-interlaced operation

• 30 frames/s

• Built-in driver for the horizontal (H) clock

• Base oscillation 1560 fH (24.5454 MHz)

Applications

Progressive Scan CCD cameras

Structure

Silicon gate CMOS IC

Applicable CCD Image Sensors

ICX084AK, ICX084AL

Absolute Maximum Ratings (Ta = 25 °C)

• Supply voltage VCC VSS –0.5 to +7.0 V

• Input voltage VI VSS –0.5 to VDD +7.0 V

• Output voltage VI VSS –0.5 to VDD +7.0 V

• Operating temperature

• Storage temperature

Recommended Operating Conditions

• Supply voltage VDD 4.75 to 5.25 V

• Operating temperature

48 pin TQFP (Plastic)

Topr –20 to +75 °C

Tstg –55 to +150 °C

Topr –20 to +75 °C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

—1—

E95605-TE

Block Diagram

CXD2434TQ

RG

H1
H2

XSHP

XSHD

XRS

XV1
XV2
XV3

XSG

CLD

CL

CKO

10
13
14
21
22
23
18
17
16
19
39
38
40

BUSY

WEN

ID

PULSE GENERATOR

1/2

TG

PBLK

XCPOB

XCPDM

VD

HD

WM

STDBY

REGISTER

DECODE

COUNTER

GATE

SMDE

252629313233343536 424647

FSE

11

28

48

41

3
4

5
7
8

9

PS
STRB
DCLK
DATA
SMD1
SMD2

XSUB

TEST1

TEST2

TEST3

Pin Configuration (Top View)

SS

V

CL

CLD

CKO

TEST3

STDBY

TRIG

ESG

EFS

HD
VD

1 2 6

EFS

ESG

TRIG

OSCI

OSCO

ID

37

BUSY

WEN

PBLK

XCPDM

XCPOB

CXD2434TQ

12 15 20 24 27 3743 44 45 30

DD

V

TEST1

SS

V

SS

V

SS

V

DD

WM

V

DD

V

SMDE

2536

SS

V

FSE

24

SS

V

DD

V

SS

V
XRS
XSHD
XSHP

VDD
XSG
XV1
XV2
XV3
VSS
H2

SS

V

TEST2

48

1

OSCO

OSCI

PS

STRB

DCLK

—2—

13

H1

12

SS

V

DATA

SMD1

RG

SMD2

XSUB

DD

V

Pin Description

Pin No. Symbol I/O Description

CXD2434TQ

1
2

3
4

5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25

26
27

28
29
30

31
32
33
34
35
36
37
38
39

OSCO

OSCI

PS

STRB
DCLK

VSS
DATA
SMD1
SMD2

RG
XSUB

VDD

H1
H2

VSS

XV3
XV2
XV1

XSG

VDD
XSHP
XSHD

XRS

VSS

FSE

SMDE

VSS

TEST1

WM

VDD

XCPDM

XCPOB

PBLK

ID

WEN

BUSY

VSS

CL

CLD

O

Inverter output for oscillation.

I

Inverter input for oscillation.
Switching for electronic shutter speed input method. (With pull-up resistor)

I

Low: Serial input, High: Parallel input

I

Shutter speed setting. (With pull-up resistor)

I

Shutter speed setting. (With pull-up resistor)

—

GND

I

Shutter speed setting. (With pull-up resistor)

I

Shutter mode setting. (With pull-up resistor)

I

Shutter mode setting. (With pull-up resistor)

O

Reset gate pulse output.

O

CCD discharge pulse output.

—

Power supply.

O

Clock output for horizontal CCD drive.

O

Clock output for horizontal CCD drive.

—

GND

O

Clock output for vertical CCD drive.

O

Clock output for vertical CCD drive.

O

Clock output for vertical CCD drive.

O

Sensor charge readout pulse output.

—

Power supply.

O

Sample-and-hold pulse output.

O

Sample-and-hold pulse output.

O

Sample-and-hold pulse output.

—

GND
Switching for external trigger discharge operation. (With pull-up resistor)

I

Low: No high-speed discharge, High: High-speed discharge
Switching for readout timing. (With pull-up resistor)

I

Low: ESG input valid, High: ESG input invalid

—

GND

I

Test. (With pull-down resistor)
WEN mode setting. (With pull-down resistor)

I

Low: Effective line, High: XSG synchronization

—

Power supply.

O

Clamp pulse output.

O

Clamp pulse output.

O

Blanking cleaning pulse output.

O

Line identification output.

O

Write enable output.

O

Trigger mode flag output.

—

GND

O

780 fH clock output.

O

AD conversion pulse output.

—3—

Pin No. Symbol I/O Description

CXD2434TQ

40
41

42
43

44
45
46
47
48

CKO

TEST3

STDBY

TRIG

ESG

EFS

HD
VD

TEST2

O

1560 fH clock output.

I

Test. (With pull-up resistor)
Standby. (With pull-up resistor)

I

Low: Internal clock supply stopped, High: Normal

I

External trigger input. (With pull-up resistor)

I

External readout input. (With pull-up resistor)

I

Vertical CCD discharge input. (With pull-up resistor)

I

Horizontal sync signal input.

I

Vertical sync signal input.

I

Test. (With pull-up resistor)

Note) Pins with built-in pull-up or pull-down resistors should be connected to VDD or VSS in locations with high

noise.

Electrical Characteristics

1. DC Characteristics VDD = 4.75 V to 5.25 V Topr = –20 to +75 °C
Item

Supply voltage
Input voltage 1
(Input pins other than those listed below)
Input voltage 2
(Pin 2)
Output voltage 1
(Output pins other than those listed below)
Output voltage 2
(Pins 21, 22, 23, 38, 39 and 40)
Output voltage 3
(Pin 10)
Output voltage 4
(Pins 13 and 14)
Output voltage 5
(Pin 1)
Feedback resistor
Pull-up resistor
Pull-down resistor
Current consumption

Symbol

VDD
VIH1
VIL1
VIH2

VIL2
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
VOH5
VOL5

RFB

RPU

RPD

IDD

Conditions

IOH = –2.5 mA
IOL = 4.5 mA
IOH = –5.0 mA
IOL = 9.0 mA
IOH = –7.5 mA
IOL = 13.5 mA
IOH = –14.0 mA
IOL = 24.0 mA

VIN = VSS or VDD
VIL = 0 V
VIH = VDD
VDD = 5 V

Min.

4.75

0.7 VDD

0.7 VDD

VDD–0.4

VDD–0.4

VDD–0.4

VDD–0.4

VDD/2

Typ.

5.0

1 M
50 k
50 k

40

Max.

5.25

0.3 VDD

0.3 VDD

0.4

0.4

0.4

0.4

VDD/2

100 k
100 k

Unit

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

Ω
Ω
Ω

mA

—4—

2. AC Characteristics

1) Waveform characteristics of H1, H2 and RG

0.9VDD

H1

0.1VDD

tRH1 tWH1 tFH1

0.9VDD

H2

0.1VDD

tFH2 tWH2 tRH2

CXD2434TQ

Symbol

tRH1
tFH1

tWH1

tRH2

tFH2
tWH2
tRRG
tFRG

tWRG

0.9VDD

RG

0.1VDD

tRRG tWRG tFRG

VDD = 5.0 V, Topr = 25 °C, load capacitance of H1 and H2 = 100 pF, load capacitance of RG = 10 pF

Definition
H1 rise time
H1 fall time
H1 high level time
H2 rise time
H2 fall time
H2 low level time
RG rise time
RG fall time
RG high level time

Min.

25

25

10

Typ.

6
5

35

6
5

35

2
2

15

Max.

15
15

15
15

5
5

20

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns

—5—

2) Phase characteristics of H1, H2, RG, XSHP, XSHD, XRS, CL, CLD and CKO

tH1

CXD2434TQ

H1

H2

RG

XSHP

XSHD

XRS

CLD

CL

0.5VDD 0.5VDD 0.5VDD

tPD3 tPD1 tPD2

0.5VDD0.5VDD

tW1

0.5VDD 0.5VDD

tPD10

tW4

0.5VDD

tPD5tPD4

0.5VDD 0.5VDD
tPD7

tPD8

tW3

0.5VDD

tW5

tW2

0.5VDD0.5VDD

tPD9

0.5VDD0.5VDD

0.5VDD0.5VDD

tPD6

CKO

0.5VDD

0.5VDD

0.5VDD

tW5

0.5VDD

tPD11tPD11

VDD = 5.0 V, Topr = 25 °C, load capacitance of CL and CKO = 30 pF, load capacitance of CLD, XSHP, XSHD, XRS and RG = 10 pF

Symbol

tH1
tPD1
tPD2
tPD3
tPD4
tPD5
tPD6
tPD7
tPD8
tPD9

tPD10
tPD11

tW1

tW2

tW3

tW4

tW5

H1 cycle
H2 rising delay, activated by the falling edge of H1
H2 falling delay, activated by the rising edge of H1
H1 rising delay, activated by the rising edge of RG
XSHP falling delay, activated by the falling edge of RG
H1 falling delay, activated by the rising edge of XSHP
H1 rising delay, activated by the rising edge of XSHD
CLD falling delay, activated by the falling edge of XSHD
CLD falling delay, activated by the rising edge of XRS
XRS falling delay, activated by the falling edge of CLD
CL falling delay, activated by the rising edge of H1
H1 rising (falling) delay, activated by the rising edge of CKO
XSHP pulse width
XSHD pulse width
CLD pulse width
CL pulse width
CKO pulse width

Definition

Min.

–5
–5
–5
–2
–7
–5
–5
17

0
–5
–5
13
15
17
38
17

Typ.

82

0
0
0
4
2
2
2

22

8
0

2
18
20
22
41
20

Max.

5
5
5

10

7
7

7
27
15

5

7
23
25
27
45
24

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

—6—

3) Phase conditions of HD, VD, TRIG, EFS and ESG

CXD2434TQ

CL

HD, VD, TRIG,
EFS, ESG

0.5VDD 0.5VDD

0.5VDD

tSETUP

tHOLD

VDD = 5.0 V, Topr = 25 °C, load capacitance of CL = 30 pF

Symbol
tSETUP
tHOLD

HD, VD, TRIG, EFS and ESG setup time, activated by CL
HD, VD, TRIG, EFS and ESG hold time, activated by CL

Definition

Min.

20

5

Typ. Max. Unit

4) Phase characteristics of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID

CL

0.5VDD

0.5VDD

ns
ns

tPDCL1

XV1, XV2, XV3

BUSY, WEN, ID

XSG, PBLK,
XCPDM, XCPOB

tPDCL2

0.5VDD

tPDCL3

0.5VDD

0.5VDD

VDD = 5.0 V, Topr = 25 °C, load capacitance of CL = 30 pF,
load capacitance of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID = 10 pF

Symbol

tPDCL1
tPDCL2

tPDCL3

XV1, XV2 and XV3 delay, activated by the falling edge of CL
BUSY, WEN and ID delay, activated by the rising edge of CL
XSG, PBLK, XCPDM and XCPOB delay, activated by the
rising edge of CL

Definition

Min.

30
40

40

Typ. Max.

65
60

55

Unit

ns
ns

ns

—7—

Description of Functions

1.Progressive Scan CCD drive pulse generation

• Combining this IC with a crystal oscillator generates a fundamental frequency of 24.5454 MHz.

• CCD drive pulse generation is synchronized with the HD and VD inputs.

Set fCL to 780 fHD and fHD to 525 fVD.

• The various operations are performed by the TRIG, EFS and ESG inputs. (See the following items.)

<Detection timing for VD, TRIG, EFS and ESG>

CL

1

HD

H1

Detection timing for VD,

TRIG, EFS and ESG

35

T1

CXD2434TQ

After HD input is detected, the status of VD, TRIG, ESG and EFS is detected during T1.
Do not change the status of VD, TRIG, ESG and EFS during T1.
When input is from a non-synchronized system, the low level period for each pulse should be set to 63.5 µs or
longer to prevent misoperation.

—8—

CXD2434TQ

2.Electronic shutter
<Shutter modes>
The electronic shutter has the following four shutter modes.

• Electronic shutter off: Exposure time is 1/30 s.

• High-speed electronic shutter: Exposure time is shorter than 1/30 s.

• Low-speed electronic shutter: Exposure time is longer than 1/30 s.

• Flickerless: Exposure time is 1/50 s. This is a special feature of the high-speed

electronic shutter, and reduces flicker from fluorescent lights, etc. in areas
with 50 Hz power supply

<Shutter mode and speed setting methods>
PS = Low: Serial input; set by the STRB, DCLK and DATA pins. The SMD1 and SMD2 pins are not used.
PS = High: Parallel input; set by the STRB, DCLK, DATA, SMD1 and SMD2 pins.

2-1. [Serial input]

Serial input is set by the STRB, DCLK and DATA pins. The electronic shutter mode and the meanings of the
numbers indicated by D0 to 9 vary according to the SMD1 and SMD2 setting of the internal register.

STRB

DCLK

SMD2 SMD1

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Mode
Electronic shutter off (1/30 s accumulation)
High-speed electronic shutter
Low-speed electronic shutter

D0 to 9

—

Number of exposed lines (Note 1)

Number of exposed frames (Note 2)

SMD1

H

L

H

DATA

SMD2

H
H

L

Note 1) Relationship between the number of exposed lines and the exposure time

The relationship between the number of exposed lines and the exposure time is as follows.
(Exposure time) = (Number of exposed lines) x (One horizontal scan period) + (Accumulation time for
the readout lines)
In this formula, one horizontal scan period equals the HD falling interval, and the accumulation time for
the readout lines is the time from the rising edge of XSUB to the rising edge of XSG (456 bits). Also,
(Number of exposed lines) should be set to greater than 1 but less than 524.

Note 2) The number of exposed frames should be set to greater than 1 but less than 1023. However, when

the number of exposed frames is 1 and SMDE is set to high, external trigger mode does not function.

Timing Chart (Serial input)

STRB

DCLK

DATA

tWD tSDS tWS

tSDD tHDD

—9—