Sony CXD2422R Datasheet
CCD Camera Timing Generator
Description
The CXD2422R generates the timing pulses
required for driving and signal processing CCDs with
480,000 pixels (EIA, effective pixels) and CCDs with
570,000 pixels (CCIR, effective pixels).
Features
• EIA and CCIR compatible
• Compatible with component digital and composite
digital recording format
• Compatible with field/frame accumulation modes
Applications
CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX062/063AL
Block Diagram
D0
D2
D1
2
3
Delay
1514
D3
4
V latch
16
Pulse Generation Circuit
Internal clock
Delay
19
18
SD
SC
LD
HTSG
FLD/FRM
EIA/CCIR
MODE
CLKI
30
31
32
Shutter data
58
61
62
63
33
51
Shift
Register
13
Latch
94
Reset
High-speed
Pulse
Generation
Circuit
34
SDO
1
Latch
XH gate
CXD2422R
64 pin LQFP (Plastic)
Absolute Maximum Ratings
• Supply voltage VDD VSS – 0.5 to +7.0 V
• Input voltage VI VSS – 0.5 to VDD + 0.5 V
• Output voltage VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage VDD 4.5 to 5.5 V
• Operating temperature
Topr –20 to +75 °C
VD
HD
6
5
39
XSG1
38
XSG2
44
XV1
XV2
43
XV3
42
41
35
26
22
21
28
27
XV4
XSUB
HCLP1
HCLP2
VCLP
PBLK
PBLKON
Output
F.F.
7
37
53
54
20
36
52
CLKO
SHP
BAI
BAO
SHD
BBI
BBO
XRG
BCI
BCO
XH1
XH2
CLK
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94Y30-ST
Pin Configuration
CXD2422R
NC
NC
SDO
BCO
BCI
XRG
VSS
VDD
NC
HTSG
RST
TEST12
49
50
51
52
53
54
55
56
58
59
57
60
TEST11
48
TEST10
47
TEST9
46
TEST8
45
44
XV1
43
XV2
XV3
SS
XV4
V
XSG1
XSG2
40
4142
39
38
37
XH1
36
XH2
35
XSUB
CLKO
34
33
CLKI
32
31
30
29
28
27
26
25
24
23
22
21
LD
SC
SD
TEST7
PBLK
PBLKON
HCLP1
TEST6
VDD
SS
V
HCLP2
VCLP
FLD/FRM
EIA/CCIR
MODE
TEST13
61
62
63
64
BBO
20
BBI
19
SHD
18
NC
17
6
1
2
3
D0
D1
D2
5
4
D3
VD
HD
7
CLK
9
8
SS
V
10
TEST1
11
TEST2
TEST3
12
TEST4
13
TEST5
14 15
SHP
BAI
16
BAO
– 2 –
Pin Description
Pin No. Symbol I/O Description
CXD2422R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
D0
D1
D2
D3
VD
HD
CLK
VSS
TEST1
TEST2
TEST3
TEST4
TEST5
SHP
BAI
BAO
(NC)
Extended I/O output.
O
Extended I/O output.
O
Extended I/O output.
O
Extended I/O output.
O
Vertical sync signal input. (With pull-up resistor)
I
Horizontal sync signal input. (With pull-up resistor)
I
Two frequency divider output of Pin 33.
O
—
Test input (normally Low). (With pull-down resistor)
I
Test input (normally Low). (With pull-down resistor)
I
Test input (normally Low). (With pull-down resistor)
I
Test input (normally Low). (With pull-down resistor)
I
Test input (normally Low). (With pull-down resistor)
I
CCD output precharge level sampling pulse output.
O
Buffer input (for phase adjustment of SHP). (With pull-up resistor)
I
Non-inversed output of BAI.
O
—
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
SHD
BBI
BBO
VCLP
HCLP2
VSS
VDD
TEST6
HCLP1
PBLKON
PBLK
TEST7
SD
SC
LD
CLKI
CLKO
CCD output signal level sampling pulse output.
O
Buffer input (for phase adjustment of SHD). (With pull-up resistor)
I
Non-inversed output of BBI.
O
Vertical clamp pulse output.
O
Horizontal (dummy bit block) clamp pulse output.
O
—
—
Test input (normally High). (With pull-up resistor)
I
Horizontal (OPB block) clamp pulse output.
O
Output ON/OFF of PBLK. (High: ON) (With pull-up resistor).
I
Preblanking pulse output.
O
Test input (normally High). (With pull-up resistor)
I
Serial data input for electronic shutter control. (With pull-up resistor)
I
Clock input for electronic shutter control. (With pull-up resistor)
I
Latch pulse input for electronic shutter control. (With pull-up resistor)
I
Clock input.
I
Inversed output of CLKI.
O
35
36
37
XSUB
XH2
XH1
Substrate pulse output for electronic shutter.
O
Clock output for horizontal register drive.
O
Clock output for horizontal register drive.
O
– 3 –
Pin No. Symbol I/O Description
CXD2422R
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
XSG2
XSG1
VSS
XV4
XV3
XV2
XV1
TEST8
TEST9
TEST10
TEST11
(NC)
(NC)
SDO
BCO
BCI
XRG
Sensor charge readout pulse output.
O
Sensor charge readout pulse output.
O
—
Clock output for vertical register drive.
O
Clock output for vertical register drive.
O
Clock output for vertical register drive.
O
Clock output for vertical register drive.
O
Test output (normally open).
O
Test output (normally open).
O
Test output (normally open).
O
Test output (normally open).
O
—
—
Serial data output for electronic shutter control.
O
Non-inversed output of BCI.
O
Buffer input (for phase adjustment of XRG). (With pull-up resistor)
I
Reset gate pulse output of output block.
O
55
56
57
58
59
60
61
62
63
64
VSS
VDD
(NC)
HTSG
RST
TEST12
FLD/FRM
EIA/CCIR
MODE
TEST13
—
—
—
Readout pulse (XSG1, 2) ON/OFF. (High: OFF) (With pull-down resistor)
I
Test input (normally High). (With pull-up resistor)
I
Test input (normally Low). (With pull-up resistor)
I
High: Field accumulation mode, Low: Frame accumulation mode.
I
(With pull-up resistor)
High: EIA, Low: CCIR. (With pull-up resistor)
I
High: Component digital mode, Low: Composite digital mode.
I
(With pull-up resistor)
Test input (normally Low). (With pull-up resistor)
I
Note) TEST12 and TEST13 have a built-in pull-up resistor.
Be sure to fix them at Low.
– 4 –
CXD2422R
Electrical Characteristics
1) DC characteristics (VDD = 4.5 to 5.5V, Topr = –20 to +75°C)
Item
Supply voltage
Input/Output voltages
Symbol
VDD
VI, VO
Conditions Min. Typ. Max. Unit
VIH
Input voltage
VIL
VOH
IOH = –2mA
Output voltage
Pull-up/
Pull-down resistors
VOL
RPU,
RPD
IOL = 4mA
VIL = 0V, VIH = VDD
2) AC characteristics
2)-1. Pulses for electronic shutter control (SD, SC, LD)
SD
4.5
VSS
0.7VDD
VDD – 0.8
40k
5.0
100k
5.5
VDD
0.3VDD
0.4
250k
V
V
V
V
V
V
Ω
Symbol
ts1
tH1
tw1
ts2
tH2
tw2
ts1 t
SC
LD
H1
tw1
ts2 t
Item Min.
SD set-up time, activated by the rising edge of SC
SD hold time, activated by the rising edge of SC
SC pulse width
SC set-up time, activated by the rising edge of LD
SC hold time, activated by the rising edge of LD
LD pulse width
H2
tw2
20ns
20ns
20ns
20ns
20ns
20ns
– 5 –
2)-2. HD/VD take-in characteristics
CXD2422R
HD, VD
CLK
1.6V 1.6V
Symbol
ts3
th3
HD/VD set-up time, activated by CLK
HD/VD hold time, activated by CLK
2)-3. Field discrimination characteristics
DD
0.7V
ts3 th3
(VDD = 4.5 to 5.5V, Topr = –20 to +75°C)
Definition Min. Typ. Max. Unit
4
0
ns
ns
VD
HD
1.6V
tpd1
When the HD logic level is Low tpd1 after
VD falls, the field is discriminated as an
ODD (EVEN with CCIR) field.
Symbol
tpd1
Field discriminating clock phase, activated by the falling edge of VD 890 ns
VD
HD
1.6V
tpd1
When the HD logic level is High tpd1 after
VD falls, the field is discriminated as an
EVEN (ODD with CCIR) field.
(VDD = 4.5 to 5.5V, Topr = –20 to +75°C)
Definition Min. Typ. Max. Unit
– 6 –
2)-4. CLKO, CLK, XH1, XH2, XRG, SHP, SHD phase characteristics
CLKI
CXD2422R
CLKO
CLK
XH1
XH2
XRG
SHP
SHD
tpd2
tpd4
tpd6
tpd8
tpd10
tpd14
tpd3
tpd5
tpd7
tpd9
tpd11
tpd12
tpd13
tpd15
(VDD = 4.5 to 5.5V, Topr = –20 to +75°C, load capacitance = 10pF)
Symbol Definition Min. Typ. Max. Unit
tpd2
tpd3
CLKO falling delay time against CLKI
CLKO rising delay time against CLKI
3.5
4.0
6.2
7.2
12.1
14.1
ns
ns
tpd4
tpd5
tpd6
tpd7
tpd8
tpd9
tpd10
tpd11
tpd12
tpd13
tpd14
tpd15
CLK2 falling delay time against CLKI
CLK2 rising delay time against CLKI
XH1 falling delay time against CLKI
XH1 rising delay time against CLKI
XH2 rising delay time against CLKI
XH2 falling delay time against CLKI
XRG falling delay time against CLKI
XRG rising delay time against CLKI
SHP rising delay time against CLKI
SHP falling delay time against CLKI
SHD falling delay time against CLKI
SHD rising delay time against CLKI
5.2
6.5
5.2
6.4
5.7
5.3
4.7
5.2
8.1
7.9
7.9
8.6
9.3
11.6
8.8
11.4
10.2
9.4
8.4
9.2
14.4
14.1
14.1
15.2
18.3
22.8
17.2
22.4
20.3
18.5
16.5
18.1
28.3
27.6
27.6
29.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
– 7 –
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