Sony CXD2412AQ Datasheet

Timing Generator for LCD Panels

Description

The CXD2412AQ is a timing signal generator for

LCD panel drivers.

Features

• Generates the LCX007 drive pulse.

• Supports NTSC/PAL. (With PAL, a video signal on which scanning line conversion has been performed is used.)

• Supports WIDE.

• Supports HD (20 MHz band).

• Supports Muse-NTSC conversion signal (MNDC).

• Supports up/down and/or right/left inversion.

• Supports three-panel projector.

• Generates timing signal of external sample-andhold circuit.

• Generates line inversion and field inversion signals.

• AC drive for LCD panel during no signal.

• AFC circuit supporting static and dynamic fluctuations.

CXD2412AQ

100 pin QFP (Plastic)

Applications

LCD projectors

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings (Ta = 25 °C)

• Supply voltage

• Input voltage

• Output voltage

• Operating temperature

• Storage temperature

Recommended Operating Conditions

•

Supply voltage

•

Operating temperature

VDD VSS–0.5 to +7.0 V VI VSS – 0.5 to VDD + 0.5V VO VSS – 0.5 to VDD + 0.5V Topr –20 to +75 °C Tstg –55 to +150 °C

VDD 5.0 ± 0.5 V Topr –20 to +75 °C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94Y04-ST

Block Diagram

CXD2412AQ

RPD1 RPD2 RPD3

FPD1 FPD2 FPD3

TC1 TC2 TC3

HSYNC

N.C.

N.C. CKI1 CKI2 CKI3

CKO1 CKO2 CKO3

VSYNC

TST6 TST1 TST2 TST3 TST4 TST5

XCLR

VP1 VP2 VST

SLAUX

V

SS0 SS1

V

SS2

V

SS3

V V

SS4 SS5

V

SS6

V

SS7

V

SS8

V

SS10 SS11

V

SS12

V

DD0

V

DD1

V V

DD2 DD3

V

DD4

V

DD5

V

86 94

83 97

82 98 16

12 89 92 11 88 91 17 14 24 25 26 27 30 31 49 50 46

10 13 15 29 40

65 79 87 90

28 35 53

78

73

54

93

70

9

LOOP

6

FILTER

PHASE

COMPARATOR

5

PLL-COUNTER

2 1

H-SYNC

DETECTOR

H-SKEW

HALF-H

KILLER

DETECTOR

FIELD & LINE

CONTROLLER

V-SYNC

SEPERATER

(NOISE SHAPE)

V-TIMING

PULSE GENERATOR

4

H-TIMING

PULSE

GENERATOR

3

84 95

85 96 48 51 52 55 56 57 58 59 60 75 32 47 33 61 18 19 20

22 23 74

72 81 99

100

36 37 38 39 34

42 43 44 45 62 63 64

67 68 69 76 77 80

7

8

21

71

41

66

PEO1 PEO2 PEO3 PWM1 PWM2 PWM3 N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. SLFR RGT DWN XRGT FRP HP1 HP2 HP3 HP4 HP5 HP6 PCGW SLSH1 SLSH2 SLSH3 CP1 CP2 HCK1A HCK2A HCK1B HCK2B HSTA HSTB CLR ENB VCK PCG XCLP1 XCLP2 PRG SH1 SH2 SH3 SH4 NTPL XWD XHD

– 2 –

Pin Description

CXD2412AQ

Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

Symbol N.C.

N.C. VDD0 VSS0 TC1 FPD1 PEO1 PWM1 RPD1 VSS1 CKO1 CKI1 VSS2 TST6 VSS3

I/O

Not connected

—

Not connected

—

Power supply

—

GND

—

FPD1 pin pulse width adjustment

I

Phase comparator output B-1 (for NTSC/PAL)

O

Loop filter integrator output 1

O

Loop filter integrator input 1

I

Phase comparator output A-1 (for NTSC/PAL)

O

GND

—

NTSC/PAL oscillation cell output

O

NTSC/PAL oscillation cell input

I

GND

—

Test

I

GND

—

Description

Input pin for open

status

L

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

HSYNC VSYNC HP1 HP2 HP3 HP4 HP5 HP6 TST1 TST2 TST3 TST4 VDD1 VSS4 TST5 XCLR RGT

Hsync input (negative polarity)

I

Vsync input (negative polarity)

I