Sony CXD2093Q Datasheet

Digital Comb Filter (NTSC)

Description

The CXD2093Q is an adaptive intra-field three lines comb filter for NTSC systems, and can provide high-precision Y/C separation with a single chip.

Features

• Adaptive intra-field three lines comb filter

• For NTSC

• Vertical enhancer

• Horizontal aperture correction

• 8-bit A/D converter (1-channel)

• 8-bit D/A converter (2-channel)

• 4× PLL

• Sync tip clamp

Applications

Y/C separation for color TVs and VCRs

Structure

Silicon gate CMOS ICStructure

Absolute Maximum Ratings (Ta = 25°C, VSS = 0V)

• Supply voltage DVDD VSS – 0.5 to +7.0 V

DAVD VSS – 0.5 to +7.0 V ADVD VSS – 0.5 to +7.0 V PLVD VSS – 0.5 to +7.0 V CLVD VSS – 0.5 to +7.0 V

• Input voltage VI VSS – 0.5 to VDD + 0.5 V

• Output voltage VO VSS – 0.5 to VDD + 0.5 V

• Storage temperature

Tstg –55 to +150 °C

Recommended Operating Conditions

• Supply voltage DVDD 5.0 ± 0.25 V

DAVD 5.0 ± 0.25 V ADVD 5.0 ± 0.25 V PLVD 5.0 ± 0.25 V CLVD 5.0 ±0.25 V

• Analog input ADIN 1.75 Vp-p

• Operating temperature

Topr –20 to +70 °C

– 1 –

E99537-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD2093Q

48 pin QFP (Plastic)

– 2 –

CXD2093Q

Pin Configuration

Block Diagram

FIN

CKSL

PLSL

MCKO

ADCK

CPO

PLVS

VCV

PLVD

CLVD

CLPEN

CLVS

DV

SS

DVSS

VEH1

VEH2

VEH3

MOD1

DV

SS

MOD2

DV

DD

TEST

VB

IRF

DV

SS

TEST

DV

DD

TEST

TRAP

APCN

DV

SS

TEST

DV

DD

DV

SS

DV

SS

CLPO

ADIN

RB

ADVS

ADVD

RT

ACO

DAVD

AYO

DAVS

VG

VRF

2

3

4

5

6

9

10

11

121

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

8

7

A/D

Clamp

1H DL

Logical operation

Adaptive

filter

operation

DL D/A

ADIN

D/A

CLPO

AYO

ACO

VCO 1/4

SW

Phase

comparator

1/2

SW

4fsc

CPO VCV PLSL FIN CKSL

Vertical

enhancement circuit

2

1

7

9

39

38

37

44

42

1H DL

– 3 –

CXD2093Q

Pin Description

CLPO

ADIN RB ADVS ADVD RT

ACO

DAVD

AYO

DAVS VG VRF

IRF VB TEST

DVDD DVSS

VEH3 VEH2 VEH1 DVSS DVSS DVSS DVSS DVDD

O

I

O — —

O

—

O

—

O

I

O

I — —

I

I — — — — —

1

2 3 4 5 6

7

8

9

10 11 12

13 14 15

16 18

20 21 22 23 24 25 26 27

Internal clamp circuit current output. Connect to ADIN when using the internal clamp. Leave this pin open when not in use.

Comb filter analog input (A/D converter input). Reference bottom voltage for the A/D converter (0.52V typ.). A/D converter analog ground. A/D converter analog power supply. (5.0V) Reference top voltage for the A/D converter (2.60V typ.). Analog chroma signal output.

Output can be obtained by connecting a resistor between this pin and the analog ground.

D/A converter analog power supply. (5.0V) Analog luminance signal output.

Output can be obtained by connecting a resistor between this pin and the analog ground.

D/A converter analog ground. D/A converter related pin. Connect a capacitor of approximately 0.1µF between

this pin and the analog power supply (DAVD). Sets the full-scale value of the Y and C-channel D/A converter output signal. Connect a resistor of “16R” (16 times the output resistor “R” of the D/A converter). D/A converter related pin.

Connect to the analog ground (DAVS) via a capacitor of approximately 0.1µF. Test pin. Normally fix to “Low”. Digital power supply. (5.0V) Digital ground. Y/C separation mode setting. MOD2 MOD1

L L Adaptive processing mode H L BPF separation mode H H Through mode

Vertical enhancement setting. Can be set in 8 stages from VEH3 VEH2 VEH1: LLL (off) to HHH (max.)

Digital ground. Digital ground. Digital ground. Digital ground. Digital power supply. (5.0V)

No.

Symbol I/O Description

17

19

MOD2

MOD1

I

– 4 –

CXD2093Q

28 29 30 31 32 33 34 35 36

37

38

39

40 41 42 43 44 45 46 47 48

Test pin. Normally fix to “Low”. Digital ground. Horizontal aperture correction circuit setting. Low: Off, High: On. Trap filter setting. Low: Off, High: On. Test pin. Normally open or fix to “Low”. Test pin. Normally open or fix to “Low”. Digital power supply. (5.0V) Test pin. Normally open or fix to “Low”. Digital ground. Clock input. Input the burst-locked fsc (2fsc) when using the internal PLL.

Input the burst-locked 4fsc when not using the internal PLL. PLL control.

Low: The internal PLL is not used. The clock (4fsc) which is input to FIN is

supplied internally.

High: The internal PLL is used. VCO oscillation output 4fsc clock is supplied

internally.

Selects the clock input to FIN. Low: fsc, High: 2fsc. When inputting 4fsc to FIN (when not using the internal PLL), this pin may be set to either “Low” or “High”.

Clock (4fsc) output. Clock input for A/D converter. Normally connect to MCKO. PLL phase comparator output. Leave open when not using the PLL. PLL analog ground. VCO control voltage input. Connect to PLVS when not using the PLL. PLL analog power supply. (5.0V) Clamp D/A converter analog power supply. (5.0V) Clamp circuit enable pin. Low: Clamp on, High: Clamp off. Clamp D/A converter analog ground.

Pin No.

Symbol I/O Description

I

—

I I I I

—

I

—

I

O

I

O

—

I — —

I —

TEST DVSS APCN TRAP TEST TEST DVDD TEST DVSS

FIN

CKSL

PLSL

MCKO ADCK CPO PLVS VCV PLVD CLVD CLPEN CLVS

– 5 –

CXD2093Q

Electrical Characteristics

DC Characteristics (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +70°C)

∗1

All pins

∗2

All pins other than

∗6

∗3

All input pins other than

∗6

∗4

All output pins other than

∗5

CPO (Pin 42)

∗6

FIN (Pin 37)

∗7

All input pins other than

∗8

Pins 32, 33 and 35

∗9

MCKO (Pin 40)

Supply voltage —

4.75

–20

—

Vss

0.7VDD

0

VDD – 0.8

0.5

250k

–10

40

3.0

DVDD DAVD ADVD PLVD CLVD Topr IDD VI, VO VIH VIL

tr, tf

VOH

VOL

VIN RFB IIL, IIH IIH

—

5.0

85

1M

100

9.0

5.25

+70 120 VDD

0.3VDD 500

0.4

2.5M 10

240

18.0

V

°C

mA

V

ns

V

Vp-p

Ω

µA

ns

∗1

—

∗2

∗3

∗1 ∗4 ∗5 ∗4 ∗5

∗6

∗7 ∗8 ∗9

Operating temperature Supply current Input/output voltage

Input voltage

Input rise/fall time

Output voltage

Clock input amplitude Feedback resistance value

Input leak current

Clock amplifier output delay

—

Clock 14.3MHz

—

CMOS level input

— IOH = –2mA IOH = –3mA IOL = 4mA IOL = 1.5mA fmax = 50MHz sine wave VIN = Vss or VDD VIN = Vss or VDD VIH = VDD

—

Applicable pins

Item

Symbol

Measurement

conditions

Min. Typ. Max. Unit