Sony CXD2027R, CXD2027Q Datasheet

DBS Audio Signal Processor

For the availability of this product, please contact the sales office.

CXD2027Q/R

Description

The CXD2027Q/R are audio signal processors
designed for DBS applications. These LSIs perform
all digital processing from QPSK demodulation to
analog audio output on a single chip.

Features

QPSK and PCM demodulators and DAC output
are configured on a single chip.

Descrambler interface according to the COATEC
system and SkyPort system .

Functions

QPSK demodulator

• Carrier, clock and data regeneration

• ALC and VCXO adjustment-free

PCM demodulator

• Frame sync protection by correlation detection

• De-interleaving and descrambling

• BCH error correction, range bit error correction

• Audio data range control
Expansion from 10 to 14 bits in A mode
Upper bit majority correction in B mode

• Control sign integration correction, chargeable

flag integration correction by master frame
synchronization

• Interface output for external DAC

• Digital interface output

1-bit DAC output

• Quadruple oversampling filter

• Digital de-emphasis circuit

• 1-bit stereo DAC with 2nd-order ∆∑ format noise

shaper

S/N ratio : 90dB (Typ.)
Distortion: 0.011% (Typ.)

CPU interface

•I2C bus

Descrambler interface

• COATEC system, SkyPort system

Mute functions

• Error occurrence frequency detection mute

• Audio chargeable flag detection mute

• Control sign (B7) detection mute

CXD2027Q

64 pin QFP (Plastic)

Structure

Silicon gate CMOS IC

Applications

TVs, VCRs with built-in BS tuners

Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)

• Supply voltage VDD Vss – 0.5 to +7.0 V

• Input voltage VI Vss – 0.5 to VDD + 0.5V

• Output voltage VO Vss – 0.5 to VDD + 0.5V

• Storage temperature Tstg –55 to +150 °C

Operating Conditions

• Supply voltage VDD 4.75 to 5.25 V

• Operating temperature Topr –20 to +75 °C

CXD2027R

80 pin LQFP (Plastic)

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E94808-ST

CXD2027Q/R

DATB

DATA

DATO

DSLA

13

MUTE
54

&

SHIFTER

BCH (7, 3)

RANGE BIT

GENERATOR

MUTE SIGNAL

8
9

(63, 56)

BCH DECODER

7

ERROR

MAJORITY

CORRECTION

10 → 14 BIT

DATA EXPAND

LPO
28

CLOCK GENERATOR

32

25

DAC1

DAC2

DE-ENPHASIS

DIGITAL FILTER

35

43

44

AUDIO

INTERFACE

DIGITAL

INTERFACE

LRCK

AUD

RNO

RPO

LNO

BCLK
45

F256
46

15

38

Note) Pin numbers are for the CXD2027R.

TX

SASL

NSYN

BITI

DSLB

BITO

48

DE-SCRAMBLER

AUDIO DATA

INTERPOLATOR

C BUS I/F

2

I

4 kBIT-RAM

DE-INTERLEAVER

FRAME SYNC

5

6

4

DATA

RECOVERY

ADC

SYNC

MASTER FRAME

ALC SIGNAL

GENERATOR

INTEGRAL

CORRECTION

8TH RANGE BIT

INTEGRAL

CORRECTION

CONTROL WORD

CARRIER

RECOVERY

GENERATOR

SYSTEM CLOCK

TIMING

GENERATOR

CLOCK

RECOVERY

51

50

47

14

11

12

56

SCLK

SDA

DTUP

CC1

CK2M

FRAM

MCKO

Block Diagram

71
RT

73

ADIN

76
RB

77

GR

67

ALCO

– 2 –

66

PHAA

65

M23I

64

M23O

58

PHAB

57

MCKI

Pin Configuration 1
CXD2027Q

CXD2027Q/R

DD5

V

M23O

M23I
PHAA
ALCO

SS9

V

TST7

RT

ADIN
ADVD
ADVS

RB

GR

SCLK

SDA

3

DD

V

DTUP

NSYN

F256

BCLK

4

DD

V

PHAB

MCKI

8

SS

V

MCKO

TST8

MUTE

7

SS

V

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

52
53
54
55
56
57
58
59
60
61
62
63
64

1 2 3 4 5 6 7 8 9 10111213141516171819

TST0

0

SS

V

MRST

BITO

BITI

DSLB

DSLA

DATB

DATA

0

DD

V

CK2M

FRAM

CC1

DATO

TX

LRCK

TST2

AUD

TST3

TST6

TST4

SASL

TST5

32
31
30
29
28
27
26
25
24
23
22
21
20

SS6

V

SS5

V
RNO

DD2

V
RPO

SS4

V
TST1

SS3

V
LPO
V

DD1

LNO

SS2

V

SS1

V

– 3 –

Pin Configuration 2
CXD2027R

CXD2027Q/R

N.C.
N.C.

DD5

V

M23O

M23I
PHAA
ALCO

SS9

V

N.C.

TST7

RT

N.C.

ADIN
ADVD
ADVS

RB

GR

TST0

N.C.
N.C.

N.C.

4

DD

V

PHAB

MCKI

8

SS

V

MCKO

TST8

MUTE

7

SS

V

SCLK

SDA

3

DD

V

DTUP

NSYN

F256

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

BCLK

LRCK

AUD

TST6

41

N.C.

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

N.C.
N.C.
SASL

SS6

V
V

SS5

RNO
N.C.

DD2

V
RPO

SS4

V
TST1
VSS3
LPO

DD1

V
N.C.
LNO
V

SS2
SS1

V
N.C.
N.C.

1 2 3 4 5 6 7 8 9 10111213141516171819

N.C.

0

SS

V

MRST

BITO

BITI

DSLB

DSLA

DATB

DATA

0

DD

V

CK2M

DATO

FRAM

CC1

TX

TST2

TST3

TST4

20

TST5

N.C.

– 4 –

Pin Description 1
CXD2027Q (64pin QFP)

CXD2027Q/R

Pin
No.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

Symbol I/O Pin Description Remarks

TST0
MRST
VSS Digital
BITO
BITI
DSLB
DSLA
DATB
DATA
VDD Digital
CK2M
FRAM
DATO
CC1
TX

I

Test pin; normally low

I

Master reset; H: normal operation; L: reset

—

Digital ground

O

Bit stream output after PSK demodulation

I

Bit stream input after PSK demodulation

I

External descrambler pin

I

External descrambler pin

I

Data input 2 after BCH correction (for COATEC)

I

Data input 1 after BCH correction (for SkyPort)

—

Digital +5V power supply

O

2.048MHz clock output

O

Frame start bit flag

O

Data output after BCH correction

O

Control sign first bit output

O

Digital format audio output

Internal pull down

Internal pull up

TTL input
TTL input
TTL input
TTL input
TTL input

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

TST2
TST3
TST4
TST5
VSS Digital
VSS D/A
LNO
VDD D/A
LPO
VSS D/A
TST1
VSS D/A
RPO
VDD D/A
RNO
VSS D/A
VSS Digital

I

Test pin; normally low

I

Test pin; normally low

I

Test pin; normally low

I

Test pin; normally high

—

Digital ground

—

Analog ground

O

Lch D/A converter output

—

Analog +5V power supply

O

Lch D/A converter output

—

Analog ground

I

Test pin; normally low

—

Analog ground

O

Rch D/A converter output

—

Analog +5V power supply

O

Rch D/A converter output

—

Analog ground

—

Digital ground

Internal pull down
Internal pull down
Internal pull down

Internal pull down

33
34

SASL
TST6

I

I2C bus slave address select (L: D4, H: D6)

I

Test pin; normally low

– 5 –

Internal pull down
Internal pull down

CXD2027Q/R

Pin
No.

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

Symbol I/O Pin Description Remarks

AUD
LRCK
BCLK
F256
DTUP
NSYN
VDD Digital
SDA
SCLK
VSS Digital
TST8
MUTE
VSS Digital
MCKO
MCKI

O

Audio data output for external DF/DAC

O

LR clock output for external DF/DAC

O

Bit clock output for external DF/DAC

O

Clock output for external DF/DAC

O

CCUP: control sign update flag / DED: BCH 2 error detection

O

Asynchronous flag (H: asynchronous; L: synchronous)

—

Digital +5V power supply

I

SDA (I2C bus)

I

SCL (I2C bus)

—

Digital ground

I

Test pin; normally low

I

External forced muting input

—

Digital ground

O

MCKI inversion output

I

24.576MHz clock input

Switched by I2C bus

I2C bus compatible
I2C bus compatible

TTL input

50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

PHAB
VDD Digital
VDD Digital
M23O
M23I
PHAA
ALCO
VSS Digital
TST7
RT
ADIN
VDD A/D
VSS A/D
RB
GR

O

Clock regeneration phase error data output

—

Digital +5V power supply

—

Digital +5V power supply

O

M23I inversion output

I

22.909088MHz clock input

O

Carrier regeneration phase error data output

O

ALC A/D control output

—

Digital ground

I

Test pin; normally low

I

A/D converter VRT input

I

Analog data input

—

Analog +5V power supply

—

Analog ground

I

A/D converter VRB input; connect to analog ground

I

A/D converter VGR input; connect to analog ground

– 6 –

Pin Description 2
CXD2027R (80pin LQFP)

CXD2027Q/R

Pin

No.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

Symbol I/O Pin Description Remarks

N.C.
MRST
VSS Digital
BITO
BITI
DSLB
DSLA
DATB
DATA
VDD Digital
CK2M
FRAM
DATO
CC1
TX

—

Non-connection

I

Master reset; H: normal operation; L: reset

—

Digital ground

O

Bit stream output after PSK demodulation

I

Bit stream input after PSK demodulation

I

External descrambler pin

I

External descrambler pin

I

Data input 2 after BCH correction (for COATEC)

I

Data input 1 after BCH correction (for SkyPort)

—

Digital +5V power supply

O

2.048MHz clock output

O

Frame start bit flag

O

Data output after BCH correction

O

Control sign first bit output

O

Digital format audio output

Internal pull up

TTL input
TTL input
TTL input
TTL input
TTL input

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

TST2
TST3
TST4
TST5
N.C.
N.C.
N.C.
VSS Digital
VSS D/A
LNO
N.C.
VDD D/A
LPO
VSS D/A
TST1
VSS D/A
RPO

I

Test pin; normally low

I

Test pin; normally low

I

Test pin; normally low

I

Test pin; normally high

—

Non-connection

—

Non-connection

—

Non-connection

—

Digital ground

—

Analog ground

O

Lch DAC output

—

Non-connection

—

Analog +5V power supply

O

Lch DAC output

—

Analog ground

I

Test pin; normally low

—

Analog ground

O

Rch DAC output

Internal pull down
Internal pull down
Internal pull down

Internal pull down

33
34

VDD D/A
N.C.

—

Analog +5V power supply

—

Non-connection

– 7 –

CXD2027Q/R

Pin
No.

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

Symbol I/O Pin Description Remarks

RNO
VSS D/A
VSS Digital
SASL
N.C.
N.C.
N.C.
TST6
AUD
LRCK
BCLK
F256
DTUP
NSYN
VDD Digital

O

Rch D/A converter output

—

Analog ground

—

Digital ground

I

I2C bus slave address select (L: D4, H: D6)

—

Non-connection

—

Non-connection

—

Non-connection

I

Test pin; normally low

O

Audio data output for external DF/DAC

O

LR clock output for external DF/DAC

O

Bit clock output for external DF/DAC

O

Clock output for external DF/DAC

O

CCUP: control sign update flag/DED: BCH 2 error detection

O

Asynchronous flag (H: asynchronous; L: synchronous)

—

Digital +5V power supply

Internal pull down

Internal pull down

Switched by I2C bus

50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66

SDA
SCLK
VSS Digital
TST8
MUTE
VSS Digital
MCKO
MCKI
PHAB
VDD Digital
N.C.
N.C.
N.C.
VDD Digital
M23O
M23I
PHAA

I

SDA (I2C bus)

I

SCL (I2C bus)

—

Digital ground

I

Test pin; normally low

I

External forced muting input

—

Digital ground

O

MCKI inversion output

I

24.576MHz clock input

O

Clock regeneration phase error data output

—

Digital +5V power supply

—

Non-connection

—

Non-connection

—

Non-connection

—

Digital +5V power supply

O

M23I inversion output

I

22.909088MHz clock input

O

Carrier regeneration phase error data output

I2C bus compatible
I2C bus compatible

TTL input

67
68
69
70

ALCO
VSS Digital
N.C.
TST7

O

ALC A/D control output

—

Digital ground

—

Non-connection

I

Test pin; normally low

– 8 –

CXD2027Q/R

Pin
No.

71
72
73
74
75
76
77
78
79
80

Symbol I/O Description Remarks

RT
N.C.
ADIN
VDD A/D
VSS A/D
RB
GR
TST0
N.C.
N.C.

I

A/D converter VRT input

—

Non-connection

I

Analog data input

—

Analog +5V power supply

—

Analog ground

I

A/D converter VRB input; connect to analog ground

I

A/D converter VGR input; connect to analog ground

I

A/D test pin; normally low

—

Non-connection

—

Non-connection

Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)

Item

Supply voltage

Symbol Ratings Unit
VDD

Vss – 0.5 to +7.0

V

Internal pull down

Input voltage
Output voltage
Operating temperature
Storage temperature

VI
VO
Topr
Tstg

Vss – 0.5 to VDD + 0.5
Vss – 0.5 to VDD + 0.5

–20 to +75

–55 to +150

V

V
°C
°C

I/O Pin Capacitance (VDD = VI = 0V, f = 1MHz)

Item

Input pin capacitance

Output pin capacitance
Input/output pin capacitance

∗1

Input pins other than ∗2and

∗2

SCLK

∗3

BITI, DSLB, DSLA, DATB, DATA, TST5

∗4

All output pins

∗5

SDA

Symbol Min. Typ. Max. Unit Corresponding pins

pF

∗1
∗2
∗3
∗4
∗5

CIN

COUT
CI/O

9
10
11
11
10

∗3

– 9 –

CXD2027Q/R

Electrical Characteristics
[DC characteristics] (VDD = 5V ± 0.25V, Vss = 0V, Ta = –20 to +75°C)

Item

Power consumption
Input/output voltage

CMOS input

Input

TTL input

voltage

High level
Low level
Hysteresis voltage

Input rise/fall time

Output voltage

Symbol

PD
VI, VO
VIH
VIL
VIH
VIL
Vt+
Vt–
Vt+ – Vt

tr, tf

VOH
VOL
VOH
VOL
VOH
VOL

Measurement

conditions

VDD = 4.75 to 5.25V

–

IOH = –2mA
IOL = 4mA
IOH = –4mA
IOL = 4mA
IOH = –4mA
IOL = 8mA

Min. Typ. Max. Unit

180
Vss

280

350
VDD

0.7VDD

0.3VDD

2.2

0.8

0.7VDD

0.3VDD

0.5

0

500

VDD – 0.8

0.4

VDD – 0.8

0.4

VDD – 0.8

0.4

mW

V

V

ns

V

Corre-

sponding

pins

∗1

∗2

∗3

∗4

∗5

∗6

∗7

∗8

VOL
VOL

∗1

All pins

∗2

Input pins other than ∗3and

∗3

BITI, DSLB, DSLA, DATB, DATA, MUTE

∗4

SDA, SCLK

∗5

All input pins

∗6

Output pins other than ∗7, ∗8and

∗7

LNO, LPO, RPO, RNO

∗8

BITO, CK2M, FRAM, DATO, CCI, TX

∗9

SDA, SCLK

∗4

∗9

IOL = 3mA
IOL = 6mA

0
0

0.4

0.6

∗9

– 10 –